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JPS52670B2 - - Google Patents

Info

Publication number
JPS52670B2
JPS52670B2 JP48034978A JP3497873A JPS52670B2 JP S52670 B2 JPS52670 B2 JP S52670B2 JP 48034978 A JP48034978 A JP 48034978A JP 3497873 A JP3497873 A JP 3497873A JP S52670 B2 JPS52670 B2 JP S52670B2
Authority
JP
Japan
Prior art keywords
layer
photoresist
pads
leads
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP48034978A
Other languages
English (en)
Other versions
JPS499187A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS499187A publication Critical patent/JPS499187A/ja
Publication of JPS52670B2 publication Critical patent/JPS52670B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622Manufacturing methods by patterning a pre-deposited material using masks
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/1147Manufacturing methods using a lift-off mask
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/13001Core members of the bump connector
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
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    • H01L2924/01006Carbon [C]
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01015Phosphorus [P]
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    • H01L2924/01024Chromium [Cr]
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    • H01L2924/01033Arsenic [As]
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    • H01L2924/01039Yttrium [Y]
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    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/01Chemical elements
    • H01L2924/01084Polonium [Po]
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    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12036PN diode
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
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    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP48034978A 1972-03-27 1973-03-27 Expired JPS52670B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00238116A US3821785A (en) 1972-03-27 1972-03-27 Semiconductor structure with bumps

Publications (2)

Publication Number Publication Date
JPS499187A JPS499187A (ja) 1974-01-26
JPS52670B2 true JPS52670B2 (ja) 1977-01-10

Family

ID=22896575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48034978A Expired JPS52670B2 (ja) 1972-03-27 1973-03-27

Country Status (8)

Country Link
US (1) US3821785A (ja)
JP (1) JPS52670B2 (ja)
CA (1) CA984060A (ja)
DE (1) DE2314731C3 (ja)
FR (1) FR2178007B1 (ja)
GB (1) GB1377601A (ja)
IT (1) IT981659B (ja)
NL (1) NL7304183A (ja)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906541A (en) * 1974-03-29 1975-09-16 Gen Electric Field effect transistor devices and methods of making same
JPS5130673U (ja) * 1974-08-26 1976-03-05
US3959522A (en) * 1975-04-30 1976-05-25 Rca Corporation Method for forming an ohmic contact
JPS51147253A (en) * 1975-06-13 1976-12-17 Nec Corp Structure of electrode terminal
US4293637A (en) * 1977-05-31 1981-10-06 Matsushita Electric Industrial Co., Ltd. Method of making metal electrode of semiconductor device
DE3135007A1 (de) * 1981-09-04 1983-03-24 Licentia Gmbh Mehrschichtenkontakt fuer eine halbleiteranordnung
JPS59193036A (ja) * 1983-04-16 1984-11-01 Toshiba Corp 半導体装置の製造方法
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
US4742023A (en) * 1986-08-28 1988-05-03 Fujitsu Limited Method for producing a semiconductor device
US4875617A (en) * 1987-01-20 1989-10-24 Citowsky Elya L Gold-tin eutectic lead bonding method and structure
US4937006A (en) * 1988-07-29 1990-06-26 International Business Machines Corporation Method and apparatus for fluxless solder bonding
US5130779A (en) * 1990-06-19 1992-07-14 International Business Machines Corporation Solder mass having conductive encapsulating arrangement
KR960016007B1 (ko) * 1993-02-08 1996-11-25 삼성전자 주식회사 반도체 칩 범프의 제조방법
US6342442B1 (en) * 1998-11-20 2002-01-29 Agere Systems Guardian Corp. Kinetically controlled solder bonding
US6428942B1 (en) * 1999-10-28 2002-08-06 Fujitsu Limited Multilayer circuit structure build up method
US6214646B1 (en) * 2000-02-29 2001-04-10 Lucent Technologies Inc. Soldering optical subassemblies
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US20040140219A1 (en) * 2003-01-21 2004-07-22 Texas Instruments Incorporated System and method for pulse current plating
DE102004024644A1 (de) * 2004-05-18 2005-12-22 Infineon Technologies Ag Verfahren zum Aufbringen metallischer Strukturen auf Substrate und Halbleiterbauelement
US7730790B2 (en) * 2004-08-10 2010-06-08 Nordson Corporation Shear test device
DE102005055280B3 (de) * 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
TWI298204B (en) * 2005-11-21 2008-06-21 Advanced Semiconductor Eng Structure of bumps forming on an under metallurgy layer and method for making the same
WO2007093799A1 (en) * 2006-02-17 2007-08-23 Dage Precision Industries Ltd. Shear test apparatus and method
DE102008042107A1 (de) * 2008-09-15 2010-03-18 Robert Bosch Gmbh Elektronisches Bauteil sowie Verfahren zu seiner Herstellung
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
KR102430984B1 (ko) * 2015-09-22 2022-08-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10903151B2 (en) * 2018-05-23 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1196834A (en) * 1967-03-29 1970-07-01 Hitachi Ltd Improvement of Electrode Structure in a Semiconductor Device.
FR1569479A (ja) * 1967-07-13 1969-05-30

Also Published As

Publication number Publication date
FR2178007A1 (ja) 1973-11-09
JPS499187A (ja) 1974-01-26
IT981659B (it) 1974-10-10
DE2314731B2 (de) 1980-06-04
GB1377601A (en) 1974-12-18
DE2314731A1 (de) 1973-10-11
CA984060A (en) 1976-02-17
FR2178007B1 (ja) 1978-08-04
DE2314731C3 (de) 1982-10-14
NL7304183A (ja) 1973-10-01
US3821785A (en) 1974-06-28

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