JPS56111264A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS56111264A JPS56111264A JP1243780A JP1243780A JPS56111264A JP S56111264 A JPS56111264 A JP S56111264A JP 1243780 A JP1243780 A JP 1243780A JP 1243780 A JP1243780 A JP 1243780A JP S56111264 A JPS56111264 A JP S56111264A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- regions
- type
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 4
- 238000009413 insulation Methods 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To reduce parasitic capacity and enable high-speed operation by forming source and drain regions and an excelent ohmic contact without increase in the area of an element. CONSTITUTION:On a p type Si substrate 1 are formed n<+> type source and drain regions 2 and 3, a gate electrode 4 and a gate oxidized film 7, an insulation film 9 is laminated on the surface and further a resist film 17 is laminated thereon. And, according to a source-drain contact pattern, openings 200 and 300 are made in the film 17. Next, the insulation film 9 is removed by etching while the film 17 serving as a mask, and at this time, the surface of the substrate 1 or a p<+> region 13 is exposed as parts C and E. Then, a poly-Si layer 18 containing impurity of the same conductive type with those in the regions 2 and 3 is laminated on the whole surface and subjected to a heat-treatment process, whereby the impurity is diffused in the substrate 1 to n type regions 19 and 20. In this way, the layer 18 is to contact with the substrate 1 only through the intermediary of the regions 19 and 20, and thus insulation with p-n juction is obtained and a contact part can be provided without increase in the area of element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1243780A JPS56111264A (en) | 1980-02-06 | 1980-02-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1243780A JPS56111264A (en) | 1980-02-06 | 1980-02-06 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56111264A true JPS56111264A (en) | 1981-09-02 |
Family
ID=11805267
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1243780A Pending JPS56111264A (en) | 1980-02-06 | 1980-02-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56111264A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0104079A2 (en) * | 1982-09-20 | 1984-03-28 | International Business Machines Corporation | Integrated circuit contact structure |
EP0124115A2 (en) * | 1983-04-28 | 1984-11-07 | Kabushiki Kaisha Toshiba | Semiconducter ROM device and method for manufacturing the same |
JPS61501808A (en) * | 1984-04-09 | 1986-08-21 | アメリカン テレフオン アンド テレグラフ カムパニ− | How to transfer impurities from region to region in semiconductor devices |
JPH01128568A (en) * | 1987-11-13 | 1989-05-22 | Matsushita Electron Corp | Semiconductor device |
US4888297A (en) * | 1982-09-20 | 1989-12-19 | International Business Machines Corporation | Process for making a contact structure including polysilicon and metal alloys |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5353275A (en) * | 1976-10-26 | 1978-05-15 | Seiko Epson Corp | Semiconductor device |
JPS5357975A (en) * | 1976-11-06 | 1978-05-25 | Cho Lsi Gijutsu Kenkyu Kumiai | Selffmatching gate mos transistor |
-
1980
- 1980-02-06 JP JP1243780A patent/JPS56111264A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5353275A (en) * | 1976-10-26 | 1978-05-15 | Seiko Epson Corp | Semiconductor device |
JPS5357975A (en) * | 1976-11-06 | 1978-05-25 | Cho Lsi Gijutsu Kenkyu Kumiai | Selffmatching gate mos transistor |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0104079A2 (en) * | 1982-09-20 | 1984-03-28 | International Business Machines Corporation | Integrated circuit contact structure |
US4888297A (en) * | 1982-09-20 | 1989-12-19 | International Business Machines Corporation | Process for making a contact structure including polysilicon and metal alloys |
EP0124115A2 (en) * | 1983-04-28 | 1984-11-07 | Kabushiki Kaisha Toshiba | Semiconducter ROM device and method for manufacturing the same |
JPS61501808A (en) * | 1984-04-09 | 1986-08-21 | アメリカン テレフオン アンド テレグラフ カムパニ− | How to transfer impurities from region to region in semiconductor devices |
JPH01128568A (en) * | 1987-11-13 | 1989-05-22 | Matsushita Electron Corp | Semiconductor device |
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