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JPS54127245A - Integrated-circuit chip - Google Patents

Integrated-circuit chip

Info

Publication number
JPS54127245A
JPS54127245A JP3419978A JP3419978A JPS54127245A JP S54127245 A JPS54127245 A JP S54127245A JP 3419978 A JP3419978 A JP 3419978A JP 3419978 A JP3419978 A JP 3419978A JP S54127245 A JPS54127245 A JP S54127245A
Authority
JP
Japan
Prior art keywords
integrated
point
circuit chip
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3419978A
Other languages
Japanese (ja)
Inventor
Yuichi Oka
Yoshimitsu Takiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3419978A priority Critical patent/JPS54127245A/en
Priority to US06/022,949 priority patent/US4286173A/en
Publication of JPS54127245A publication Critical patent/JPS54127245A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To simplify the formation and test of the test pattern of an integrated- circuit chip at a circumference when complex integrated-circuit chips are mixing together.
CONSTITUTION: For example, when the input number is equal to output one, this is composed of main circuit part F which attains an orginal complex function, and gates G1 to G6 and terminal (a3) for control signals. At the time of an ordinary operation, a high-level input is supplied to point (a3). The output of part F is selected by selective gates G1 and G2 and outputted to (d3). Marks "o" at the inputs of G2 and G5 represent inversion. At the time function inspection, a low-level input is supplied to point (a3). As a result, an input to (b3) is selected by selective gates and then outputted to point (d3). In this logic constitution, making point (a3) low in level makes it possible to transfer easily the logical values of (b3) and (c3) to output points (d3) and (e3). Namely, the transfer of logical values can be carried out having no relation with a complex function, and the test pattern of an integrated-circuit chip at its circumference can be formed easily.
COPYRIGHT: (C)1979,JPO&Japio
JP3419978A 1978-03-27 1978-03-27 Integrated-circuit chip Pending JPS54127245A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3419978A JPS54127245A (en) 1978-03-27 1978-03-27 Integrated-circuit chip
US06/022,949 US4286173A (en) 1978-03-27 1979-03-22 Logical circuit having bypass circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3419978A JPS54127245A (en) 1978-03-27 1978-03-27 Integrated-circuit chip

Publications (1)

Publication Number Publication Date
JPS54127245A true JPS54127245A (en) 1979-10-03

Family

ID=12407487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3419978A Pending JPS54127245A (en) 1978-03-27 1978-03-27 Integrated-circuit chip

Country Status (1)

Country Link
JP (1) JPS54127245A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102172A (en) * 1985-10-29 1987-05-12 Nec Corp Logical device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102172A (en) * 1985-10-29 1987-05-12 Nec Corp Logical device

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