JPS5627667A - Method of estimating semiconductor device - Google Patents
Method of estimating semiconductor deviceInfo
- Publication number
- JPS5627667A JPS5627667A JP10422779A JP10422779A JPS5627667A JP S5627667 A JPS5627667 A JP S5627667A JP 10422779 A JP10422779 A JP 10422779A JP 10422779 A JP10422779 A JP 10422779A JP S5627667 A JPS5627667 A JP S5627667A
- Authority
- JP
- Japan
- Prior art keywords
- adjacent
- test patterns
- output pins
- circuits
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
PURPOSE: To detect a short circuit when there are a plurality of same function circuits in an integrated circuit, by dispensing with the repeated input of an identical test pattern and by making test patterns lest adjacent wirings should undergo the same change.
CONSTITUTION: When AND circuits are connected as function circuits to terminals 1W14 in an integrated circuit 10, function blocks are normally made in the same pattern. For instance, output pins 3, 4 are adjacent to each other and output pins 10, 11 are also adjacent to each other. For this reason, different test patterns are made so that output states differ from one another. Defects can be detected by the test patterns even if the output pins are short-circuited. As a result, the short circuit of wirings can be detected.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10422779A JPS5627667A (en) | 1979-08-15 | 1979-08-15 | Method of estimating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10422779A JPS5627667A (en) | 1979-08-15 | 1979-08-15 | Method of estimating semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5627667A true JPS5627667A (en) | 1981-03-18 |
Family
ID=14375067
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10422779A Pending JPS5627667A (en) | 1979-08-15 | 1979-08-15 | Method of estimating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5627667A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176339U (en) * | 1984-12-26 | 1986-11-04 | ||
| JPS61176341U (en) * | 1985-04-22 | 1986-11-04 | ||
| US6412745B1 (en) | 1997-03-06 | 2002-07-02 | Yokoyama Co., Ltd. | Fastener using metal and wooden board |
| US7812259B2 (en) | 2008-10-24 | 2010-10-12 | Southwire Company | Metal-clad cable with foraminous coded label |
| US11031157B1 (en) | 2013-08-23 | 2021-06-08 | Southwire Company, Llc | System and method of printing indicia onto armored cable |
-
1979
- 1979-08-15 JP JP10422779A patent/JPS5627667A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176339U (en) * | 1984-12-26 | 1986-11-04 | ||
| JPH057379Y2 (en) * | 1984-12-26 | 1993-02-24 | ||
| JPS61176341U (en) * | 1985-04-22 | 1986-11-04 | ||
| JPH0336671Y2 (en) * | 1985-04-22 | 1991-08-02 | ||
| US6412745B1 (en) | 1997-03-06 | 2002-07-02 | Yokoyama Co., Ltd. | Fastener using metal and wooden board |
| US7812259B2 (en) | 2008-10-24 | 2010-10-12 | Southwire Company | Metal-clad cable with foraminous coded label |
| US8344254B2 (en) | 2008-10-24 | 2013-01-01 | Southwire Company | Electrical cable with foraminous label |
| US11031157B1 (en) | 2013-08-23 | 2021-06-08 | Southwire Company, Llc | System and method of printing indicia onto armored cable |
| US11670438B2 (en) | 2013-08-23 | 2023-06-06 | Southwire Company, Llc | System and method of printing indicia onto armored cable |
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