JPH01260977A - Clamp circuit - Google Patents

Abstract

PURPOSE:To attain stable digital synchronization separation by clamping an input signal to an A/D converter to a specific voltage so as to utilize effectively the input range of an A/D conversion section. CONSTITUTION:An analog composite video signal inputted to an input terminal 1 is clamped by an amplifier 5 whose clamp level is set by a clamp level setting device 4 and the result is inputted to an A/D converter 6. A digital video signal from a delay circuit 7 is compared with a reference level (reference sink top level) by a comparator 11 and the result of comparison is outputted to an inte gration average circuit 13. The synchronizing signal component outputted from the integration average circuit 13 is converted into an analog signal by a D/A converter 15, amplified by an amplifier 17 and fed to the said clamp level setting device 4 as a correction voltage. Thus, the sink top clamp at the clamp section is attained with high accuracy at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clamp circuit that receives a composite video signal and clamps a sync top (horizontal synchronizing signal tip).

[Conventional technology]

When dealing with television signals, to prevent level fluctuations,
Analog video signals are processed with a sync top or pedestal clamp at the input section for DC reproduction. However, as the definition of television signals progresses,
Digital processing will become essential.

[Problem to be solved by the invention]

In the case of such digital processing, the image quality is greatly affected by how the analog signal is clamped before the A/D conversion process, as well as timing extraction, including synchronization separation, etc. is greatly affected. In other words, the input level range of the A/D converter must be utilized to the maximum. In particular, in the case of full digitalization, it is impossible to detect clamping pulses unless the input signal to the A/D converter is properly clamped.

An object of the present invention is to clamp the input signal to the A/D converter to a specific voltage level, so that the input range of the A/D converter can be effectively used, and the input signal with the full dynamic range can be processed. The objective is to enable stable digital synchronization separation with improved signal-to-noise ratio.

[Means to solve the problem]

To this end, the present invention includes: a clamp section that clamps an input analog composite video signal at a predetermined clamp level; an A/D converter that converts the video signal clamped by the clamp section into a digital signal;
a comparator that compares the digital signal from the A/D converter with a reference level for a horizontal synchronization signal period; an integral averaging circuit that integrates and averages the comparison output from the comparator; and an output from the integral averaging circuit. The holding means holds the signal for a horizontal scanning period, and means converts the output from the holding means into an analog signal and applies it to the clamp level of the clamp section.

〔Example〕

Examples of the present invention will be described below. FIG. 1 is a diagram showing a clamp circuit of one embodiment.

The analog composite video signal input to input terminal 1 is level-adjusted by level adjuster 2, and capacitor 3
After the direct current is cut at , the signal is clamped by an amplifier 5 whose clamp level is set by a clamp level setter 4 , and then input to an A/D converter 6 . Then, after being subjected to A/D conversion processing using the sampling clock fs in this A/D converter 6 and being delayed by a predetermined time in the delay unit 7, the signal processing unit (
(not shown).

On the other hand, the output signal from the amplifier 5 described above is amplified by the amplifier 8, and only the synchronization signal component from which the video signal component has been removed is extracted by the low-pass filter 9 (see FIG. 2(b)). The components are subjected to limit processing (FIG. 2(C)).

The digital video signal from the delay circuit 7 described above is compared in a comparator 11 with a reference level (reference sync top level) set in advance with reference level setters 1 and 2 such as a digital switch, and the comparison result is It is output to the integral averaging circuit 13. This integrating/averaging circuit 13 receives a synchronizing signal from the limiter 10 (this synchronizing signal and the output signal from the comparator 11 are synchronized in timing by the delay circuit 7), and integrates the comparison output for the period of the signal. Perform averaging processing.

The synchronizing signal component output from the integrating and averaging circuit 13 is held in a latch 14 for an IH period (horizontal scanning period), converted into an analog signal by a D/A converter 15, and then offset by an offset setting device 16 in advance. The voltage is amplified by the set amplifier 17 and output to the clamp level setter 4.
is applied as a correction voltage.

Therefore, for example, when a video signal as shown in the second (k(a)) is input, the top (lower end) of the horizontal synchronizing signal may deviate from the reference level a set by the reference level setter 12. If so, a comparison output corresponding to the difference is output from the comparator 11. Then, this comparison output is integrated and averaged.

This integral averaging is performed by cumulatively adding or subtracting the comparison output and dividing it by the number of additions or subtractions. When division is performed using a shift register, the number of divisions is 2''.

As described above, since the voltage V' outputted from the amplifier 17 is proportional to the comparison output, the clamping of the zinc top in the clamp section is performed at high speed and with high precision.

By performing such a sink top clamp, A
The input level of the /D converter 6 is completely corrected, making it possible to process input signals with a wide dynamic range (see FIG. 3). Therefore, the S/N ratio is improved and stable all-digital synchronization separation becomes possible, and especially in the case of high-definition television, both the synchronization signal and the video signal can be obtained as highly accurate and highly stable signals. Furthermore, it becomes possible to slice the synchronization signal portion by an appropriate value, and it is also possible to expand the dynamic range of the input signal.

〔Effect of the invention〕

As described above, according to the present invention, the intended purpose can be effectively achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a clamp circuit according to an embodiment of the present invention, and FIGS. 2(a) to 3(C) and 3 are signal waveform diagrams for explaining its operation. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Level adjuster, 3... DC cut capacitor, 4... Clamp level setter, 5... Amplifier, 6... A/D converter, 7 ...Delay circuit, 8...Amplifier, 9...Low pass filter,
10... Limiter, 11... Comparator, 12... Reference level setter, 13... Integrating average circuit, 14...
Latch, 15...D/A converter, 16...Offset setter, 17...Amplifier. Agent Patent Attorney Tsuneaki Nagao

Claims (1)

[Claims] (1) a clamp section that clamps an input analog composite video signal at a predetermined clamp level; an A/D converter that converts the video signal clamped by the clamp section into a digital signal; A comparator that compares the digital signal from the D converter with the reference level for only the horizontal synchronization signal period, an integral averaging circuit that integrates and averages the comparison output from the comparator, and a horizontal scanning circuit that horizontally scans the output from the integral averaging circuit. 1. A clamp circuit comprising: a holding means for holding for a period of time; and means for converting an output from the holding means into an analog signal and applying it to the clamp level of the clamp section.