JPH03102974A - Video signal processor - Google Patents

Abstract

PURPOSE:To freely set clamp precision at the time of applying PWM, and to remove line flicker by providing a direct current level correction circuit, a sink chip detection circuit, a subtracter, a first coefficient multiplication circuit, a low order bit integration circuit, a second coefficient multiplication circuit, a pulse width modulation circuit, and an integrator. CONSTITUTION:The direct current level of an input analog video signal is corrected by the output of the integrator 508 by the correction circuit 501, and the input analog video signal is A/D-converted 502. The sink chip level of the converted output is detected by the detector 503, and a reference level is subtracted 504 from it. The output of the subtracter is multiplied by a prescribed coefficient by the coefficient multiplication circuit 505, and the portion of the signal of the prescribed number of bits from the least significant bit is integrated by the low order bit integration circuit 101 before this portion is rejected by the coefficient multiplication circuit 505, and a carrier signal is added to a high order bit, and the output of the integration circuit is multiplied by the prescribed coefficient by the coefficient multiplication circuit 506. As the result, the clamp precision can be set freely and correctly independently of clock frequency at the time of the PWM. If RWM input is fixed to '0' at the time of using a steady state, the direct current level of the output of the correction circuit never varies, and the flicker is never caused.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing device for performing digital signal processing by AD (analog/digital) conversion of a video signal having a synchronization signal such as a television signal. It is.

2. Description of the Related Art In recent years, analog video signals are often converted into digital video signals using an AD converter (hereinafter referred to as ADC) for signal processing. At this time, a video signal processing device is required that includes a clamp circuit that maintains the DC component of the video signal at a predetermined value.

An example of a conventional video signal processing device will be described below with reference to the drawings.

FIG. 5 shows a block diagram of a conventional video signal processing device.

In FIG. 5, 501 is a DC level correction circuit, 502
is an ADC, 503 is a sync chip detection circuit, 504 is a subtracter, 505, 506 are coefficient circuits, 507 is a pulse width modulation circuit (hereinafter referred to as PWM), 508 is an integrator, and 509 is a clamp control circuit. , 510 is an analog video signal input terminal, 511 is a digital video signal output terminal, and 512 is a reference sync chip level input terminal.

The operation of the video signal processing device configured as described above will be described below.

First, an analog video signal is input to the analog video signal input terminal 510. Then, the DC level correction circuit 501 corrects only the error DC level output from the integrator 508.

The analog video signal corrected to a predetermined DC level by the DC level correction circuit 501 is converted into a digital video signal of a predetermined number of bits by an ADC 502 using a clock of a predetermined frequency. A sync tip detection circuit 503 detects the sync tip level of the digital video signal. Its sync tip level and reference sync tip level input terminal 51
2 and the reference sync chip level input to the subtracter 504.
to obtain an error signal, then multiply it by a predetermined coefficient in a coefficient circuit 505 to set a predetermined time constant of the entire feedback system, and then multiply it by a predetermined coefficient in a coefficient circuit 508 to perform pulse width modulation in the PWM 507. Multiply. The sync chip detection circuit 503, subtracter 504, coefficient circuit 505
, 506, the reference sync tip level input terminal 512 is the clamp control circuit 509. The output signal of the coefficient circuit is P
By performing pulse width modulation with the WM 507 and further integrating with the integrator 508, an error DC level to be corrected by the DC level correction circuit 501 is obtained. As a result, even if the DC level of the input analog video signal fluctuates, the error DC level follows the fluctuating sync tip level based on the time constant set by the coefficient circuit 505, and the DC level correction circuit 50
The DC level of the sync chip of the output analog video signal of 1 becomes equal to the reference sync chip level. This is a so-called feedback type sink tip clamp. As a result, the input analog video signal falls within the dynamic range of the ADC and can be effectively AD converted.

Problems to be Solved by the Invention In such conventional video signal processing devices, the following two problems occur.
There are two issues.

One example is to set the clock frequency at 13.5 MHz when pulse width modulation is performed by the PWM 507, and set the cycle to be corrected by the DC level correction circuit 501 to one horizontal synchronization period of the input analog video signal (for example, the standard television B signal of the NTSC system). Then, once every 63.5 μsec), 63.
Since 5 μsec corresponds to approximately 857 clocks of 13.5 MHz, the input dynamic range of PWM507 is limited to o bit (=±512), and if the output of coefficient circuit 505 is 13 bits, the output of coefficient circuit 506 is 1/8 times The detection accuracy of the error signal must be 3.
It will drop by the amount of bit, making it impossible to clamp accurately. That is, the clamping accuracy is PWM5 regardless of the required accuracy.
The problem is that it is determined by the clock frequency when modulating with 0.07.

Another reason is that since the clamp control circuit 509 is configured with a digital circuit, even in a stable state where the sync tip level of the input analog video signal is clamped to the reference sync tip level, the output I of the coefficient circuit 506 is L S B (east slg-nlflca
For example, if the gain of the input analog video signal is changed to I V PP (peak-k
to peak), and if the number of input bats of the PWM 507 is lOblt, then the output of the DC level correction circuit 501 is! /512 V PP fluctuates. This is because when the digital video signal output to the digital video signal output terminal 511 is converted to DA (digital/analog) and viewed on a monitor, the brightness signal flickers every horizontal period, causing an unsightly so-called line flicker. This is a challenge.

In view of the above problems, the present invention solves the first problem by
We provide a video signal processing device that can freely set the clamp accuracy regardless of the clock frequency when modulating with M507. It is an object of the present invention to provide a video signal processing device in which there is no fluctuation in the DC level of a signal.

Means for Solving the Problems In order to achieve the above object, the present invention includes a DC level correction circuit that corrects the DC level of an analog video signal using the output of an integrator, and a DC level correction circuit that corrects the output of the DC level correction circuit with a predetermined clock. an AD converter for converting into a digital video signal;
a sync tip detection circuit that detects the sync tip level of the output of the D converter; a subtracter that subtracts the reference sync tip level and the output of the sync tip detection circuit; and the output of the subtracter is input and multiplied by a predetermined coefficient. a first coefficient circuit;
a lower bit integration circuit that integrates only a predetermined number of bits from the least significant bit of the output of the first coefficient circuit; a second coefficient circuit that multiplies the output of the lower bit integration circuit by a predetermined coefficient; The present invention includes a pulse width modulation circuit that pulse width modulates the output of the coefficient circuit, and an integrator that integrates the output of the pulse width modulation circuit.

The present invention also provides a DC level correction circuit that corrects the DC level of an analog video signal using the output of an integrator, an AD converter that converts the output of the DC level correction circuit into a digital video signal using a predetermined clock, and a sync tip detection circuit that detects the sync tip level of the output of the converter;
a subtracter that subtracts the reference sync tip level and the output of the sync tip detection circuit; a first coefficient circuit that multiplies the output of the subtracter by a predetermined coefficient; and a first coefficient circuit that multiplies the output of the first coefficient circuit by a predetermined coefficient. a second coefficient circuit that generates a pulse when the output of the subtracter is within a predetermined level range; and a switch means that switches between the output of the second coefficient circuit and a zero level using the pulse. and a pulse width modulation circuit for pulse width modulating the output of the switch means, and an integrator for integrating the output of the pulse width modulation circuit.

Operation With the above-described configuration, the present invention digitally integrates only the 3-bit signal and uses the carry signal, for example, before the second coefficient circuit divides the signal by 1/8 and discards the 3-bit signal. By adding to the upper bits, even if the second coefficient circuit performs 178, the signal of the lower bits is reflected on the upper bits, so it is possible to accurately clamp the error signal without reducing the detection accuracy.

In addition, when the error signal that is the output of the subtracter falls within a predetermined level range, that is, when the clamp is in a steady state, by fixing the PWM input to zero, the analog signal that is the output of the DC level correction circuit is Since the DC level of the video signal does not change at all, no line flicker occurs when viewed on a monitor.

Embodiment Hereinafter, a video signal processing device according to an embodiment of the present invention will be described.
This will be explained with reference to the drawings.

However, the same components as those of the conventional video signal processing device shown in FIG. 5 are given the same reference numerals, and explanations of their operations will be omitted.

FIG. 1 shows a block diagram of a video signal processing device according to a first embodiment of the present invention. In Figure 1,
501 is a DC level correction circuit, 502 is an ADC, 503
is a sync tip detection circuit, 504 is a subtracter, 505.5
06 is a coefficient circuit, 101 is a lower bit integration circuit, 507
508 is an integrator, 102 is a clamp control circuit, 510 is an analog video signal input terminal, 5l1 is a digital video signal output terminal, and 512 is a reference sync tip level input terminal.

FIG. 6 shows a block diagram of a lower bit integration circuit included in the video signal processing device of FIG. 1. In FIG. 6, 60l is an adder, 602 is a lower bit extractor,
603 is a delay circuit, 604 is an input terminal, and 605 is an output terminal.

The operation of the video signal processing device configured as described above will be described below with reference to FIGS. 1 and 6.

A lower bit integration circuit 10l integrates only a predetermined lower bit of the output of the coefficient circuit 505, and outputs an error signal obtained by adding the carry output to the upper bit. The output of the lower bit integration circuit 101 is multiplied by a predetermined coefficient in a coefficient circuit 506. This sync tip detection circuit 503, subtracter 504
, coefficient circuit 505, lower bit integration circuit 101, coefficient circuit 506, reference sync chip level input terminal 512
is the clamp control circuit 102. The number of lower bits integrated by the lower bit integration circuit 101 matches the number of lower bits discarded by the coefficient circuit 506, for example, the coefficient circuit 50B.
When the number is 178, the lower bit integration circuit 101 selects the lower 3 bits.
Integrate b+t, and similarly when it is 1/4, the lower 2 blt
and when it is 1/16, the lower 4 bits are integrated.

Clamp control circuit 10 including this lower bit integration circuit
Set to 1. The lower bit integration circuit 101 will now be explained using FIG. 6. An adder 601 adds the input of the lower bit 15 division circuit 101, that is, the signal input to the input terminal 604, and the output of the delay circuit 603. Adder 6
The output of 01 is input to the lower bit extractor E302, and a predetermined number of bits are extracted from the least significant bit. The predetermined number of bits is the same as the number of lower bits integrated by the lower bit integrator 10t described above. The output of the lower bit extractor 602 is delayed by a predetermined period in a delay circuit 603. The predetermined delay corresponds to the period corrected by the DC level correction circuit 501 and is one horizontal synchronization period. The output of adder 601 is output to output terminal 605, which is the output of lower bit integration circuit 1O1.

FIG. 2 shows a block diagram of a video signal processing device according to a second embodiment of the present invention. In Figure 2,
501 is a DC level correction circuit, 502 is ADC1 50
3 is a sync tip detection circuit, 504 is a subtracter, 505,
506 is a coefficient circuit, 201 is a switch means, 202 is a pulse generation circuit, 507 is a PWM1, 508 is an integrator, 2
03 is a clamp control circuit, 510 is an analog video signal input terminal, 511 is a digital video signal output terminal, 512
204 is a reference sync tip level input terminal, and 204 is a zero level input terminal.

The operation of the video signal processing device configured as above will be described below.

The error signal which is the output of the subtracter 504 is sent to the pulse generation circuit 2.
For example, if the error signal is within the range of ±4 steps, it is defined that the clamp is in the holding mode, and the output pulse is set to high level. If it is outside the range of ±4 steps, the pulse is set to low level. Switch means 2
The output of the coefficient circuit 506 and the zero level input to the zero level input terminal 204 are input to 01, and when the pulse is at a low level, the output of the coefficient circuit is used as the output of the switch means, and when it is at a high level, that is, the holding mode is set. In this case, switch to the zero level input terminal side. These pulse generation circuits 2
02, switch means 201, zero level input terminal 204
The clamp control circuit 203 includes the above.

FIG. 3 shows a block diagram of a video signal processing device according to a third embodiment of the present invention. In Figure 3,
502 is ADC1 301 is a DC level correction circuit, 50
3 is a sync tip detection circuit, 504 is a subtracter, 505,
506 is a coefficient circuit, 20I is a switch means, 202 is a pulse generation circuit, 302 is an integrator, 303 is a clamp control circuit, 510 is an analog video signal input terminal, 511 is a digital video signal output terminal, 512 is a reference sync chip level input Terminal 204 is a zero level input terminal.

The operation of the video signal processing device configured as above will be described below.

The difference from the second embodiment is that the DC level correction circuit 301 and the integrator 302 are constructed with digital circuits, but their operation is the same as when constructed with analog circuits. By configuring the circuit using a digital circuit, PWM for converting the error DC level into an analog signal is not required.

FIG. 4 shows a block diagram of a video signal processing device according to a fourth embodiment of the present invention. In Figure 4,
501 is a DC level correction circuit, 502 is ADC1 50
3 is a sync tip detection circuit, 504 is a subtracter, 505,
506 is a coefficient circuit, 1O1 is a lower bit integration circuit, 20
1 is a switch means, 202 is a pulse generation circuit, 507 is a PWM, 508 is an integrator, 401 is a clamp control circuit,
510 is an analog video signal input terminal, 511 is a digital video signal output terminal, 5l2 is a reference sync chip level input terminal, and 204 is a zero level input terminal.

The operation of the video signal processing device configured as above will be described below. However, the explanation of the parts having the same configuration as the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 2 will be omitted.

FIG. 4 shows the conventional example shown in FIG. 5, the lower bit integrator circuit 101 of the first embodiment shown in FIG. 1, the switch means 201 of the second embodiment shown in FIG. It is also configured with an input terminal 204. Therefore, this fourth embodiment is similar to the PWM5 in the first embodiment.
The advantage is that the clamp accuracy can be set freely regardless of the clock frequency when modulating with PWM50 when modulating with PWM50 when the clamp in the second embodiment reaches a steady state.
This video signal processing device has the effect that the DC level of the analog video signal that is the output of the DC level correction circuit 501 does not change at all by fixing the input No. 7 to zero.

Effects of the Invention As explained above, according to the present invention, by providing the lower bit integration circuit, the coefficient circuit multiplies the signal by a predetermined coefficient and discards the signal for a predetermined number of bits starting from the lowest bit. By digitally integrating only the signal for that number of bits and adding the carry signal to the upper bits, even if the coefficient circuit multiplies the signal of the lower bits, the signal of the lower bits is reflected in the upper bits. Accurate clamping is possible without reducing detection accuracy. That is, the clamp accuracy can be freely set regardless of the clock frequency when modulating with PWM.

In addition, by providing a pulse generation circuit, a switch means, and a zero level input terminal, when the error signal that is the output of the subtracter falls within a predetermined level range, that is, when the clamp is in a steady state, the PWM input terminal By fixing to zero, the DC level of the analog video signal output from the DC level correction circuit does not change at all, so line flicker does not occur even when viewed on a monitor.

In this way, it is extremely useful when performing digital signal processing on video signals, and has great industrial value.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a video signal processing device according to a first embodiment of the present invention, and FIG. 2 is a block diagram of a video signal processing device according to a second embodiment of the present invention. 3 is a process diagram of a video signal processing device according to a third embodiment of the present invention, and FIG. 4 is a process diagram of a video signal processing device according to a fourth embodiment of the present invention.
FIG. 5 is a block diagram of a conventional video signal processing device, and FIG. 6 is a block diagram of a lower bit integration circuit in the first and fourth embodiments. 501, 301... DC level correction circuit, 502...
・ADC1 503...Sync chip detection circuit, 5
04...Subtractor, 505,506...Coefficient circuit, 507...PWM1 508.302...Integrator, 102,203,303.401...Clamp control circuit, 510...Analog video signal input terminal,
611...Digital video signal output terminal, 512
...Reference sync tip level input terminal, 101.
...lower bit integration circuit, 201...switch means, 202...pulse generation circuit, 204...
・Zero level input terminal, 601...adder,
602... Lower bit extractor, E303... Delay circuit, 604... Input terminal, 605... Output terminal.

Claims (4)

[Claims] (1) A DC level correction circuit that corrects the DC level of an analog video signal using the output of an integrator, an AD converter that converts the output of the DC level correction circuit into a digital video signal at a predetermined clock, and the AD converter a sync tip detection circuit that detects the sync tip level of the output of the sync tip detection circuit; a subtracter that subtracts the output of the sync tip detection circuit from the reference sync tip level; and a first circuit that receives the output of the subtracter and multiplies it by a predetermined coefficient. a coefficient circuit; a lower bit integration circuit that integrates only a predetermined number of bits from the least significant bit of the output of the first coefficient circuit; and a second lower bit integration circuit that multiplies the output of the lower bit integration circuit by a predetermined coefficient.
A video signal processing device comprising: a coefficient circuit; a pulse width modulation circuit that pulse width modulates the output of the second coefficient circuit; and an integrator that integrates the output of the pulse width modulation circuit. (2) a DC level correction circuit that corrects the DC level of an analog video signal using the output of an integrator; an AD converter that converts the output of the DC level correction circuit into a digital video signal at a predetermined clock; and the AD converter a sync tip detection circuit that detects the sync tip level of the output of the sync tip detection circuit; a subtracter that subtracts the output of the sync tip detection circuit from the reference sync tip level; and a first coefficient circuit that multiplies the output of the subtracter by a predetermined coefficient. a second coefficient circuit that multiplies the output of the first coefficient circuit by a predetermined coefficient; a pulse generating circuit that generates a pulse when the output of the subtracter is within a predetermined level; A switch means for switching between the output of the second coefficient circuit and a zero level, a pulse width modulation circuit for pulse width modulating the output of the switch means, and an integrator for integrating the output of the pulse width modulation circuit. A video signal processing device characterized by: (3) an AD converter that converts an analog video signal into a digital video signal using a predetermined clock; a DC level correction circuit that corrects the DC level of the output of the AD converter using the output of an integrator; and the DC level correction circuit. a sync tip detection circuit that detects the sync tip level of the output of the sync tip detection circuit; a subtracter that subtracts the output of the sync tip detection circuit from the reference sync tip level; and a first coefficient circuit that multiplies the output of the subtracter by a predetermined coefficient. a second coefficient circuit that multiplies the output of the first coefficient circuit by a predetermined coefficient; a pulse generating circuit that generates a pulse when the output of the subtracter is within a predetermined level; A switch means for switching between the output of the second coefficient circuit and a zero level, a pulse width modulation circuit for pulse width modulating the output of the switch means, and an integrator for integrating the output of the pulse width modulation circuit. A video signal processing device characterized by: (4) a DC level correction circuit that corrects the DC level of an analog video signal using the output of an integrator; an AD converter that converts the output of the DC level correction circuit into a digital video signal at a predetermined clock; and the AD converter a sync tip detection circuit that detects the sync tip level of the output of the sync tip detection circuit; a subtracter that subtracts the output of the sync tip detection circuit from the reference sync tip level; and a first circuit that receives the output of the subtracter and multiplies it by a predetermined coefficient. a coefficient circuit; a lower bit integration circuit that integrates only a predetermined number of bits from the least significant bit of the output of the first coefficient circuit; and a second lower bit integration circuit that multiplies the output of the lower bit integration circuit by a predetermined coefficient.
a coefficient circuit; a pulse generating circuit that generates a pulse when the output of the subtracter is within a predetermined level; and a switch means that switches between the output of the second coefficient circuit and a zero level using the pulse; A video signal processing device comprising: a pulse width modulation circuit that pulse width modulates the output of the switching means; and an integrator that integrates the output of the pulse width modulation circuit.