JPH11261845A - Video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To normally perform a clamp processing to video signals on which various information is superimposed relating to a video signal processing circuit provided with a clamp circuit for performing the DC restoration of the video signals in an image transmitter for performing waveform transmission. SOLUTION: By detecting superimposing signals inside a video invalid part in the video signals in a superimposing signal detection part 1 and supplying switching signals based on the presence/absence of the superimposing signals from a clamp changeover control part 2 to the clamp circuit 4, a clamp level in the video invalid part where the superimposing signals are not present in the video signals is held and the DC restoration is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit having a clamp circuit for reproducing a DC signal of a video signal in an image transmission apparatus for performing waveform transmission.

2. Description of the Related Art Generally, an image encoding apparatus performs a "clamp (DC component reproduction)" process unique to an image signal before inputting the image signal and performing an encoding process. This clamp circuit includes a sync tip clamp system and a pedestal clamp system.

In the former sync tip clamp circuit, since the base of synchronization is used as a reference, the sync tip clamp circuit is easily affected by a large level fluctuation (expansion) of the input signal, and the pedestal level of the video signal and the entire signal fluctuate. . For this reason,
Usually, a clamp circuit based on the latter pedestal level is often used.

[0004]

2. Description of the Related Art FIG. 23 shows a conventional example of a clamp circuit used in a video signal processing circuit. In this clamp circuit, a video signal as shown in FIG. The synchronization signal is input to the separation unit 102 at the same time, and the synchronization separation unit 102 extracts a horizontal synchronization signal from the video signal. From this horizontal synchronizing signal, the clamp pulse generator 103 further generates a clamp pulse having the same cycle ((2) in the figure) at a color bust position adjacent to the horizontal synchronizing signal.

With this clamp pulse, the potential at the output point P ₂ of the clamp unit 101 (FIG. 4 (4)) is sampled and held by the clamp level holding unit 104, and the reference unit V _E (FIG. 3 (3)) ). This comparison unit 105
By feeding back the error voltage P ₁ (= P ₂ −V _E ) obtained by the comparison in the above to the clamp unit 101, stable DC reproduction can always be performed. Then, the output signal of the clamp unit 101 is converted into a digital signal by the A / D converter 110.

[0006]

However, when such a pedestal clamp circuit is used, a VIT using a plurality of horizontal scanning periods or the like in a recent vertical blanking period is used.
The DC value of the pedestal level fluctuates arbitrarily due to the superposition of information such as S signal, character information, and copy guard signal.
When the TSC signal (FIG. 25 (1)) is clamped as shown in FIG. 25 (2), the clamp level cannot be specified directly from the input signal, and the pedestal level extracted as shown in FIG. , The required clamp level cannot be obtained, and as a result, an out-of-synchronization screen or the like occurs.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a video signal processing circuit provided with a clamp circuit capable of normally performing a clamp process on a video signal on which various information is superimposed, in order to solve such a problem. .

[0008]

In order to achieve the above object, a video signal processing circuit according to the present invention detects a superimposed signal in a video invalid portion in a video signal as shown in principle in FIG. A superimposed signal detector 1, a clamp switching controller 2 for generating a switching signal based on the presence or absence of the superimposed signal, a delay circuit 3 for delaying the video signal by a predetermined time, and an output from the delay circuit based on the switching signal. And a clamp circuit 4 that holds a clamp level in the video invalid portion where the superimposed signal of the video signal does not exist and reproduces the video signal by a DC component.

That is, in the present invention, the superimposed signal detecting section 1
Monitor the video invalid portion of the video signal to detect a superimposed signal. When the superimposed signal is detected, the clamp switching control unit 2 supplies a switching signal indicating this to the clamp circuit 4,
The clamp circuit 4 reliably clamps (reproduces DC components) the video signal by holding the clamp level in a portion where there is no superimposed signal in the video invalid portion. When a superimposed signal is not detected, a switching signal from the clamp switching control unit 2 indicating this indicates that, as in the related art, the clamp level in a portion where no superimposed signal is present in the video invalid portion is reproduced by a DC component of the video signal. I do.

[0010] As described above, by performing the clamping at the image invalid portion in the video signal in accordance with the presence or absence of the signal superimposed on the video signal, a clamp level required for the clamp processing can be obtained. Thus, the clamp process can be performed without being affected by the superimposed signal.

[0011] The superimposed signal detecting section may detect a superimposed signal of the video signal in a vertical blanking period.
Further, the video invalid portion may be a portion corresponding to a back porch position following each horizontal synchronization signal.

Further, the clamp switching control section may include a circuit for generating the switching signal when the threshold value is exceeded regardless of the polarity of the superimposed signal. Further, the clamp switching control unit can output the switching signal in units of horizontal lines, and can output the switching signal in units of fields.

Further, the clamp circuit may include a circuit for selecting a back porch position or a front porch position by the switching signal and holding a clamp level of the video signal. Further, the clamp circuit may include a circuit that selects a back porch position or a sync tip position based on the switching signal, selects a reference potential corresponding to each position, and holds a clamp level of the video signal.

Further, the clamp circuit selects a clamp level at the back porch position or a previous value clamp level holding the clamp level at the back porch position by the switching signal to perform DC level reproduction of the video signal. May be provided.

Further, the clamp circuit selects the clamp level at the back porch position or the average clamp level holding the average value of a plurality of clamp levels at all the back porch positions by the switching signal and selects the clamp level of the video signal. A circuit for holding a clamp level for performing DC component reproduction may be provided.

The above-mentioned predetermined time is a time during which the clamp level of the video signal can be held at a position other than the back porch position in the video invalid portion when the superimposed signal is present. Further, the above-described superimposed signal detection unit and clamp switching control unit can be configured by an analog circuit or a digital circuit.

[0017]

FIG. 2 shows an embodiment (1) of the superimposed signal detecting section 1 shown in FIG. In this embodiment, a sync separation unit 11 and a band rejection filter (BEF) 14 for inputting a video signal, a reference pattern generation unit 12 and a vertical blanking period signal generation unit 13 connected to the synchronization separation unit 11, Calculator 15 for calculating the difference between the output signal of band rejection filter 14 and the output signal of reference pattern generator 12
And a low-pass filter (LPF) 16 for removing a noise component of the output signal of the arithmetic unit 15. Note that the vertical blanking period signal generator 13 enables the operation unit 15 only during the vertical blanking period.

The operation of the embodiment of such a superimposed signal detecting section will be described below with reference to the timing chart shown in FIG. First, the video signal is supplied to an inverting input terminal of a computing unit 15 as a video signal A after removing a signal such as a color burst through a filter 14. In this case, as shown in FIG. 3, a superimposed signal such as a VITS signal or a copy guard signal is superimposed on the video signal A in the vertical blanking period as shown in FIG.

On the other hand, a vertical synchronizing signal is separated from the video signal by a synchronizing separation unit 11, which is applied to a vertical blanking period signal generating unit 13, whereby the signal generating unit 1
3 operates the arithmetic unit 15 for the vertical blanking period based on the vertical synchronization signal. Further, based on the horizontal synchronization signal separated from the synchronization separation unit 11, the reference pattern generation unit 12 generates a reference pattern B as shown in FIG.

The arithmetic unit 15 performs pattern matching between the video signal A and the reference pattern B to obtain a detection signal C shown in FIG. 3 as a difference signal. The detection signal C has a waveform in which only the superimposed signal is left. In this way, a superimposed signal is detected. Here, in the embodiment (1) shown in FIG. 2, the superimposed signal detecting section 1 is constituted by an analog circuit, but it can be constituted by a digital circuit as shown in FIG.

That is, in the embodiment (2) of the superimposed signal detection section, the analog output signal of the filter 14 is converted into a digital signal by the A / D conversion section 17, and the digital operation signal is outputted via the flip-flop 18. Has given to. Also, a flip-flop 20 is provided on the output side of the digital filter 16, and this flip-flop 20 is reset when a vertical blanking period by the signal generator 13 has elapsed. The operation of the superimposed signal detection unit having such a digital circuit configuration also exhibits the same operation as the time chart shown in FIG.

FIG. 5 shows an embodiment (3) of the superimposed signal detecting section shown in FIG. 1, and this embodiment also comprises an analog circuit. That is, in this embodiment (3), instead of detecting a superimposed signal in a vertical blanking period of a video signal as shown in FIGS. 2 and 4, a superimposed signal for each horizontal line is detected. It is.

For this reason, the video signal is supplied to the sync separation unit 11 and the filter 14, and the level signal for generating the level extraction timing signal at the back porch position by inputting the horizontal sync signal separated from the sync separation unit 11 An extraction timing generator 21 is connected, and a level extractor 22 is connected to the output of the filter 14. Further, the detection signal is output from the level extraction unit 22 according to the extraction timing from the level extraction timing generation unit 21.

The operation of the embodiment (3) shown in FIG. 5 will be described with reference to the timing chart shown in FIG. First,
Assuming that the video signal A has a waveform as shown in FIG. 6, the horizontal synchronizing signal of the video signal A is separated by the sync separation section 11, and when this is supplied to the level extraction timing generation section 21, the level extraction is performed. The timing signal B is provided to the level extraction unit 22.

Accordingly, the level extracting section 22 outputs a detection signal C indicating that there is a superimposed signal at the back porch position in the video invalid portion following the horizontal synchronizing signal as shown in FIG.

FIG. 7 shows an embodiment (4) in which the superimposed signal detector 1 shown in FIG. 5 is constituted by a digital circuit. In this embodiment, an A / D converter is provided on the output side of the filter 14.
The conversion section 23 is provided to convert the digital signal into a digital signal, and the converted digital signal is hit by the level extraction timing signal B to obtain the back porch position detection signal C as shown in the timing chart of FIG. be able to.

FIG. 9 shows the clamp switching control unit 2 shown in FIG.
1 shows the embodiment (1). In this example,
The superimposed signal detection signal C detected by the superimposed signal detection unit 1 is 2
The output signals of the level monitoring units 31 and 32 are supplied to an OR gate 33.

The output signal of the OR gate 33 is
4 set input terminal S. A switching timing pulse from a switching timing pulse generator 35 is applied to a reset input terminal R of the latch circuit 34.
The switching timing pulse generation unit 35 is a synchronization separation unit 36 that separates a horizontal synchronization signal or a vertical synchronization signal from a video signal.
It is connected to the.

In this case, in the case of a horizontal synchronization signal, a switching timing pulse CLK can be generated for each line and given to the holding circuit 37, or in the case of a field unit, the pulse CLK based on the vertical synchronization signal is held. It is given to the circuit 37. The holding circuit 37 temporarily holds the output signal of the latch circuit 34 and then switches the switching timing pulse generator 35
A switching signal is generated by a pulse CLK from the CPU.

The operation of the embodiment (1) of such a clamp switching control unit will be described with reference to a timing chart shown in FIG. That is, when the superimposed signal detection signal C is commonly supplied to the level monitoring units 31 and 32 by the superimposition signal detection unit 1, the level monitoring units 31 and 32 use the comparators 310 and 320 respectively provided with the + threshold. And-Compare with threshold.

Now, if the detection signal C has a waveform as shown in the superimposed signal detection example (1) shown in FIG. 10, the superimposed signal is further below the -threshold. A 1 "level signal is output and the latch circuit 34 is set via the OR gate 33 as a latch example (1). In this case, the latch circuit 34 is similarly set as shown in the latch example (2) in the case of the superimposed signal as shown in the superimposed signal detection example (2) in FIG.

The latch circuit 3 set as described above
4 is a pulse generator 3 which receives a horizontal synchronizing signal from the synchronizing separator 36 when processing is performed on a line-by-line basis.
5, the switching timing pulse is supplied to the reset input terminal R of the latch circuit 34 line by line, so that the switching is reset at the rising edge of the timing pulse.

On the other hand, the holding circuit 37 does not change the switching signal only when the latch circuit 34 is latched in the set state, and when the switching timing pulse CLK is supplied from the switching timing pulse At the time of falling, the output signal of the latch circuit 34 is latched.

The latch state of the holding circuit 37 is the switching timing pulse C based on the next horizontal synchronizing signal.
It is held until the falling point of LK comes, at which point the holding state is released. In this way, a switching signal as shown in FIG. 10 is output from the holding circuit 37.

In the above description, an example has been described in which the horizontal synchronizing signal is separated from the synchronizing separator 36. However, when the vertical synchronizing signal is separated, a switching timing pulse is generated in field units. The holding circuit 37 performs the holding operation and the reset operation for each field.

FIG. 11 shows an embodiment (2) of a clamp switching control unit constituted by a digital circuit instead of the clamp switching control unit having the analog circuit configuration shown in FIG. In this embodiment, only the configurations of the level monitoring units 31 and 32 are different. In the level monitoring unit 31, the + threshold and the superimposed signal detection signal C are compared with each other by the comparator 311.
Similarly, in the level monitor 32, the comparator 321 compares the minus threshold value with the detection signal C.

The clamp switching control section 2 having such a digital circuit configuration exhibits the same operation as the time chart shown in FIG. FIG. 12 shows an embodiment of the video signal processing circuit shown in FIG. 1, and particularly shows an embodiment (1) of the clamp circuit 4.

That is, in this embodiment, the clamp section 41, the synchronization separation section 42, and the clamp level holding section 45
And the comparison unit 46 are used in the same connection relationship as the clamp unit 101, the synchronization separation unit 102, the clamp level holding unit 104, and the comparison unit 105 in the conventional example shown in FIG.

On the other hand, in this embodiment, the synchronization separation unit 4
2 is connected to a generator 43 for generating a clamp pulse at the back porch position and a clamp pulse generator 44 for generating a clamp pulse at the front porch position. The output signal is configured to be selectively supplied to the clamp level holding unit 45 via a switch SW1 that performs a switching operation according to a switching signal from the clamp switching control unit 2.

The operation of the embodiment (1) of such a clamp circuit will be described below with reference to a time chart shown in FIG. First, a horizontal synchronizing signal is given to the clamp pulse generation units 43 and 44 from the synchronization separation unit 42, whereby the clamp pulse generation units 43 and 44 are respectively moved to the back porch position and the front porch position as shown in FIG. The corresponding clamp pulse is constantly being generated.

In such a state, the clamp switching control unit 2
, A switching timing signal (holding circuit output signal) is supplied to the switch SW1.

As shown in FIG. 10, this switching timing signal indicates that the superimposed signal exists in the set state (logic "1" level), and in this period, at the back porch position where the superimposed signal can exist. Since it is better not to perform the clamping operation, the clamping operation at the front porch position is performed as shown in FIG.

As a result, the switch SW1 in the clamp circuit 4 is switched to the side of the clamp pulse generating section 44, and the clamp level holding section 45 receiving the switch receives the clamp pulse and outputs the video signal output from the clamp section 41. DC component of the pedestal level of the front porch position retained as clamp level, by comparing the comparing unit 46 conventional example as well as the clamp level reference potential V _E, a stable and feeding back the difference to the clamp portion 41 in the Perform playback.

When the switching timing signal is in the reset state (logic "0" level), it means that there is no superimposed signal.
Is returned to the position shown in the drawing, whereby the clamp pulse at the back porch position is given from the clamp pulse generation unit 43 to the clamp level holding unit 45, and the pedestal level at the back porch position is held as the clamp level. Perform minute playback.

In the time chart of FIG. 13, the switching timing signal is shown differently from the relationship between the superimposition signal and the switching signal in FIG. This is because the setting is made such that the clamping operation of the front porch position is reliably performed before the horizontal synchronization signal.

FIG. 14 shows an embodiment (2) of the clamp circuit 4 shown in FIG. 1. In this embodiment, the clamp pulse generator 44 is different from the clamp circuit embodiment (1) described above. Alternatively using a clamp pulse generator 47 for generating a clamp pulse in sync tip position, and gives the pedestal reference potential 48 or sync tip reference potential 49 in place of the reference potential V _E to the comparator 46 through the switch SW3 of The difference is that these switches SW1 and SW3 are controlled by the clamp switching control unit 2.

The operation of the embodiment (2) of such a clamp circuit will be described below with reference to the timing chart shown in FIG.

In this embodiment, when a superimposed signal exists at the back porch position, the signal level at the sync tip position indicating the bottom position of the horizontal synchronization signal is clamped instead of clamping the video signal at the front porch position. As shown in the figure, the time for delaying the video signal by the delay circuit 3 does not need to include the front porch position as shown in FIG. 13, but may include at least the sync chip position in the horizontal synchronization signal. Therefore, the clamp pulse generation unit 47 also generates a clamp pulse at a position where the sync tip position is detected.

[0049] In this case, when the clamp pulse generator 43 is selected by the switch SW1, which reference potential 48 in synchronization with is selected by the switch SW3, but given as a reference potential V _E to the comparator 46, the sync tip The position of the clamp pulse generator 47 is the switch SW1
When the switch SW3 is selected, the reference potential 49 is also selected by the switch SW3 and supplied to the comparator 46 in synchronization with this.

As a result, as shown in FIG. 15, it can be understood that the extracted clamp level similarly changes with the switching of the reference potential. The control signal from the clamp switching control unit 2 to the switches SW1 and SW3 has the same switching time as shown in FIG.
It is preferable that W1 is earlier by the amount of the clamp pulse.

FIG. 16 shows an embodiment (3) of the clamp circuit 4 shown in FIG. 1. In this embodiment, too,
The clamp pulse generator 44 at the front porch position shown in FIG. 12 is not used, and the synchronization separator 42, the clamp pulse (back porch position) generator 43, and the clamp level holding unit 45 are fixedly connected. Instead, the clamp level held by the clamp level holding unit 45 is not always given to the comparison unit 46, but is switched to the clamp level held by the previous value clamp level holding unit 50, and the comparison unit 46 is switched via the switch SW4. Is to be given.

The previous value clamp level holding section 50 is connected to the clamp level holding section 45 via the switch SW5, and outputs a clamp level extracted from one or more effective video signal lines having no superimposed signal. It is provided from the clamp level holding section 45.

Accordingly, the switch SW5 in this case is ON / OFF controlled by the clamp switching control unit 2.

The operation of the embodiment (3) of such a clamp circuit will be described with reference to a timing chart shown in FIG. 17. If no superimposed signal is placed on the back porch position of the video signal as described above, the clamp switching is performed. The control unit 2 switches and connects the switch SW4 to the position shown in the figure. As a result, the clamp level is held by the clamp level holding unit 45 at the back porch position of the video signal, and the above-described clamp operation is performed based on this.

On the other hand, when the superimposed signal is on the back porch position, the clamp switching control unit 2 switches the switch SW.
4 is switched to the previous value clamp level holding unit 50 side.

When the switch SW4 is connected to the clamp level holding unit 45, the previous value clamp level holding unit 50 is turned on in synchronization with the switch SW4.
5 is connected to the clamp level holding unit 45 via the control unit 5, so that the holding level of the clamp level holding unit 45 can be held as the previous value clamp level. Therefore,
When the superimposed signal at the back porch position is detected, the switch SW5 is turned off by the control signal from the clamp switching control unit 2, and the previous value clamp level is supplied from the switch SW4 to the comparison unit 46.

In this way, as shown in FIG. 17, the clamp level is set at the video signal lines a, b, and c.
For line a, the pedestal level of line a becomes the clamp level, for line b, the pedestal level of line a becomes the clamp level, and further, line c
It is shown that the pedestal level of the line c becomes the clamp level.

FIG. 18 shows an embodiment (4) of the clamp circuit 4 shown in FIG. 1. In this embodiment, the previous value clamp level holding section is different from the embodiment (3) of the clamp circuit described above. An average value clamp level holding unit 51 is provided instead of 50, and the average value clamp level holding unit 51 and the clamp level holding unit 45 are fixedly connected. The difference is that it is controlled by the control unit 2.

The embodiment of the embodiment (4) of such a clamp circuit will be described with reference to a timing chart shown in FIG. 19. The average value clamp level holding section 51 is controlled by the clamp switching control section 2 so that Of the clamp levels held by the clamp level holding unit 45, the clamp levels only when there is no superimposed signal at the back porch position are accumulated, and the average value is held.

Therefore, when the clamp switch control section 2 switches the switch SW4 from the clamp level holding section 45 to the average value clamp level holding section 51 when the superimposed signal is present at the back porch position, the average value accumulated so far is stored. The clamp level is given from the switch SW4 to the comparing section 46, and a predetermined DC component reproducing operation is executed.

Accordingly, also in this case, the clamp level is the pedestal level clamped in the same manner as in FIG. 17, as shown in FIG. FIG. 20 shows the average value clamp level holding unit 5 received in the embodiment (4) of the clamp circuit shown in FIG.
1 shows an embodiment (1) of the present invention.

The average value clamp level holding section 51 according to this embodiment includes a line pulse generating section 61 receiving a control signal from the clamp switching control section 2 and a clamp level from the clamp level holding section 45 for line pulses A, B,. A switch (SW) 62 for passing / blocking by C,
63, 64, Ln line clamp level holding units 65-67 for holding the output signals of these switches 62-64 for a predetermined number Ln lines, and output signals D ~ of these Ln line clamp level holding units 65-67. F to resistance 69
, An adder 68 that adds and outputs the result through an arithmetic unit 72, a divider 73 that divides the output signal of the adder 68 by １ ／, and a resistor 7 that outputs the output signal of the divider 73.
5 and an inverting amplifier 74 for inverting and amplifying via an arithmetic unit 76
And a holding unit 77 which holds the output signal of the inverting amplifier 74 and outputs it as an average clamp level.

The operation of the embodiment (1) of such an average value clamp level holding unit will be described with reference to a timing chart shown in FIG. 21. Line pulses A to C are generated when there is no superimposed signal. The switches 62 to 64 output the clamp level output from the clamp level holding unit 45 as shown in FIG. This is the line pulse A ~
This is because, since C is sequentially input, the clamp level held in the clamp level holding unit 45 also changes sequentially.

When the output levels of the switches 62 to 64 are held by the Ln line clamp level holding units 65 to 67, the output signal D of the clamp level holding unit 65 is held in the 21st line as shown in FIG. The holding section 66 outputs the output signal F holding the 22nd line, and the clamp level holding section 67 outputs the output signal F holding the 23rd line.

Therefore, these signals D to F are added to the adder 68.
21 is obtained, the respective levels become 1/3 when they are divided, and can be inverted and output as an average clamp level from the holding unit 77.

In this way, it is possible to hold the average clamp level for three horizontal lines.
FIG. 22 shows an embodiment (1) of the average value clamp level holding section having the analog configuration shown in FIG. 20, which is constituted by a digital circuit.

In this embodiment, the latch pulse generator 61
Are latched by flip-flops 81-83 instead of switches, and the output signals D-F of these flip-flops 81-83 are added by an adder 84. And sends it to the flip-flop 87 via the sign inverter 86.

The flip-flop 87 receives the latch pulse from the latch pulse generator 61 and outputs an average clamp level.

As described above, by storing a plurality of past clamp levels and further using the average value, it becomes unnecessary to perform the clamping operation of the front porch position as in the case of the preceding value clamp.

[0070]

As described above, according to the video signal processing circuit of the present invention, a superimposed signal in a video invalid portion in a video signal is detected, and the superimposed signal of the video signal is detected based on the presence or absence of the superimposed signal. Since the DC level is reproduced by holding the clamp level in the non-existent video invalid part, there is no problem such as loss of synchronization with NTSC signals in which the DC value of the pedestal level fluctuates arbitrarily. Can be transmitted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing in principle the configuration of a video signal processing circuit according to the present invention.

FIG. 2 is a block diagram showing an embodiment (1) of a superimposed signal detection unit used in the present invention.

FIG. 3 is an operation timing chart of an embodiment (1) of a superimposed signal detector used in the present invention.

FIG. 4 is a block diagram showing an embodiment (2) of a superimposed signal detector used in the present invention.

FIG. 5 is a block diagram showing an embodiment (3) of a superimposed signal detection unit used in the present invention.

FIG. 6 is an operation timing chart of an embodiment (3) of a superimposed signal detector used in the present invention.

FIG. 7 is a block diagram showing an embodiment (4) of a superimposed signal detection unit used in the present invention.

FIG. 8 is an operation timing chart of an embodiment (4) of a superimposed signal detection unit used in the present invention.

FIG. 9 is a block diagram showing an embodiment (1) of a clamp switching control unit used in the present invention.

FIG. 10 is an operation timing chart of an embodiment (1) of a clamp switching control unit used in the present invention.

FIG. 11 is a block diagram showing an embodiment (2) of a clamp switching control unit used in the present invention.

FIG. 12 is a block diagram showing an embodiment (1) of a clamp circuit used in the present invention.

FIG. 13 is an operation timing chart of the embodiment (1) of the clamp circuit used in the present invention.

FIG. 14 is a block diagram showing an embodiment (2) of a clamp circuit used in the present invention.

FIG. 15 is an operation timing chart of an embodiment (2) of the clamp circuit used in the present invention.

FIG. 16 is a block diagram showing an embodiment (3) of a clamp circuit used in the present invention.

FIG. 17 is an operation timing chart of the embodiment (3) of the clamp circuit used in the present invention.

FIG. 18 is a block diagram showing an embodiment (4) of a clamp circuit used in the present invention.

FIG. 19 is an operation timing chart of the embodiment (4) of the clamp circuit used in the present invention.

FIG. 20 is a block diagram showing an embodiment (1) of an average value clamp level holding unit used in the present invention.

FIG. 21 is an operation timing chart of an embodiment (1) of an average clamp level holding unit used in the present invention.

FIG. 22 is a block diagram showing an embodiment (2) of an average value clamp level holding unit used in the present invention.

FIG. 23 is a block diagram showing an example of a clamp circuit used in a conventional video signal processing circuit.

FIG. 24 is an operation timing chart of a conventional clamp circuit.

FIG. 25 is an operation timing chart in a case where additional information is present in a horizontal line portion in a conventional clamp circuit.

[Explanation of symbols]

1: superimposed signal detector, 2: clamp switching controller, 3: delay circuit, 4: clamp circuit, 5: A / D converter, 11:
Synchronization separation unit, 12: reference pattern generation unit, 13: vertical blanking period signal generation unit, 14: band rejection filter (BE
F), 15: arithmetic unit, 16: low-pass filter, 17:
A / D converter, 18: flip-flop, 19: arithmetic unit, 20: flip-flop, 21: level extraction timing generator, 22: level extractor, 23: A / D converter, 24: flip-flop, 31, 32: level monitoring unit, 33: OR gate, 34: latch circuit, 35: switching timing pulse generation unit, 36: synchronization separation unit, 37: holding circuit, 41: clamp unit, 42: synchronization separation unit, 43,
44: clamp pulse generation unit, 45: clamp level holding unit, 46: comparison unit, 47: clamp pulse generation unit, 4
8, 49: reference potential, 50: previous value clamp level holding unit, 51: average value clamp level holding unit, 61: line pulse generation unit, 62 to 64: switch, 65 to 67: L
n-line clamp level holding unit, 68: adder, 73:
Divider, 74: inverting amplifier, 77: holding unit, 81-8
3: flip-flop, 84: adder, 85: divider, 86: sign inverter, 87: flip-flop In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of the front page (72) Inventor Mitsunori Ohno 4-1-1 1-1 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (13)

[Claims] 1. A superimposed signal detector for detecting a superimposed signal in a video invalid portion of a video signal, a delay circuit for delaying the video signal by a predetermined time, and a clamp for generating a switching signal based on the presence or absence of the superimposed signal. A switching control unit; and a clamp circuit that holds a clamp level of the video signal output from the delay circuit by the switching signal in the video invalid portion where the superimposed signal does not exist and performs DC component reproduction of the video signal. A video signal processing circuit comprising: 2. The video signal processing circuit according to claim 1, wherein said superimposed signal detector detects a superimposed signal in a vertical blanking period of said video signal. 3. The video signal processing circuit according to claim 1, wherein said video invalid portion is a portion corresponding to a back porch position following each horizontal synchronization signal. 4. The video signal processing device according to claim 1, wherein said clamp switching control section has a circuit for generating said switching signal when a threshold value is exceeded regardless of the polarity of said superimposed signal. circuit. 5. The video signal processing circuit according to claim 1, wherein said clamp switching control section outputs said switching signal for each horizontal line. 6. The video signal processing circuit according to claim 1, wherein said clamp switching control section outputs said switching signal in field units. 7. The video signal according to claim 1, wherein the clamp circuit has a circuit for selecting a back porch position or a front porch position by the switching signal and holding a clamp level of the video signal. Processing circuit. 8. The apparatus according to claim 1, wherein the clamp circuit selects a back porch position or a sync tip position by the switching signal, and selects a reference potential corresponding to each position to hold a clamp level of the video signal. A video signal processing circuit, comprising: 9. The video signal of claim 1, wherein the clamp circuit selects a clamp level at the back porch position or a previous value clamp level holding the clamp level at the back porch position by the switching signal. A video signal processing circuit comprising a circuit for holding a clamp level for performing reproduction. 10. The clamp circuit according to claim 1, wherein the clamp circuit selects a clamp level at a back porch position or an average clamp level holding an average value of a plurality of clamp levels at all the back porch positions according to the switching signal. A video signal processing circuit comprising a circuit for holding a clamp level for performing DC reproduction of the video signal. 11. The video signal as claimed in claim 1, wherein the predetermined time allows the video signal to be held at a position other than the back porch position in the video invalid portion when the superimposed signal is present. A video signal processing circuit, characterized in that it is time to perform. 12. The video signal processing circuit according to claim 1, wherein said superimposed signal detection section and said clamp switching control section are constituted by analog circuits. 13. A video signal processing circuit according to claim 1, wherein said superimposed signal detection section and said clamp switching control section are constituted by digital circuits.