JPH09330937A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mold-seal a semiconductor device without deteriorating the characteristics of an element by a method wherein a cap layer is etched through a gate opening window, the cap layer under the lower side of an insulating layer is side-etched, a gate electrode is formed in the gate opening window and a cavity is formed of an element formation layer, the side surfaces of the cap layer, the insulating film and the gate electrode. SOLUTION: An SiO2 film 5 is grown on the whole upper surface of a cap layer 2, which is a gate formation region, and source and drain electrodes 3 are formed on prescribed positions on an element region. Then, a resist pattern 4 having an opening for gate window formation use is formed, the film 5 is etched using the pattern 4 as a mask, the pattern 4 is removed, a second layer SiO2 film 6 is grown, a semiconductor substrate is etched until the surface of the semiconductor substrate is exposed to obtain a gate opening window 9 with the open section having a projected curve toward the opening. Then, a resist pattern 7 for gate electrode film lift-off use is formed, the cap layer 2 is etched through the window 9, the insulating film is left over a recess part into an overhang shape and a cavity 12 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a T-type gate structure of a resin-sealed field effect transistor (FET) and its formation.

There is a demand for a gate structure that can maintain its performance even if a FET having a short gate length used in a μ-wave circuit or a high-speed logic circuit is resin-sealed.

[0003]

2. Description of the Related Art With the recent increase in the speed of transistors, the gate length is shrinking. Especially in high-performance transistors such as HEMT (High Electron Mobility Transistor),
The gate length has become less than 0.3 μm. However,
As the gate length is shortened, the gate resistance increases and the device characteristics deteriorate due to the increase of parasitic capacitance near the gate electrode.

In order to solve the contradictory problems of shortening the gate length and the gate resistance, as shown in FIG. 2, the cross-sectional shape of the gate electrode 11 is formed into a shape called T-shape or mushroom-shape, and the semiconductor substrate While reducing the contact area of the gate electrode and the gate length, the gate resistance is reduced by ensuring a large cross-sectional area of the gate electrode.

An example of a method of forming this T-type gate is shown in FIG. 3A to 3E are explanatory views of a conventional example of the manufacturing process of the T-type gate. In Fig. 3 (a), a resist pattern (resist for low-sensitivity electron beam) 13 and a wide upper opening that forms a narrow lower opening by using optical exposure using the electron beam direct writing method or the phase shift method. Pattern that forms the area (resist for high-sensitivity electron beam) 14
And the high-dose electron beam is applied to the aperture area.

In FIG. 3B, a low dose electron beam is applied to the opening region. In FIG. 3 (c), after development, T
A resist pattern 17 having an opening for forming a mold gate electrode is formed.

In FIG. 3D, a metal film for a gate electrode
Deposit 10 by vapor deposition. In FIG. 3 (e), the T-type gate electrode 11 is formed by lifting off the resist and removing the metal film on the resist pattern.

The HEMT device manufactured in this way is
High gain and low noise figure were obtained in the waveband, which made a great contribution to the progress of radio astronomy and to the reception of radio waves by artificial satellites that travel between planets, and also made it possible to receive satellite broadcasts. However, since practical application began in such a special field,
These devices are mounted in a metal hermetic package that can easily achieve high reliability.

Introducing a cheaper mold package instead of this expensive metal hermetic package will further spread the position measuring device using satellite broadcasting receivers and artificial satellites, and will enable automobiles utilizing millimeter waves. This is an essential issue for the development and commercialization of the collision prevention device.

[0010]

The device characteristics were evaluated by sealing the conventional device with a mold resin, but all the devices were defective and could not be measured. The failure mode was open gate electrode. The cause of this is shown in Fig. 4 (a).
This is because the gate electrode was peeled off and floated up due to the resin flow during molding and the stress during resin curing, as shown in FIG.

As a countermeasure against this, as shown in FIG. 4 (b), the element was covered with a polyimide resin and then sealed with a mold resin. At this time, too, the gate electrode was frequently opened, but the gain of the element that barely operated was significantly reduced. This is because the polyimide resin on the side wall of the gate electrode has parasitic capacitance C _gs (parasitic capacitance between gate and source), C
_The cause was that _gd (parasitic capacitance between gate and drain) was increased.

Further, as shown in FIG. 4 (c), when operating elements were selected and a general temperature cycle test was performed, the gate electrodes of all the elements were opened at the initial stage of the test. Oops. This is because the gate electrode floats due to repeated expansion and contraction of the polyimide resin.

The following attempts were made to more firmly fix the gate electrode. As shown in Figure 5, vapor phase growth
A silicon dioxide (SiO ₂ ) film was fixed by the (CVD) method so as to fill the lower part of the gate electrode and then sealed with a mold resin. This device did not cause initial opening of the gate electrode or defects in a simple temperature cycle test, but like the one covered with polyimide resin, the parasitic capacitance increased and the gain decreased and the noise figure increased. However, it was not practical.

From the above facts, in the conventional element structure having a gate length of 0.3 μm or less and the T-type electrode structure, the gate electrode is peeled off due to the flow of the molding resin and the stress of expansion and contraction, and the conventional element is not molded. It turned out that it could not be converted.

Therefore, an attempt was made to perform resin encapsulation after another means for avoiding an increase in parasitic capacitances C _gs and C _gd was taken.
The process will be described with reference to FIG. 6 (a) to 6 (e) are explanatory views of another conventional example.

In FIG. 6 (a), a source / drain electrode 3 is formed on a semiconductor substrate 1 and silicon dioxide (S
An insulating film 23 such as an iO ₂ ) film is formed, and then a resist package 24 for forming a gate electrode is formed.

In FIG. 6B, the insulating film 23 is etched by dry etching. At this time, the semiconductor substrate 1 is laterally etched (side etching) through the opening of the insulating film 23 generated by etching.
Perform over etching. The recess of the gate region of the semiconductor substrate formed in this process is called a recess.

In FIG. 6C, a gate electrode film 10 is deposited on the semiconductor substrate so as to cover the opening of the insulating film and contact the semiconductor substrate. Then, a resist mask 25 for forming a gate electrode is formed thereon.

In FIG. 6D, the gate electrode film 10 is dry-etched to form a gate electrode 11. FIG. 6 (e) is an enlarged view of the electrode portion. In this structure, the recess under the insulating film near the gate electrode is hollow, preventing an increase in parasitic capacitance.

The device characteristics of the HEMT having the above structure were sufficient as a product. When this device was molded and sealed,
There is no defect that the gate electrode is open, and parasitic capacitance
The increase of C _gs and C _gd was significantly suppressed, and although the characteristics varied slightly, they satisfied the product specifications.

Next, in order to evaluate the reliability of this device, a high-temperature current test was conducted.
I _gso , I _gdo , G _m increase, and gate voltage V _gso , V
_{The gdo} decreased, and the currents I _dss and G _m fluctuated.

Further, a temperature cycle test was conducted in which temperatures of −65 ° C. and 175 ° C. were alternately repeated, and the gate of a considerable sample was opened. This phenomenon was more remarkable in devices with shorter gate lengths. As a result of investigating the cause, the following was found.

FIGS. 7 (a) and 7 (b) are explanatory views of problems of the cavity type element. (1) Differences in the thermal expansion coefficients of the semiconductor, insulating film, gate electrode and resin of the device, and the stress that peels the gate electrode from the surface of the insulating film due to the temperature cycle causes a slight difference between the insulating film and the gate electrode. A gap is created, and outside air such as the organic component of the resin and water enters and enters the cavity of the recess area,
Contamination of semiconductor surface, resulting in instability and deterioration of characteristics
(See Figure 7 (a)). (2) In a short gate length FET, the upper part of the electrode floats up due to repeated stress due to similar temperature changes, and at the same time, the opening size of the gate electrode is small, causing electrode breakage inside the insulating film (Fig. 7 (b )).

It is an object of the present invention to provide a gate electrode structure which enables mold sealing without deteriorating device characteristics.

[0025]

Means for Solving the Problems To solve the above problems, 1) a step of forming an insulating film on a cap layer made of a semiconductor deposited on an element forming layer made of a semiconductor and the cross-sectional shape of an opening are Forming in the insulating film a gate opening window having a convex curve with respect to the opening and expanding upward, and etching the cap layer through the gate opening window using the insulating film as an etching mask, Subsequently, a step of forming a recess by side-etching the cap layer under the insulating film to form a recess, and forming a gate electrode film by covering the gate opening window and forming a gate electrode, A method for manufacturing a semiconductor device, including the step of forming a cavity with the surface of the element forming layer, the side surface of the cap layer, the insulating film and the gate electrode, or 2) a curve of a cross-sectional shape of the gate opening window The semiconductor according to 1 above, wherein an angle between the tangent of the curve at the intersection with the center line of the thickness of the insulating film and the surface of the element forming layer is 50 to 75 °, and the thickness of the insulating film exceeds 0.2 μm. A method for manufacturing the device, or 3) the insulating film is composed of two layers, and after depositing the lower insulating film,
4. The method for manufacturing a semiconductor device as described in 1 above, wherein an opening is provided, an upper insulating film is deposited to include the opening, and the gate opening window is formed by dry etching, or 4) The gate opening window is formed in the insulating film. 2. The method for manufacturing a semiconductor device according to 1 above, in which, when forming a film, a high-resolution type resist film is used as an upper layer and a high-sensitivity type resist film is used as a lower layer to form a two-layer structure Or 5) It is achieved by a resin-sealed semiconductor device manufactured by including the method described in 1 above.

Next, the operation of the present invention will be described. The change in characteristics due to contamination does not occur in the conventional gate electrode structure having no cavity opened in the insulating film on the semiconductor surface, but only in the gate electrode structure having a cavity in the recess structure. In this way, the cavity recess structure is very sensitive to contamination, but it was judged that other structures are difficult to reduce the parasitic capacitance.

Here, in order to secure the airtightness, that is, the adhesive force between the insulating film and the gate electrode, the contact area between the gate electrode and the insulating film may be increased, but the problem is remarkable when the gate length is 0.3 μm or less. However, in such an element, an increase in the size of the electrode or element leads to a deterioration in performance.

Therefore, in the present invention, attention is paid to the shape of the contact portion in order to obtain high peeling resistance in a small area. In the conventional electrode structure, there is a corner near the top of the gate window of the insulating film. The stress concentrates on this corner, the gate electrode floats up from the insulating film, and since the wall surface inside the window is nearly vertical, the adhesion between the electrode and the insulating film is poor, and the electrode is cut or a contamination path is formed. It was

Therefore, as a result of the experiment, it was found that a gentle curve where the wall surface inside the window is convex to the opening as shown in FIG. 8 (a) is effective. It was also found that even if the curve is gentle as shown in Fig. 8 (b), if there is an S-shaped depression, the electrode peels from this part.

In a device having a gate length of 0.3 μm or less, as a structure in which the gate electrode does not become excessively large and a sufficient adhesive force is obtained, as shown in FIG.
The angle between the tangent line drawn at the point where the curve of the cross-sectional shape intersects the horizontal line of 1/2 the thickness of the insulating film and the horizontal plane is 50 to 75 °, and the thickness of the insulating film must be 0.2 μm or more. I understood.

In the present invention, by adopting the above structure,
By maintaining the airtightness of the recess cavity, deterioration of the device characteristics is not caused, and by enclosing the gate electrode with an insulating film and mechanically protecting it, mold sealing is possible.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION HEMTs according to embodiments of the present invention will be described below.
The field structure will be described together with its manufacturing process with reference to FIG.

1 (a) to 1 (f) are explanatory views of an embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is GaAs
Cap layer, 3 source / drain electrodes, 4 positive photoresist pattern for forming gate window, 5 first layer SiO ₂ film, 6 second layer SiO ₂ film, 7 gate electrode film Positive photoresist pattern for lift-off, 8 is the final insulating film, 9 is the gate opening window, 10 is the gate electrode film on the resist film, 11 is the gate electrode, 12 is under the insulating film on the recess. It is the formed cavity.

In FIG. 1 (a), a semiconductor substrate 1 is used which has been subjected to element isolation by an ion implantation method, and a 0.3 μm-thick first layer is formed on the entire surface of the cap layer 2 in a region where a gate is formed. A SiO ₂ film 5 is grown to form a source / drain electrode 3 at a predetermined position on the device region.

Next, as the first step of forming the gate window, a resist pattern 4 having an opening size of about 0.4 μm is formed,
Using this as a mask, the SiO ₂ film 5 is dry-etched.
In FIG. 1 (b), the resist pattern 4 is removed.

Next, the Si of the second layer having a thickness of about 0.4 μm
O ₂ film 6 is grown. In Fig. 1 (c), anisotropic etching is performed by reactive ion etching (RIE) until the semiconductor surface is exposed. The upper opening size is about 0.6 in this process.
A gate opening window 9 is obtained which has a lower opening size of about 0.2 μm and a curve whose opening cross section is convex (convex upward) toward the opening. The angle between the curve and the semiconductor surface is about 65 °.

Next, a positive photoresist pattern 7 for lift-off of the gate electrode film is formed. In FIG. 1 (d), the GaAs cap layer 2 is etched through the gate opening window 9 to a desired depth by dry etching with weakened anisotropy.

This dry etching was performed by optimizing various conditions such as the configuration of the apparatus, gas selection, gas pressure, and input power. In performing this optimization, the upward convex curved opening shape is one factor for increasing the radical density of the etching gas, and side etching is performed by weakening the anisotropy to form the recess. .

In this manner, the cavity 12 can be formed by leaving the insulating film, which serves as an etching mask, in the form of an eaves above the recess. Next, an example of etching conditions for forming the gate opening window is shown.

Reaction gas: CCl ₂ F ₂ 30 SCCM + He 60 SCCM Gas pressure: 4.0 Pa RF power: 70 W Substrate temperature: 38 ° C. In FIG. 1 (e), aluminum (Al) was used as the gate electrode films 10 and 11. A film is formed, and unnecessary aluminum film 10 on resist pattern 7 is lifted off to form gate electrode 11.

FIG. 1 (f) is an enlarged view of the gate electrode portion.
The sectional shape of the completed gate electrode is T-shaped,
12 is surrounded by the semiconductor surface, the side wall of the cap layer, the eaves-shaped insulating film, and the side wall of the gate electrode, and the cavity is hermetically sealed by the close contact between the gently curved side wall of the insulating film and the gate electrode. .

Next, another embodiment of the HEMT device will be described. Similar to the previous embodiment, after forming the opening with the gently curved side wall in the insulating film, the resist pattern for lift-off is not formed, and the recess structure and the eave structure are formed by overetching the cap layer. To do.

Next, in order to stabilize the semiconductor surface of the recessed portion, a thin silicon nitride (Si ₃ N ₄ ) film is grown by a photo vapor deposition (CVD) method through an insulating film opening window, and an insulating window having an opening window is formed again. Using the film as a mask, the Si ₃ N ₄ film on the semiconductor surface is removed by RIE to form a gate window.

Next, by the magnetron sputtering method,
After depositing the WSi film to be the gate electrode on the entire surface and performing heat treatment for removing the semiconductor damage, a gold (Au) -based gate electrode pattern is formed on the WSi film and other unnecessary WSi film is formed. After removal by etching, a device having a gate electrode structure according to the present invention was manufactured.

In the formation of the positive photoresist pattern 7 in the above process, a high resolution type (for example, TSMR-V50 manufactured by Tokyo Ohka) is used as the upper layer and a high sensitivity type is used as the lower layer.
(For example, OFPR7450 manufactured by Tokyo Ohka Co., Ltd.) is used as a two-layer resist structure, exposed by a reduction projection exposure apparatus, and developed to have a sectional shape suitable for lift-off with a narrow entrance and a wide bottom as shown. be able to.

The devices shown in the above two embodiments had device characteristics equivalent to or higher than those of the HEMTs of the embodiments. The process for realizing the gate electrode structure of the present invention is not limited to the above embodiment. Moreover, the present invention is effective not only for HEMT formation but also for other short channel elements.

[0047]

The resin-encapsulated short-channel transistor according to the present invention has no increase in parasitic capacitance, has a high gain and a low noise figure in the μ-wave band, and is suitable for temperature cycle tests, high-temperature current tests, and high-temperature humidity resistance tests. As a result, a highly reliable element capable of maintaining sufficient performance can be obtained.

Further, it becomes possible to supply the HEMT element which has been put to practical use only with a hardened metal package in the past with an inexpensive mold package. As a result, wider application fields of short-channel FETs can be developed into the millimeter wave band.

Further, the present invention can be applied not only to the μ-wave device but also to a high-speed logic circuit device, and can be applied not only to the molding of a single device but also to the molding packaging of a semiconductor device including a short channel device. .

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional gate electrode (1)

[Figure 3] Illustration of the conventional example of the process (1)

FIG. 4 is an explanatory diagram of the problems of the conventional example (1)

FIG. 5 is a sectional view of a conventional gate electrode (2)

[Figure 6] Illustration of the conventional example of the process (2)

FIG. 7 is an explanatory diagram of problems of the conventional example (2)

FIG. 8 is an explanatory diagram of the operation of the present invention.

[Explanation of symbols]

1 semiconductor substrate 2 GaAs cap layer 3 source / drain electrode 4 positive photoresist pattern for gate window formation 5 first layer SiO ₂ film 6 second layer SiO ₂ film 7 positive for lift-off of gate electrode film -Type photoresist pattern 8 Insulation film in final shape 9 Gate opening window 10 Gate electrode film on resist film 11 Gate electrode 12 Cavity formed under insulation film on recess

Claims (5)

[Claims] 1. A step of forming an insulating film on a cap layer made of a semiconductor, which is deposited on an element forming layer made of a semiconductor, and then the cross-sectional shape of the opening has a convex curve with respect to the opening. And forming a gate opening window that expands upward in the insulating film, and then etching the cap layer through the gate opening window using the insulating film as an etching mask, followed by overetching the insulating layer. A step of side-etching the cap layer on the lower side of the film to form a recess, and then depositing a gate electrode film to cover the gate opening window to form a gate electrode, and to form a surface of the element forming layer. A method of manufacturing a semiconductor device, comprising: forming a cavity between the side surface of the cap layer, the insulating film, and the gate electrode. 2. An angle between a tangent to the curve of the cross-sectional shape of the gate opening window and the center line of the thickness of the insulating film and the surface of the element forming layer is 50 to 75 °, and The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the insulating film exceeds 0.2 μm. 3. The insulating film comprises two layers, an opening is provided after depositing a lower insulating film, an upper insulating film is deposited including the opening, and dry etching is performed to form the gate opening window. The method for manufacturing a semiconductor device according to claim 1, wherein 4. When forming the gate opening window in the insulating film, a high-resolution type resist film is formed as an upper layer, and a high-sensitivity type resist film is formed as a lower layer in a two-layer structure resist film. The method of manufacturing a semiconductor device according to claim 1, wherein the exposure is performed. 5. A semiconductor device manufactured by including the method according to claim 1. Description: