JPS58159381A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form gate length thin in accordance with the design, and moreover to obtain a stabilized gate withstand voltage by a method wherein a part of the bottom of a concave part formed in a semiconductor active layer is exposed, and an electrode layer is formed by adhesion of the semiconductor active layer exposed in an insulating film. CONSTITUTION:The concave part 31 is formed in the GaAs active layer 8, and the second layer insulating film 11 is adhered. When directional etching is performed in this condition, the second layer insulating film 11 adhered on the bottom in the concave part 31 is removed by width nearly the same with L2 shown in the figure. After a metal 5 for formation of the gate is evaporated on the whole surface, a mask is formed by a photo resist 12, etc., as to cover an window in SiO2 layers 6, 11', and etching is performed. Accordingly structure as shown in the figure can be formed, and enlargement of gate length according to creeping of the adhering metal is not generated. Moreover even when the halo phenomenon is generated, because the island type metal adheres only on the insulating film 6, no influence is affected to the withstand voltage between the gate and a drain. Accordingly the stabilized gate withstand voltage can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schottky barrier field effect transistor (hereinafter referred to as 88FET) used in, for example, a microwave band.
Regarding the reform of the law.

For example, an 88FET made of GaAs (gallium arsenide) has excellent characteristics as an element that performs low noise amplification and high output amplification in the microwave band. For this purpose, 1. Reduce the gate length Lg. 2. Reduce the source series resistance Rs. 3. Reduce the gate resistance. 4. Increase the source-drain breakdown voltage (VD).
, Measures such as increasing the gate-drain breakdown voltage BVGD are used.

As a structure that satisfies these claims, l! An FET with a so-called overlay recess structure as shown in Figure 1 has been proposed. This structure can reduce the source series resistance and gate resistance, and is also excellent in mass production.杢结at - To explain, a series of methods for creating the part near the gate is shown.
On the surface of the GaAs active layer 4, an insulating film (for example, 8i0
．． 3, remove the insulating film at the area where the gate is to be formed using a photoresist (not shown) as a mask, and then remove the photoresist. Next, remove the remaining insulating film 3. Using this as a mask, the GaAs active layer 4 is etched to form the recesses 30 to obtain the thickness of the GaAs active layer that provides the desired device characteristics. Thereafter, a gate metal is deposited on the entire surface, and a photoresist or the like is processed so as to surround the etched insulating layer portion, and using this as a mask, the gate metal is etched to form a gate electrode 1. In this way an overlay recess structure can be formed. Note that 2 is a source/drain electrode made of ohmic metal that is formed before forming the insulating layer 3.

However, the above structure has the following drawbacks, which are independent of the manufacturing method.

1. When etching the GaAs active layer 4 and depositing the gate electrode gold rj41 on the surface, the deposited metal is not formed in the window shape of the insulating layer, but actually wraps around, as shown in Figure 1. (like a window), the characteristics deteriorate with a large gate length.

2. The gate gold l11 adheres to the inner bottom surface of the recess 30 in spots in the form of islands (hereinafter abbreviated as a halo phenomenon).

As a result, characteristics and reliability deteriorate.

The disadvantage of the gate forming method described up to t'L is that the entire surface of the saw active layer 4 is exposed. For this reason, when metal 1 wraps around, the gate length increases until it reaches the point where it wraps around.
If a halo phenomenon occurs, it will occur on the GaA1 surface where current can flow between the gate and drain, thereby degrading the gate breakdown voltage.

The present invention eliminates the above-mentioned drawbacks, makes the gate length as narrow as designed, and provides stable gate breakdown voltage69.
Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a sectional view showing one example #1ii143 of the present invention.

The features of this structure and its manufacturability are shown in Figures 3 to 6.
As shown in the figure, after depositing an insulating film (for example, 810. film) 6 on the direct surface of the GaAs active layer 8, 8i02 at the site where the gate is to be formed is removed using photoresist or the like.
@Figure 3), then the photoresist is also removed.

Using the oxide film 6 remaining on the GaAs active layer 8 as a mask, a predetermined drain-source saturation current CIDIIIm
) to form the recess 31.

After that, the insulating film of @2111 (
For example, 8i0ri11 is applied.

When the second layer insulating film 11 is etched using directional etching (reactive ion etching) in the state shown in Figure @4, the paste in Figure @4 is etched.

The second layer of insulation 1Ill deposited on the bottom surface within the recess 31 is removed with a width approximately equal to . As a result, as shown in Figure @5, GaAsg
is exposed, and both yokes are exposed at 810.11'. Note that even if the second layer insulating film 11 is overetched, the same structure as shown in FIG. 5 can be obtained if the first layer insulator 6 is sufficiently thick. At this time, G by directional etching
If there is a damaged layer on the aAs811 plane, after obtaining the structure shown in Figure @5, it will be further increased by 200 to 1000 A! [Ga
As B may be etched.

Then, gold-5 for gate formation is deposited on the entire surface. After that, a mask is formed using photoresist 12 or the like so as to cover the sto, 6° 11' windows, and etching is performed to form the second window.
A structure as shown in the figure can be formed.

Note that 7 is a source/drain electrode. In addition, in Figure 2, 8i0!6 and 11' shown in Figure 6 are combined into 6
′.

As shown in FIG. 2 (the exposed part of GaAs 8 is approximately the same width as the large window of the insulating film 6, the gate length Lg is the same size as the 810° window even if the gate thickness is reduced to t). The gate length does not increase due to the thickness of the deposited metal.Even if a halo phenomenon occurs, the island-like metal is only attached to the insulating film 6, so the gate length between the gate and drain is not increased. This does not affect the breakdown voltage of the gate, so a stable gate breakdown voltage can be obtained.

Although GaAs S B FET has been described here, it is obvious that it can also be applied to other 88FETs. Furthermore, any combination of the first insulating film and the second insulating film can be realized.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing a conventional overlay recess structure, Fig. 2 is a sectional view showing an overlay recess structure according to an embodiment of the present invention, and Figs. 3 to 6 are! 2
FIG. 3 is a cross-sectional view of a manufacturing process showing an example of making the structure shown in the figure. 1.5... Gate electrode, 2.7 Old... Source/drain electrode, 3, 6.6', 11.11' Old...
sto, etc. insulating layer, 4, 8...-GaAs
Active layer, 12...Photoresist, 30.3
1... Concavity. Graduation 1 figure is skewered Z times 3 times 40 'JiI-ta figure'+- is turned

Claims (1)

[Claims] The droplet conductor active layer has a recess, an insulating film is formed in the recess exposing a part of the bottom surface, and an electrode layer is formed and adhered to the hand conductor active layer exposed by the insulating film. A hand conductor device characterized by: