JPH0766384A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Purpose] A via hole and a heat dissipation hole of a semiconductor device are formed in one step. [Structure] On the main surface of the semi-insulating GaAs substrate 1,
A high output FET (not shown), a gate electrode 2, a source electrode 3 and a drain electrode 4 are formed and covered with an insulating film 5. Next, after thinning the back surface of the semi-insulating GaAs substrate 1, the size of the mask pattern 6b for forming a via hole is formed larger than the size of the mask pattern 6b for forming a heat dissipation hole on the back surface of the semi-insulating GaAs substrate. Mask pattern 6b
On the other hand, the semi-insulating GaAs substrate 1 is etched until the source electrode 3 is exposed to form a via hole. As a result, a semi-insulating GaAs substrate 1 is provided with a non-penetrating heat dissipation hole 7 for the mask pattern 6a. Next, a desired plating base metal layer 9 is formed on the entire back surface, and A
u plating 10 is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor provided with a via hole and a heat dissipation hole for a high frequency power device or the like which is composed of active elements such as field effect transistors and bipolar transistors and passive elements such as inductance and capacitors. The present invention relates to a method for manufacturing a device.

[0002]

2. Description of the Related Art High-frequency power semiconductors such as field effect transistors (hereinafter referred to as FETs) and bipolar transistors are used as semiconductor devices for mobile communication and satellite communication because of their high speed and high efficiency. With the expansion of information communication systems, high-power semiconductor devices that operate in a higher frequency band are desired.

In order to achieve this purpose, it is necessary to improve heat dissipation efficiency and reduce parasitic capacitance and inductance. If the heat dissipation is insufficient, the semiconductor for power amplification heats up, and it becomes difficult for current to flow, so the output power decreases, and the wiring length of the bonding wire greatly affects the electrical characteristics of the element. In particular, when the power amplification semiconductor is grounded, the wiring is laid out on the semiconductor substrate and the bonding wire appears as an inductance, so that complete grounding cannot be obtained, leading to deterioration of the high frequency characteristics of the semiconductor device.

For example, in a microwave monolithic IC (MMIC) using GaAs, the thermal conductivity of the GaAs substrate is low. Therefore, in order to reduce the thermal resistance, the GaAs substrate is thinned to 100 μm or less and a heat sink is provided, or the ground inductance is reduced. In order to reduce the number, a method of opening a via hole in the source electrode of the FET and metallizing the inside with a metal (gold or the like) having a high thermal conductivity is used.

A conventional method of manufacturing the above-described semiconductor device will be described below with reference to the drawings. FIG. 3 is a schematic cross-sectional view of a manufacturing process for explaining a conventional method for manufacturing a semiconductor device having a via hole and a heat dissipation hole. First, as shown in FIG. 3A, the semi-insulating GaAs substrate 1
A high-frequency / high-power FET (not shown), a gate electrode 2, a source electrode 3, and a drain electrode 4 are formed on one main surface and covered with an insulating film 5.

Next, as shown in FIG.
The back surface of the semi-insulating GaAs substrate 1 of (a) is mechanically or chemically thinned to a desired thickness, and a resist or a resist is formed on the back surface of the thinned semi-insulating GaAs substrate 1 according to the position of the drain electrode 4. A pattern 6a is formed using an insulating film, and a non-penetrating heat dissipation hole 7 is formed in the semi-insulating GaAs substrate 1 by etching using this as a mask, and the pattern 6a is removed.

Next, as shown in FIG. 3 (c), a pattern 6b is formed on the back surface (opposite main surface) of the semi-insulating GaAs substrate 1 in accordance with the position of the source electrode 3 using a resist or an insulating film. Formed and used as a mask for semi-insulating G
The aAs substrate 1 is etched until the source electrode 3 is exposed to form a via hole 8. Next, as shown in FIG. 3D, the pattern 6b used for the mask is removed, a desired plating base metal layer 9 is formed on the entire back surface, and Au plating 10 is applied.

FIG. 4 is a sectional schematic view of a manufacturing process for explaining another conventional method for manufacturing a semiconductor device. 4, the same reference numerals as those in FIG. 3 indicate the same or corresponding portions. First, as shown in FIG. 4A, semi-insulating Ga
A high-frequency / high-power FET, a gate electrode 2, a source electrode 3, and a drain electrode 4 are formed on one main surface of the As substrate 1.
Cover with insulating film 5.

Next, as shown in FIG.
The main surface side of the semi-insulating GaAs substrate 1 of (a) is attached to a supporting plate 12 such as a quartz substrate using wax 13, and the back surface (opposite main surface) of the semi-insulating GaAs substrate 1 is mechanically or chemically desired. The drain electrode 4 on the back surface (opposite main surface) of the thinned semi-insulating GaAs substrate 1.
A mask pattern 6a is formed by using a resist or an insulating film in accordance with the position of 1), and a non-penetrating heat dissipation hole 7 is formed in the semi-insulating GaAs substrate 1 by etching using this as a mask, and the mask pattern 6a is removed. .

Next, as shown in FIG. 4 (c), a mask pattern 6b is formed on the back surface of the semi-insulating GaAs substrate 1 by using a resist or an insulating film in accordance with the position of the source electrode 3, and As a mask for semi-insulating GaAs
The substrate 1 is etched until the source electrode 3 is exposed, the via hole 8 is formed, and the mask pattern 6b is removed.

Next, as shown in FIG. 4D, a desired plating base metal layer 9 is formed on the entire back surface (opposite main surface) of the semi-insulating GaAs substrate 1, and Au plating 10 is applied. Next, as shown in FIG. 4E, after the semi-insulating GaAs substrate 1 is peeled from the support plate 12, the semi-insulating GaAs substrate 1 is fixed to the opposite main surface side in order to fix the semi-insulating GaAs substrate 1. A vinyl sheet 14 is attached and chips are divided in the dicing area 11.

[0012]

However, in the conventional method of manufacturing a semiconductor device shown in FIGS. 3 and 4, since the heat dissipation hole and the via hole are formed separately, the complexity of the process increases and the process There are problems that the reliability and yield are deteriorated and the device characteristics are deteriorated.

In view of the above problems, it is an object of the present invention to provide a semiconductor device manufacturing method capable of easily manufacturing a semiconductor device having a via hole and a heat dissipation hole.

[0014]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming an active element on one main surface of a semiconductor substrate and a step of forming a ground electrode of the active element on an opposite main surface of the semiconductor substrate. The step of forming the via-hole opening mask and the heat-dissipating hole opening mask in the region directly below the active element so that the size of the via-hole opening mask is larger than that of the heat-dissipating hole opening mask, and the opposite main surface of the semiconductor substrate. Through the opening mask for the via hole and the opening mask for the heat dissipation hole to simultaneously form the via hole in which the ground electrode of the active element is exposed and the heat dissipation hole not penetrating the semiconductor substrate, and on the opposite main surface of the semiconductor substrate. Forming a backside metal layer.

A method of manufacturing a semiconductor device according to claim 2 is
A step of forming an active element on one main surface of the semiconductor substrate, a step of attaching the semiconductor substrate to a supporting plate, and a via hole for the ground electrode of the active element on the opposite main surface of the semiconductor substrate while being attached to the supporting plate. Forming the opening mask for heat dissipation holes and the opening mask for heat dissipation holes in the region directly below the active element so that the size of the opening mask for via holes is larger than the size of the opening mask for heat dissipation holes, and with the state of being attached to the support plate. A step of simultaneously forming a via hole in which the ground electrode of the active element is exposed by etching the opposite main surface of the semiconductor substrate through an opening mask for a via hole and an opening mask for a heat dissipation hole and a heat dissipation hole not penetrating the semiconductor substrate, and supporting the same. The step of forming a backside metal layer on the opposite main surface of the semiconductor substrate when it is attached to the plate, and the opposite of the semiconductor substrate when it is attached to the support plate. And a step Keru sticking a sheet for expanding the chip surface, a step of peeling the semiconductor substrate from the support plate, and a step of dicing the semiconductor substrate in a state attached on the sheet.

[0016]

According to the method of manufacturing a semiconductor device of claim 1, an active element is formed on one main surface of a semiconductor substrate, and an opening mask for a via hole of a ground electrode of the active element is formed on the other main surface of the semiconductor substrate. And the heat dissipation hole opening mask immediately below the active element so that the size of the via hole opening mask is larger than that of the heat dissipation hole, and the opposite main surface of the semiconductor substrate is connected to the via hole opening mask and the heat dissipation hole. By etching through the hole opening mask, a via hole in which the ground electrode of the active element is exposed and a heat dissipation hole not penetrating the semiconductor substrate are formed at the same time, and a back surface metal layer is formed on the opposite main surface of the semiconductor substrate. Compared to the case where the heat dissipation hole and the heat dissipation hole are formed separately, the process can be simplified, the process reliability and yield are improved, and the element characteristics are stable. .

According to a second aspect of the method of manufacturing a semiconductor device, the semiconductor substrate is attached to the supporting plate and the opposite main surface of the semiconductor substrate is etched through the opening mask for via holes and the opening mask for heat dissipation holes. Since a via hole and a heat dissipation hole are simultaneously formed on the substrate, a sheet for expanding the chip is attached to the back surface of the semiconductor substrate while being attached to the support plate, the semiconductor substrate is peeled from the support plate, and the semiconductor substrate is diced. Compared to the case where the holes and the heat dissipation holes are formed separately, the process can be simplified, the process reliability and yield are improved, and a chip having excellent element characteristics can be obtained.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device manufacturing method according to the present invention will be described.
A description will be given with reference to the drawings. 1 (a) to 1 (d) are sectional structural views of a manufacturing process of a semiconductor device having a via hole and a heat dissipation hole showing a first embodiment of the present invention.
1, the same reference numerals as those in FIGS. 3 and 4 denote the same or corresponding parts. The first embodiment will be described below with reference to the drawings.

First, as shown in FIG. 1A, a high frequency / high power FET (not shown), a gate electrode 2, a source electrode 3 and a drain electrode 4 are provided on one main surface of a semi-insulating GaAs substrate 1. It is formed and covered with the insulating film 5. Next, FIG. 1 (b)
As shown in FIG. 5, after the back surface (opposite main surface) of the semi-insulating GaAs substrate 1 is mechanically or chemically thinned to a desired thickness (tens of μm), the back surface (opposite main surface) of the semi-insulating GaAs substrate 1 is thinned. ), A pattern 6b is formed using a resist or an insulating film aligned with the source electrode 3 for forming a via hole, and a resist or an insulating film is aligned with the drain electrode 4 for forming a heat dissipation hole. The mask pattern 6a is formed. Since the size of the mask pattern 6b is larger than that of the mask pattern 6a, the semi-insulating GaAs substrate 1 is etched with respect to the mask pattern 6b until the source electrode 3 is exposed, and the via hole 8 is formed. When opened, a radiating hole 7 is formed in the semi-insulating GaAs substrate 1 so as not to penetrate the mask pattern 6a.

Next, as shown in FIG. 1C, the patterns 6a and 6b are removed, and a desired plating base metal layer 9, such as Ti (titanium) or Au, is formed on the entire back surface (opposite main surface).
(Gold) is formed and Au plating 10 is applied. As shown in this embodiment, by forming the via hole 8 and the heat dissipation hole 7 at the same time, the process can be simplified, the process reliability and yield can be improved, and the element characteristics can be stabilized.

2 (a) to 2 (e) are cross-sectional structural views of a manufacturing process of a semiconductor device having a via hole and a heat dissipation hole showing a second embodiment of the present invention. 2, the same reference numerals as those in the conventional example of FIGS. 3 and 4 indicate the same or corresponding portions. The second embodiment will be described below with reference to the drawings. First, as shown in FIG. 2A, a high frequency / high power FET is formed on one main surface of the semi-insulating GaAs substrate 1.
A gate electrode 2, a source electrode 3, and a drain electrode 4 (not shown) are formed and covered with an insulating film 5.

Next, as shown in FIG.
One main surface side of the semi-insulating GaAs substrate 1 of (a) is pasted on a supporting plate 12, for example, a quartz substrate or a silicon substrate using a wax 13, and in this state, the semi-insulating GaAs substrate 1 is formed.
After the back surface (opposite main surface) of the substrate 1 is mechanically or chemically thinned to a desired thickness (tens of μm), semi-insulating G
On the back surface (opposite main surface) of the aAs substrate 1, a pattern 6b is formed using a resist or an insulating film in alignment with the source electrode 3 for forming a via hole, and in alignment with a drain electrode 4 for forming a heat dissipation hole. Then, the pattern 6a is formed using a resist or an insulating film. Here, since the size of the pattern 6b is larger than that of the pattern 6a, the semi-insulating G
When the via hole 8 is opened by etching the aAs substrate 1 until the source electrode 3 is exposed, the semi-insulating GaAs substrate 1 is provided with a non-penetrating heat dissipation hole 7 for the pattern 6a.

Next, as shown in FIG. 2C, the patterns 6a and 6b are removed, and a desired plating base metal layer 9, such as Ti (titanium) or Au, is formed on the entire back surface (opposite main surface).
(Gold) is formed, and Au plating is performed on the plating base metal layer 9 1
0 is applied. Next, as shown in FIG. 2D, the support plate 1
2 is attached, a vinyl sheet 14 for expanding is attached to the back surface (opposite main surface) of the semi-insulating GaAs substrate 1 on which the heat dissipation electrode is formed, and then the semi-insulating GaAs substrate 1 is peeled from the support plate 12. By dividing the chip in the dicing area 11 and expanding the vinyl sheet 14, a desired chip is obtained.

[0024]

According to the method of manufacturing a semiconductor device of the first aspect, an active element is formed on one main surface of a semiconductor substrate, and a via hole for a ground electrode of the active element is formed on the other main surface of the semiconductor substrate. The opening mask and the opening mask for the heat dissipation hole in the region directly below the active element are formed so that the size of the opening mask for the via hole is larger than that of the opening mask for the heat dissipation hole, and the opposite main surface of the semiconductor substrate is opened for the via hole. By etching through the mask and the heat dissipation hole opening mask, the via hole in which the ground electrode of the active element is exposed and the heat dissipation hole not penetrating the semiconductor substrate are simultaneously formed, and the back surface metal layer is formed on the opposite main surface of the semiconductor substrate. Compared to the case where via holes and heat dissipation holes are formed separately, the process can be simplified, the process reliability and yield are improved, and the device characteristics are improved. Stable.

According to the method of manufacturing the semiconductor device of the second aspect, the back surface of the semiconductor substrate attached to the supporting plate is obtained by etching the opposite main surface of the semiconductor substrate through the opening mask for via holes and the opening mask for radiation holes. A via hole and a heat dissipation hole are simultaneously formed from (opposite main surface), and a sheet for expanding the chip is attached to the back surface (opposite main surface) of the semiconductor substrate while being attached to the support plate, and the semiconductor substrate is attached to the support plate. Peel it off, dice the chip and expand the expanding sheet,
Compared to the case where the via hole and the heat dissipation hole are formed separately, the process can be simplified, the process reliability and yield are improved, and a chip having excellent element characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional structural view showing a first embodiment of a manufacturing process of a semiconductor device of the present invention.

FIG. 2 is a sectional structural view showing a second embodiment of the manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a cross-sectional structure diagram showing a first conventional semiconductor device manufacturing method.

FIG. 4 is a cross-sectional structure diagram showing a second conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Semi-Insulating GaAs Substrate 2 Gate Electrode 3 Source Electrode 4 Drain Electrode 5 Insulating Film 6a Pattern 6b Pattern 7 Heat Dissipation Hole 8 Via Hole 9 Plating Base Metal Layer 10 Au Plating 11 Dicing Area 12 Supporting Plate 13 Wax 14 Vinyl Sheet

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Osamu Ishikawa 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A step of forming an active element on one main surface of a semiconductor substrate, and an opening mask for a via hole of a ground electrode of the active element and heat radiation on a region directly below the active element on the opposite main surface of the semiconductor substrate. Forming an opening mask for holes so that the dimensions of the opening mask for via holes are larger than the dimensions of the opening mask for heat dissipation holes; and forming an opposite main surface of the semiconductor substrate on the opening mask for via holes and the heat dissipation. Simultaneously forming the via hole in which the ground electrode of the active element is exposed by etching through a hole opening mask and the heat dissipation hole not penetrating the semiconductor substrate, and a back metal layer on the opposite main surface of the semiconductor substrate. And a step of forming a semiconductor device. 2. A step of forming an active element on one main surface of a semiconductor substrate, a step of attaching the semiconductor substrate to a support plate, and a step of attaching the semiconductor element to the support plate on the opposite main surface of the semiconductor substrate in a state of being attached to the support plate, The via hole opening mask of the ground electrode of the active element and the heat dissipation hole opening mask in the region directly below the active element are formed such that the size of the via hole opening mask is larger than the size of the heat dissipation hole opening mask. And a via electrode in which the ground electrode of the active element is exposed by etching the opposite main surface of the semiconductor substrate attached to the support plate through the via hole opening mask and the heat dissipation hole opening mask. Forming a hole and the heat dissipation hole that does not penetrate the semiconductor substrate at the same time, and the semiconductor substrate in a state of being attached to the support plate. A step of forming a backside metal layer on the opposite main surface, a step of attaching a sheet for expanding a chip to the opposite main surface of the semiconductor substrate in a state of being attached to the support plate, and the semiconductor substrate on the support plate. And a step of dicing the semiconductor substrate while being attached to the sheet.