JPH0228335A - Manufacture of monolithic integrated circuit element - Google Patents
Manufacture of monolithic integrated circuit elementInfo
- Publication number
- JPH0228335A JPH0228335A JP63179412A JP17941288A JPH0228335A JP H0228335 A JPH0228335 A JP H0228335A JP 63179412 A JP63179412 A JP 63179412A JP 17941288 A JP17941288 A JP 17941288A JP H0228335 A JPH0228335 A JP H0228335A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hole
- monolithic integrated
- etching
- monolithic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 6
- 238000005219 brazing Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 abstract 2
- 239000000470 constituent Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 238000007747 plating Methods 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 238000001465 metallisation Methods 0.000 description 8
- 239000010453 quartz Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、モノリシック集積回路素子の製造方法に関し
、特に素子接地を裏面パイ７ホールと側面メタライズの
両方で同時に行い得ることによって、回路素子配置の自
由度を上げ、チップの小型化をはかった集積回路素子の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a monolithic integrated circuit device, and in particular, the present invention relates to a method of manufacturing a monolithic integrated circuit device. This invention relates to a method for manufacturing integrated circuit devices that increases the degree of freedom in manufacturing and reduces the size of chips.
近来、半導体トランジスタについては、超高周波帯での
性能向上と共に、整合回路や保護回路、又電源バイアス
回路をも半導体基板上に一体構成した所謂、モノリシッ
ク集積回路素子が各所で検討されている。とりわけ、ガ
リウム砒素は半絶縁性基板が容易に得られることや高速
性に適していることから、ＩＧＨｚ以上のより超高周波
帯域で増幅器５発振器１位相器、あるいは高速分局器等
のモノリシヅク素子が検討され、既に、一部は商品化さ
れている。一方、Ｘ帯以上のモノリシック集積回路素子
においては、ソース電極の接地にポンディング線を用い
たのでは、回路整合に影響を及ぼす為に基板に貫通孔を
設けて接地を行う、所謂、バイアホール接地法やチップ
側面に設けた接地金属を通して、接地を行う、側面メタ
ライズ法が知られ、モノリシック素子の高周波化・高性
能化に必要不可欠な技術となっている。In recent years, with regard to semiconductor transistors, in addition to improving performance in ultra-high frequency bands, so-called monolithic integrated circuit elements in which matching circuits, protection circuits, and power supply bias circuits are also integrated on a semiconductor substrate are being studied in various places. In particular, gallium arsenide is suitable for high-speed operation and it is easy to obtain semi-insulating substrates, so monolithic elements such as amplifiers, 5 oscillators, 1 phase shifter, or high-speed splitters are being considered for ultra-high frequency bands above IGHz. Some of them have already been commercialized. On the other hand, in monolithic integrated circuit devices of X band and above, using a bonding wire to ground the source electrode is not possible, but in order to affect circuit matching, grounding is done by providing a through hole in the substrate, so-called via hole. The side surface metallization method, which performs grounding through grounding metal provided on the side of the chip, is known and is an essential technology for increasing the frequency and performance of monolithic devices.
従来、この様なバイアホールを通して、ソース電極を接
地せしめるモノリシック集積回路素子の製造方法として
は、第３図（ａ）〜（ｄ）に示す様に半絶縁性基板４１
上に能動素子４２および整合回路素子や電源バイアス回
路素子からなる受動素子４３を設ける（第３図（ａ））
。次に、この基板４１を接着剤４４を介して支持板４５
に貼り付は固定し、薄化した後、バイアホールエツチン
グマスク４６を用いて、集積回路素子の接地電極に到達
する貫通孔、すなわち、バイアホール４７を設ける（第
３図（ｂ））。続いて、メツキ給電層４８を用いて接地
用金属のメツキ層４９を選択的に設けた後、エッチカッ
トマスク５０を用いて、エツチングにより素子分離の為
のエッチカット領域５２を形成する（第３図（Ｃ））。Conventionally, as a method for manufacturing a monolithic integrated circuit device in which the source electrode is grounded through such a via hole, a semi-insulating substrate 41 is used as shown in FIGS. 3(a) to 3(d).
An active element 42 and a passive element 43 consisting of a matching circuit element and a power supply bias circuit element are provided above (FIG. 3(a)).
. Next, this substrate 41 is attached to a support plate 45 via an adhesive 44.
After fixing and thinning, a via hole etching mask 46 is used to provide a through hole, that is, a via hole 47 that reaches the ground electrode of the integrated circuit element (FIG. 3(b)). Subsequently, a plating layer 49 of grounding metal is selectively provided using the plating power supply layer 48, and then an etch cut region 52 for element isolation is formed by etching using the etch cut mask 50 (the third Figure (C)).
最後に接着剤４４を溶解することによってモノリシック
集積回路素子チップが得られた（第３図（ｄ））。Finally, by dissolving the adhesive 44, a monolithic integrated circuit element chip was obtained (FIG. 3(d)).
又、従来の別の側面メタライズを通してソース電極を接
地せしめるモノリシック集積回路素子の製造方法として
は、第４図（ａ）〜（ｃ）に示す様に、半絶縁基板６１
上に能動素子６２．受動素子６３を設ける（第４図（ａ
乃。続いて、裏面研磨により薄化した後、裏面電極６４
を設け、表面側にメツキカバー６５を受けた後に、スク
ライブをし素子分離する（第４図（ｂ））。次に、電界
メツキによって、チップ毎に接地用側面金属６６を設け
、メツキカバー６５を除去することによってモノリシッ
ク集積回路素子チップが得られていた（第４図（Ｃ））
。Further, as a conventional method for manufacturing a monolithic integrated circuit device in which the source electrode is grounded through another side metallization, as shown in FIGS. 4(a) to 4(c), a semi-insulating substrate 61
Active element 62. A passive element 63 is provided (see FIG. 4(a)
No. Subsequently, after being thinned by back polishing, the back electrode 64 is
After a plating cover 65 is provided on the front side, scribing is performed to separate the elements (FIG. 4(b)). Next, a grounding side metal 66 was provided for each chip by electric field plating, and the plating cover 65 was removed to obtain a monolithic integrated circuit element chip (Fig. 4(C)).
.
上述した従来のモノリシック集積回路素子の製造方法は
、例えばマイクロ波電力用モノリシック増幅器の様に多
段構成の場合には、接地を取るために回路素子の配置に
制限が加えられ、従って、モノリシック集積化の大きな
利点であるべきチップの小型化が充分になされず、大量
生産、低価格化がはかれないという問題があった。In the conventional method for manufacturing monolithic integrated circuit elements described above, for example, in the case of a multi-stage configuration such as a monolithic amplifier for microwave power, restrictions are placed on the arrangement of circuit elements in order to ensure grounding. The problem was that the chips were not sufficiently miniaturized, which should be a major advantage, and mass production and price reductions were not possible.
具体的には、バイアホール接地方式では距離の関係から
、チップの周辺付近に接地電極が配置される必要がある
。又、第３図（ｄ）に示す断面形状からもわかる様に従
来のパイ７ホールによる製造方法の場合にはマウント−
ポンディング時のハンドリングの際の接触部が少なく、
チップ欠けが生じて不良となること、更に、マウント時
にパイ７ホール内部にソルダー材が入り込み、表面側受
は電極を押し上げる為に生ずる電極フクレが発生し、大
きな問題となっていた。Specifically, in the via-hole grounding method, the ground electrode needs to be placed near the periphery of the chip due to distance. In addition, as can be seen from the cross-sectional shape shown in Figure 3(d), in the case of the conventional pie-7 hole manufacturing method, the mount
There are fewer contact points during handling during pounding,
This was a major problem, as the chips would chip and become defective.Furthermore, the solder material would get into the pie hole 7 during mounting, and the electrodes would bulge as the electrodes were pushed up on the front side supports.
一方、側面メタライズによる場合には、チップ１個ずつ
のメツキによってなされていたために、工数の点で問題
であり、更に半絶縁性基板面に直接メツキしているため
に、高温保管によるメツキ剥がれが生じるという信頼性
の低下が問題となっていた。On the other hand, in the case of side surface metallization, this is done by plating one chip at a time, which poses a problem in terms of man-hours.Furthermore, since it is plated directly onto the semi-insulating substrate surface, the plating peels off due to high temperature storage. The problem was a decrease in reliability due to this.
本発明のモノリシック集積回路素子の製造方法は、基板
表面側の貫通孔形成領域および素子分離領域に対し、エ
ツチング溝を設ける工程と、エツチング溝に到達する貫
通孔を設けて表面側接地電極と電気的な導通をはかる工
程を含むという特徴と、貫通孔の内壁のみに素子マウン
トろう材となじまない性質を有するＴｉ、Ａ４あるいは
これらの酸化膜を設ける工程を含んでいる。The method for manufacturing a monolithic integrated circuit device of the present invention includes the steps of providing an etching groove in a through-hole formation region and an element isolation region on the surface side of a substrate, and forming a through-hole that reaches the etching groove to connect a surface-side ground electrode and an electrical connection. This method includes a step of establishing electrical conductivity, and a step of providing Ti, A4, or an oxide film of these materials, which have properties that are not compatible with the element mounting brazing material, only on the inner wall of the through hole.
本発明によれば基板表面側の貫通孔領域および素子分離
領域に対してエツチング溝を設け、バイアホール形成と
素子分離を同時に行ってバイアホールによる接地と側面
メタライズによる接地を同一チップ内で行い得るととも
に、チップ欠けのない断面形状を呈している。According to the present invention, etching grooves are provided in the through-hole region and the element isolation region on the surface side of the substrate, and via hole formation and element isolation can be performed simultaneously, and grounding by the via hole and grounding by the side metallization can be performed within the same chip. At the same time, it exhibits a cross-sectional shape with no chipping.
次に、本発明の典型的な一実施例であるガリウム砒素（
以下、ＧａＡｓと称す）モノリシック集積回路素子の場
合について、図面を参照して説明する。Next, gallium arsenide (
The case of a monolithic integrated circuit element (hereinafter referred to as GaAs) will be explained with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の一実施例の縦断面図で
ある。まず、半絶縁性ＧａＡｓ基板１１にパイ７ホール
領域エツチング溝１３および素子分離領域エツチング溝
１４を第１のフォトレジストマスク１２を用いて、ウェ
ットエツチングにより２０μｍの深さ選択的にエツチン
グ形成する（第１図（ａ））。次に、イオン注入により
、ＦＥＴの能動層１５、コンタクト層１６を形成した後
、ＦＥＴゲート電極１７．オーミック電極等を含む一層
配線１８、更に、配線メタルとなる二層配線１９を形成
して表面側のモノリシック素子を形成する（第１図（ｂ
））。この時、素子分離領域１４には側面メタライズの
受は電極を残しておくようにする。FIGS. 1(a) to 1(f) are longitudinal sectional views of an embodiment of the present invention. First, a pie-7 hole region etching groove 13 and an element isolation region etching groove 14 are selectively etched to a depth of 20 μm by wet etching using the first photoresist mask 12 on a semi-insulating GaAs substrate 11 (first etching process). Figure 1(a)). Next, after forming the FET active layer 15 and contact layer 16 by ion implantation, the FET gate electrode 17. A monolithic element on the front side is formed by forming a single-layer wiring 18 including ohmic electrodes, etc., and a second-layer wiring 19 that becomes a wiring metal (see Fig. 1(b).
)). At this time, electrodes are left in the element isolation region 14 to support the side metallization.
続いて、表面工程完了後のウェノ・−をワックス２５を
介して石英板２４に固定し、裏面側から４５０μｍから
１４０μｍ厚さまで研磨によって薄化した後、フォトレ
ジストマスク２１を用いて、ウェットエツチングによっ
て表面側の接地電極に到達するようにバイアホール用貫
通孔２２および素子分離貫通孔２３を選択的に形成する
（第１図（Ｃ））。次に、メツキ給電金属２６を全面に
被着した後、素子分離領域２３以外にＡｕメツキ層２７
を選択的に設ける（第１図（ｄ））。続いてＡｕメ。Subsequently, after the surface process has been completed, the wafer is fixed to a quartz plate 24 via wax 25, and after being thinned by polishing from the back side to a thickness of 450 μm to 140 μm, using a photoresist mask 21, wet etching is performed. A via hole through hole 22 and an element isolation through hole 23 are selectively formed so as to reach the ground electrode on the front side (FIG. 1(C)). Next, after the plating power supply metal 26 is deposited on the entire surface, the Au plating layer 27 is placed on the area other than the element isolation region 23.
is selectively provided (FIG. 1(d)). Next is Au Me.
キ層２７をマスクにメツキ給電金属２６をエツチング除
去した後、ワックス２５を除去し、石英板２４より剥離
することによってバイアホールおよび側面メタライズに
より接地したＧａＡｓモノリシック集積回路素子チップ
が得ちれる（第１図（ｅ））。一方、第１図（ｄ）の工
程後バイアホール内壁のみに選択的にＴｉ ２８を設け
ることによって、より信頼性の面で優れたＧａＡｓモノ
リシック集積回路素子チップが得られる。After removing the plating power supply metal 26 by etching using the transparent layer 27 as a mask, removing the wax 25 and peeling it off from the quartz plate 24, a GaAs monolithic integrated circuit element chip grounded through via holes and side metallization is obtained. Figure 1 (e)). On the other hand, by selectively providing Ti 28 only on the inner wall of the via hole after the step shown in FIG. 1(d), a GaAs monolithic integrated circuit element chip with better reliability can be obtained.
次に、第２図を用いて本発明の他の実施例１を説明する
。Next, another embodiment 1 of the present invention will be described using FIG. 2.
まず、半絶縁性Ｇ ａ Ａ ｓ基板１１に、バイアホー
ル領域エツチング溝３２および素子分離領域エツチング
溝３３を第１のエツチングマスク３１を用いてＣＣＩ２
２ Ｆ ！ ＋ Ｈｅガスを用いた反応性イオンエツチ
ングにより２０μｍの深さ、選択的にエツチング形成す
る（第２図（ａ））。次に、ＦＥＴからなる能動素子３
４．インダクタ、キャパシタおよび抵抗等より構成され
る受動素子３５を形成して、表面側のモノリシック素子
を形成する（第２図（ｂ乃。この時、素子分離領域３３
には側面メタライズの受は電極を残しておくようにする
。続いて、表面工程完了後のウェハーをワックス２５を
介して、石英板２４に固定し、裏面側から４５０μｍか
ら１４０μｍ厚さまで研磨によって薄化した後、第２エ
ツチングマスク２１を用いて、ｃｃｕ２Ｆ’２＋Ｈｅガ
スを用いた反応性イオンエツチングによって表面側の接
地電極に到達するようにバイアホール貫通孔３６素子分
離貫通孔３７を選択的に形成する（第２図（Ｃ））。次
に、メツキ給電金属３８を全面に被着した後、素子分離
領域３３以外にＡｕメツキ層３９を選択的に設ける（第
２図（ｄ））。続いて、Ａｕメツキ層３９をマスクにメ
ツキ給電金属３８をエツチング除去した後、ワックス２
５を除去し、石英板２４より剥離することによって、バ
イアホールおよび側面メタライズにより接地したＧ ａ
Ａ ｓモノリシック集積回路素子チップが得られる（
第２図（ｅ））。一方、第１図（ｄ）の工程後、バイア
ホール内壁のみに選択的にＴｉ４０を設けることによっ
て、より信頼性の点で優れたＧａＡｓモノリシック集積
回路素子チップが得られる。First, a via hole region etching groove 32 and an element isolation region etching groove 33 are etched on a semi-insulating GaAs substrate 11 using a first etching mask 31.
2 F! + selectively etched to a depth of 20 μm by reactive ion etching using He gas (FIG. 2(a)). Next, active element 3 consisting of FET
4. A passive element 35 composed of an inductor, a capacitor, a resistor, etc. is formed to form a monolithic element on the front side (Fig. 2 (b). At this time, the element isolation region 33
Make sure to leave the electrodes on the metallized sides. Subsequently, the wafer after the surface process has been completed is fixed to a quartz plate 24 via wax 25, and after being thinned by polishing from the back side to a thickness of 450 μm to 140 μm, using the second etching mask 21, ccu2F'2+He By reactive ion etching using gas, via holes 36 and element isolation through holes 37 are selectively formed so as to reach the ground electrode on the surface side (FIG. 2(C)). Next, after a plating power supply metal 38 is deposited on the entire surface, an Au plating layer 39 is selectively provided in areas other than the element isolation region 33 (FIG. 2(d)). Subsequently, after removing the plating power supply metal 38 by etching using the Au plating layer 39 as a mask, the wax 2
By removing 5 and peeling it off from the quartz plate 24, the G a grounded through the via hole and side metallization is removed.
A monolithic integrated circuit element chip is obtained (
Figure 2(e)). On the other hand, by selectively providing Ti 40 only on the inner wall of the via hole after the step shown in FIG. 1(d), a GaAs monolithic integrated circuit element chip with better reliability can be obtained.
この実施例ではパイ７ホールおよび素子分離のためのエ
ツチングを反応性イオンエツチングによっている為、マ
スク下のオーバーエツチングがほとんどなく、従ってパ
イ７ホール領域の縮小化がはかられ、チップの小型化が
なされる利点がある。In this example, reactive ion etching is used for the etching for the pi-7 hole and element isolation, so there is almost no over-etching under the mask, so the pi-7 hole area can be reduced, and the chip can be made smaller. There are benefits to be made.
以上説明したように本発明は、基板表面側の貫通孔領域
および素子分離領域にエツチング溝を設けて、裏面バイ
アホールと素子分離を同時に行い、バイアホール法と側
面メタライズ法でＩＣの接地をとることによってモノリ
シック素子配置の自由度を上げることができる効果があ
る。その結果、多段構成のモノリシックＩＣを小型で実
現することができ、又チップ断面形状も、エツチング溝
の形成によってマウントハンドリング時のチップ欠けが
生じにくい形になっており、組立歩留を向上できる効果
がある。又、バイアホール内壁のみにＴｉ等を設けるこ
とにおいて、マウント時のツルグーの這い上がりを抑制
することが出来、信頼性の向上がはかられるという効果
がある。As explained above, the present invention provides etching grooves in the through-hole region and element isolation region on the front side of the substrate, simultaneously performs backside via holes and element isolation, and grounds the IC using the via hole method and side surface metallization method. This has the effect of increasing the degree of freedom in monolithic element arrangement. As a result, it is possible to realize a compact monolithic IC with a multi-stage configuration, and the cross-sectional shape of the chip is shaped so that chipping is less likely to occur during mounting handling due to the formation of etched grooves, which has the effect of improving assembly yield. There is. Further, by providing Ti or the like only on the inner wall of the via hole, it is possible to suppress creeping up of dirt during mounting, and this has the effect of improving reliability.
第１図（ａ）〜（「）は本発明の一実施例によるモノリ
シック集積回路素子の製造方法を示す各工程の縦断面図
、第２図（ａ）〜（「）は本発明の他の実施例によるモ
ノリシック集積回路素子の製造方法を示す各工程の縦断
面図、第３図（ａ）〜（ｄ）は従来のモノリシック集積
回路素子の製造方法を示す各工程の縦断面図、第４図は
従来の別のモノリシック集積回路素子の製造方法を示す
各工程の縦断面図である。
１１・・・・・・半絶縁性ＧａＡｓ基板、１２・・・・
・・フォトレジストマスク（１）、１３． ３２・・・
・・・バイアホール領域エツチング溝、１４．３３・・
・・・・素子分離領域エツチング溝、１５・・・・・・
能動層、１６・・・・・・コンタクト層、１７・・・・
・・ゲート電極、１８・・・・・・−層配線、−１９・
・・・・・二層配線、２１・・・・・・フォトレジスト
マスク（２）、 ２２．３６・・・・・・バイアホー
ル用貫通孔、２３．３７・・・・・・素子分離貫通孔、
２４・・・・・・石英板、２５・・・・・・ワックス、
２８，３８．４８・・・・・・メツキ給電金属、２７，
３９．４９・・・・・・Ａｕメツキ層、２０・・・・・
・第２のエツチングマスク、２８．４０・・・・・・Ｔ
ｉ、４１．６１・・・・・・半絶縁性基板、４２．６２
・・・・・・能動素子、４３，６３・・・・・・受動素
子、４４・・・・・・接着剤、４５・・・・・・支持板
、４６・・・・・・バイアホールエツチングマスク、４
７・・・・・・バイアホール、５０・・・・・・エッチ
カットマスク、６４・・・・・・裏面電極、６５・・・
・・・メツキカバー ６６・・・・・・接地用側面金属
。
代理人 弁理士 内 原 晋
勇
１図
と乙ノ
２４石美林
ζ
ィ’ Ｚ／フ料シジス１マズク
刀幻分青１１且孔
（ｄ）
ｚｙＡｔ）；’ｙ〒λそ
（ｅ）
ＺとＬ
子２図
とｂノ
とＣノ
（ｄ）
３アＡｕメツ牛層
とＣノ
（ｊ−）
傷３０
（ｂ）
躬了図
（ｄ）FIGS. 1(a) to (") are longitudinal cross-sectional views of each process showing a method for manufacturing a monolithic integrated circuit device according to an embodiment of the present invention, and FIGS. FIGS. 3(a) to 3(d) are vertical cross-sectional views of each process showing a method for manufacturing a monolithic integrated circuit device according to an embodiment; FIGS. The figure is a vertical cross-sectional view of each process showing another conventional method for manufacturing a monolithic integrated circuit element. 11... Semi-insulating GaAs substrate, 12...
... Photoresist mask (1), 13. 32...
... Via hole area etching groove, 14.33...
...Element isolation region etching groove, 15...
Active layer, 16...Contact layer, 17...
・・Gate electrode, 18・・・layer wiring, −19・
...Two-layer wiring, 21...Photoresist mask (2), 22.36...Through hole for via hole, 23.37...Element isolation penetration hole,
24...Quartz plate, 25...Wax,
28,38.48...Plated power supply metal, 27,
39.49... Au plating layer, 20...
・Second etching mask, 28.40...T
i, 41.61...Semi-insulating substrate, 42.62
...active element, 43,63...passive element, 44...adhesive, 45...support plate, 46...via hole Etching mask, 4
7... Via hole, 50... Etch cut mask, 64... Back electrode, 65...
...Metsuki cover 66...Side metal for grounding. Agent Patent Attorney Shinyu Uchihara 1 Figure and Otono 24 Stone Mirin ζ Z Figure 2, b and C (d) 3A Au Metsugyu layer and C (j-) Wound 30 (b) Error figure (d)
Claims (1)
をとるモノリシック集積回路素子において、基板表面側
の貫通孔形成領域および素子分離領域に対しエッチング
溝を設ける工程と、表面パターン形成後、裏面より前記
エッチング溝に到達する貫通孔を設けて、表面側接地電
極と電気的に導通せしめる工程とを含むことを特徴とす
るモノリシック集積回路素子の製造方法。 ２、電気的導通をはかった前記貫通孔の内壁には素子マ
ウントろう材となじまない性質を有する材料を設けるこ
とを特徴とする請求項１記載のモノリシック集積回路素
子の製造方法。 ３、前記材料としてＴｉ、Ａｌおよびこれらの酸化膜で
あることを特徴とする請求項２記載のモノリシック集積
回路素子の製造方法。[Claims] 1. In a monolithic integrated circuit device in which the device is grounded through a through hole from the back side or through a side surface, a step of providing an etching groove in a through hole forming region and an element isolation region on the front side of the substrate, and a surface pattern A method for manufacturing a monolithic integrated circuit element, comprising the step of, after formation, providing a through hole that reaches the etching groove from the back surface to make it electrically conductive to the front surface ground electrode. 2. The method for manufacturing a monolithic integrated circuit device according to claim 1, characterized in that the inner wall of the through hole intended for electrical conduction is provided with a material that is incompatible with the device mounting brazing material. 3. The method of manufacturing a monolithic integrated circuit device according to claim 2, wherein the materials are Ti, Al, and oxide films thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63179412A JPH0777224B2 (en) | 1988-07-18 | 1988-07-18 | Method for manufacturing monolithic integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63179412A JPH0777224B2 (en) | 1988-07-18 | 1988-07-18 | Method for manufacturing monolithic integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0228335A true JPH0228335A (en) | 1990-01-30 |
| JPH0777224B2 JPH0777224B2 (en) | 1995-08-16 |
Family
ID=16065415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63179412A Expired - Lifetime JPH0777224B2 (en) | 1988-07-18 | 1988-07-18 | Method for manufacturing monolithic integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777224B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102200A (en) * | 1991-10-03 | 1993-04-23 | Mitsubishi Electric Corp | Semiconductor device |
| JP2005294472A (en) * | 2004-03-31 | 2005-10-20 | Nec Electronics Corp | Semiconductor device, semiconductor wafer, and their manufacturing methods |
| JP2007518253A (en) * | 2003-12-12 | 2007-07-05 | アトメル グルノーブル エス．ア． | Manufacturing method of electronic chip made of thinned silicon |
| JP2007273876A (en) * | 2006-03-31 | 2007-10-18 | Toyota Motor Corp | Semiconductor device and manufacturing method thereof |
| JP2011258833A (en) * | 2010-06-10 | 2011-12-22 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60161651A (en) * | 1984-02-02 | 1985-08-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS62122279A (en) * | 1985-11-22 | 1987-06-03 | Toshiba Corp | Manufacture of field effect transistor |
| JPS62128179A (en) * | 1985-11-29 | 1987-06-10 | Nec Corp | Semiconductor device |
-
1988
- 1988-07-18 JP JP63179412A patent/JPH0777224B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60161651A (en) * | 1984-02-02 | 1985-08-23 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS62122279A (en) * | 1985-11-22 | 1987-06-03 | Toshiba Corp | Manufacture of field effect transistor |
| JPS62128179A (en) * | 1985-11-29 | 1987-06-10 | Nec Corp | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102200A (en) * | 1991-10-03 | 1993-04-23 | Mitsubishi Electric Corp | Semiconductor device |
| JP2007518253A (en) * | 2003-12-12 | 2007-07-05 | アトメル グルノーブル エス．ア． | Manufacturing method of electronic chip made of thinned silicon |
| JP4863214B2 (en) * | 2003-12-12 | 2012-01-25 | ウードゥヴェ セミコンダクターズ | Manufacturing method of electronic chip made of thinned silicon |
| JP2005294472A (en) * | 2004-03-31 | 2005-10-20 | Nec Electronics Corp | Semiconductor device, semiconductor wafer, and their manufacturing methods |
| JP4703127B2 (en) * | 2004-03-31 | 2011-06-15 | ルネサスエレクトロニクス株式会社 | Semiconductor wafer, semiconductor chip and manufacturing method thereof |
| JP2007273876A (en) * | 2006-03-31 | 2007-10-18 | Toyota Motor Corp | Semiconductor device and manufacturing method thereof |
| JP2011258833A (en) * | 2010-06-10 | 2011-12-22 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0777224B2 (en) | 1995-08-16 |
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