JPH0723341A - Signal synchronizing device - Google Patents

Abstract

PURPOSE:To obtain a signal synchronizing device having simple and inexpensive constitution and high phase adjusting and synchronism control accuracy and capable of being constituted even when the device is separated from a device mechanism. CONSTITUTION:In the case of synchronizing a picture signal with an audio signal, the audio signal is temporarily stored in a buffer memory (RAM buffer) 33 and a memory access circuit 33 adjusts data reading timing by addressing the buffer 33 in accordance with the result of synchronism judgement based upon the code comparison of a synchronism judging circuit 31 to control a delay value. Consequently synchronism between the video signal and the audio signal can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synchronizing device, and more particularly to recording video and audio or first audio and second audio separately and synchronizing them with video or one audio as a reference. The present invention relates to a signal synchronizer used in a business system that outputs a sound by outputting a sound (for example, a program editing system that combines VTR and DAT used in a broadcasting station).

[0002]

2. Description of the Related Art For example, in editing a Japanese dubbed version of a foreign movie, the video and the dubbing audio are synchronized (that is, a synchronized playback output is obtained from two recorders recording the video and the audio, and the It is necessary to do the work (while reproducing the image and sound with the speaker).

In such a case, a video player (VTR, etc.)
Is used as a master machine, an audio player such as DAT (digital audio tape) is used as a slave machine, and the slave machine is speed-controlled on the basis of the time code recorded in the master machine to perform phase adjustment and synchronization.

A time code is a frame which is a unit of one frame of a video signal (in the case of interlaced display, one picture composed of an even field and an odd field, and 30 frames are formed per second). It is a unique identifier added to each of the above to distinguish each.

In particular, in the broadcasting industry, each picture is often distinguished by a time (time) such as "hours, minutes, seconds".
A set of "1" and "0" representing "minutes and seconds" is recorded as a time code on a dedicated track of a video / audio tape, or is superimposed on a vertical blanking period of a video signal. , The time code is also reproduced at the same time when the video / audio is reproduced and used as a synchronizing signal.

FIG. 6 is a diagram showing the configuration of a conventional example of a system for reproducing video and audio in synchronization. In this conventional example,
The video is played back by the VTR10, which is the master unit.
It is displayed on the display 20. Also, the sound is reproduced by the DAT 120 that is the slave unit, and the speaker 4
When it is 0, it is output as a sound.

Synchronous control of the reproduction signals of the VTR 10 and the DAT 120 is performed by the time code (various types are supplied from the VTR 10 to the DAT 120, but in this example,
A total of 8 recorded in the longitudinal direction of the tape, called LTC
It is assumed that a 0-bit code is used).

That is, the DAT 120 is provided with an operation clock frequency changing mechanism 130 (enclosed by a thick dotted line in the figure), and by changing the frequency of the operation clock, the tape drive of the drum control circuit 139 is performed. The speed and the audio sample reference clock of the digital signal processing reproduction system 143 are changed to adjust the audio reproduction speed, and the audio output from the speaker 40 is displayed on the display 20.
Synchronize with the video playback of.

The operation clock frequency changing mechanism 130 includes an oscillator circuit 132 using a crystal oscillator 131 and a master clock (M-CL) output from the oscillator circuit 132.
The frequency dividing circuit 13 that divides K) by n / m (n and m are arbitrary natural numbers) to generate a reference word clock (W-CLK).
3, and a PLL circuit 134 that supplies a clock obtained by multiplying the divided output by L to the drum control circuit 139,
A PLL circuit 151 that supplies a clock obtained by multiplying the divided output by K to the digital signal processing and reproducing system 143, and a VTR.
The time code reader 135 for decoding the time code supplied from the digital signal processing and reproducing system 143 and the time code reader 137 for decoding the time code separated from the sub code data through the sub code separation circuit 136.
And the time code are compared to obtain an offset, and in order to eliminate the offset and realize phase adjustment and synchronization, n /
A comparator circuit 138 for giving a control signal of a frequency division ratio to the m frequency division circuit 138, and a D / A for converting audio data into an analog signal.
And a converter 153.

In the DAT 120, the tape on which voice is recorded is sequentially wound by the drum 140 and the capstan 141. Further, the head 142 converts a magnetic recording signal into an electric signal to read voice information.

[0011]

In the above-mentioned conventional example, since the reproduction output of the slave unit is changed by changing the frequency of the operation clock to follow the reproduction output of the master unit, the slave unit is stable and follows. It is necessary to have a variable speed playback function with good performance.

In order to realize the function, a complicated variable speed drive servo mechanism and signal processing clock control (having a closed loop for negative feedback control as shown in FIG. 6) are provided. There is a need.

In this case, since the drive servo mechanism cannot be separated from the mechanism of the slave machine, the synchronization mechanism is inevitably provided inside the slave machine. Therefore, it is possible to synchronize with the master machine. It will be limited to expensive equipment with variable speed capability. This leads to high costs for the entire playback system, and
Since the synchronization function cannot be constructed as an independent external optional device, the flexibility for constructing the system will be lost.

Further, since the variable speed reproducing mechanism uses the oscillation clock of the crystal oscillator through the frequency dividing circuit having a variable division ratio, it does not have such a variable speed function and directly outputs the oscillation output of the crystal oscillator. The stability is inferior to the fixed-speed device used for the above due to the fluctuation of the frequency dividing circuit.

Therefore, when the synchronization with the master machine is not required (that is, when the slave machine is used independently), a mechanism for fixed speed operation is also provided and it is not necessary to switch and use it. In some cases it may not happen.

As described above, the variable speed mechanism in the slave machine is indispensable for the phasing and synchronization with the master machine. However, the variable speed mechanism causes the device to be complicated and the cost to increase. However, when the variable speed function is not necessary, it is one of the causes of lowering the stability.

The present invention has been made on the basis of the above consideration, and its object is to have a simple and inexpensive structure, and can be configured separately from the mechanism of the device.
Another object is to realize a synchronizer with high precision in phase adjustment and synchronization control.

[0018]

The constitution of a typical example of the present invention is as follows. That is, the speed control directly connected to the device mechanism by the variable speed drive mechanism is not used, but a buffer memory (hereinafter, also referred to as a RAM buffer) is used to adjust the signal delay amount, so that only purely electric signal control is performed. This realizes phasing and synchronization with the master machine.

That is, a RAM capable of temporarily storing the reproduction data by the slave device is provided, and the reproduction data is first temporarily stored at a predetermined address. Then, the time code reproduced by the slave machine itself is compared with the reference time code input from the reference master machine to obtain an offset amount corresponding to the time difference.

Next, the RAM buffer is addressed so as to give a time delay corresponding to this offset amount. As a result, the reproduction data of the slave machine is synchronized with the reproduction data of the master machine.

[0021]

For example, the maximum delay amount of the RAM buffer is set to 5 seconds. When the data delay control amount is set to ± 2.5 seconds, the reproduction data of the slave unit is 2.
Output 5 seconds early and write to RAM buffer.

Considering that the time of time code comparison, offset calculation, or address calculation can be ignored, these calculations end at the same time as the timing of writing the reproduction data (that is, slave data) of the slave unit to the RAM buffer. Will be done.

As shown in FIG. 2A, if the master data and the slave data are in sync as a result of the comparison of the time codes, the slave data is delayed by 2.5 seconds and output from the RAM buffer 33. Let Since the master data is also output at the time of this output, synchronization is achieved.

If the slave data is earlier by 1 second as shown in FIG. 2B, the delay amount in the RAM buffer 33 is set to 3.5 seconds. As a result, 1 second (3.5 seconds-2.
Only 5 seconds = 1 second), the slave data is output later than the master data, which eliminates the offset and realizes the synchronization relationship.

If the slave data is delayed by 1 second as shown in FIG. 2C, the delay amount in the RAM buffer 33 is set to 1.5 seconds. With this, 1 second (2.5
The slave data is output earlier than the master data only for 1 second (-1.5 seconds) = 1 second, which eliminates the offset and realizes the synchronization relationship.

[0026]

Embodiments of the present invention will now be described with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a configuration of an embodiment of a signal synchronizer (hereinafter, simply referred to as synchronizer) of the present invention.

The synchronizing device 30 of this embodiment has a pitch control function (that is, the above-mentioned reproduction speed changing function).
It is formed as an independent optional device that is used by being added to the DAT 11 that does not have the.

The overall configuration of the system of FIG. 1 is the same as that of the conventional example of FIG. 6, and is a system for outputting the reproduced image of the VTR 10 and the reproduced sound of the DAT 11 in synchronization with each other. DAT
11 has only a structure for generating an operation clock by the fixed oscillation circuit 13 using the crystal oscillator 12 having a fixed frequency, and therefore does not have a variable speed function.

Therefore, in the present embodiment, the synchronizer 30 is connected to the latter stage of the DAT 11 to control the delay amount of the data output from the DAT 11 to realize the synchronization with the image data reproduced by the VTR 10. .

The synchronizer 30 has a synchronization judgment circuit 31 including a code comparison circuit 34 and an offset calculation circuit 35, a memory access circuit 32, and a RAM buffer 33.

A concrete example of the synchronization control using the synchronizer 30 is shown in, for example, FIGS. 2A to 2C, and its concrete operation is as described in the section of the operation. Next, specific configurations and operations of the memory access circuit 32 and the RAM buffer 33 will be described with reference to FIG.

The RAM buffer 33 has addresses (addresses) from "a" to "j", and next to the address "j" is a ring buffer which returns to the address "a" which is the first address. And
Read pointer (read pointer) P at any address
1 and a write pointer (write pointer) P2 can be set.

The slave data (data (A) in FIG. 3) output from the slave machine is written in the address pointed by the write pointer P2. The read pointer P1 is set to the address designated by the memory access circuit 32, and the data is read from the address pointed to by the read pointer P1. Then, the read pointer P1, which has been set once, then moves in the opposite direction to the clockwise direction at intervals of 0.5 seconds, for example.

The setting of the write pointer P2 may be performed by the memory access circuit 32, or the setting function of the write pointer P2 may be included in the input / output control function of the RAM buffer 33 itself.

Therefore, when the RAM buffer 33 gives a delay of 1.5 seconds as shown in FIG. 2C, the write pointer P2 is set to the address "a" as shown in FIG.
The read pointer P1 may be set to the address "d".

In this case, the slave data (audio data (a) output from the DAT 11) is greater than the master data (video data output from the VTR 10) by 2.
It is output 5 seconds early and written in address "a". Simultaneously with this writing, the synchronization determination circuit 31 performs the synchronization determination and the memory access circuit 32 performs the addressing, and the read pointer P1 is set. This read pointer P1
Reaches the address "a" 1.5 seconds later, at which point the data (a) is read. That is, in this case, the data (a) is delayed by 1.5 seconds.

(Embodiment 2) FIG. 4 shows a synchronizing device 30 according to a second embodiment (which is a more specific version of the contents of Embodiment 1).
It is a figure which shows the whole structure of the reproduction | regeneration system using. The essential contents are the same as in the first embodiment.

A control circuit 50 is provided in the VTR 10 which is a master machine, and mutually controls data output timing and the like while exchanging information with the control circuit 51 provided in the DAT 11 which is a slave machine.

The synchronizer 30 has a data / code separation circuit 71, code readers 70 and 72, a comparison circuit 73, an offset calculation circuit 74, an address calculation circuit 75, and a RAM buffer 33. The movement of the read pointer PI in the RAM buffer 33 is performed at intervals of t1. In addition, the audio output is two-channel speakers 40a, 40.
obtained by b.

As shown in the figure, the signal processing timing is roughly divided into three stages of timing. That is, the timing is the output timing of the audio data, is the RAM 33 of the audio data.
Writing to and writing, synchronization judgment such as code comparison, RAM3
The addressing timing of No. 3 is the timing at which synchronized data is output from the VTR 10 and the synchronizer 30.

(Embodiment 3) FIGS. 5 (a) to 5 (c) are views showing examples of the installation form of the synchronizing apparatus of the present invention.

FIG. 5A shows a digital audio player 8
0, and the basic configuration of the synchronizing device is the same as that of the device of FIG. The data from the RAM buffer 88 is converted into an analog audio signal by the D / A converter 89 and output.

FIG. 5B shows the digital recorder 100.
In this example, a digital interface 90 for receiving input data from the digital recorder 100 is provided in the input section.

FIG. 5C shows the analog recorder 110.
In this example, the input section is provided with an A / D converter 120 that converts an input analog signal from the analog recorder 110 into digital data.

[0045]

As described above, according to the present invention, the following effects can be obtained. (1) When synchronizing the output signal of the slave unit with the output signal of the master unit, the delay control method using the RAM buffer is used. Therefore, the timing of data read from the RAM buffer by synchronization judgment, offset calculation, and memory addressing Phase control and synchronization can be achieved only by control, which is an extremely orthodox digital circuit technology. Therefore, the complicated negative feedback control of varying the frequency of the operation clock in accordance with the phase difference with the signal of the master machine by using the phase negative feedback control system such as the PLL is not required. The configuration can be simplified and the cost can be reduced.

(2) Further, unlike the conventional method of performing phase control while continuously pulling the negative feedback loop and pulling it into the lock-in range, the present invention adopts the method using the RAM buffer, and therefore the control of turning the loop is performed. Is unnecessary, and the amount of time delay can be set freely, accurately and extremely fast by a purely electrical method.

(3) Further, since the above-mentioned conventional technique has an inseparable relationship with the mechanism of the entire device, it is impossible to configure the synchronizing device as an independent optional device. An option is also possible to use the purely electrical delay technique. In other words, the synchronization function part can be configured independently or separately from the playback device main body, and therefore, even if the existing playback device that does not have the tuning / phasing function part is used, the synchronization operation with the master device can be performed. It becomes possible to improve convenience and flexibility when constructing a system.

(4) Further, in the case of the present invention, the drive mechanism does not have to have a variable speed function (pitch control function), and the normal fixed speed reproduction function by crystal control can be used as it is. Therefore, stable and highly accurate operation can be guaranteed without concern that the stability of the circuit of the variable speed function portion may be deteriorated.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a signal synchronizer of the present invention.

2A to 2C are diagrams for explaining a specific operation when synchronizing the data of the slave unit with the data of the master unit in the embodiment of FIG.

FIG. 3 is a diagram for explaining the configuration and specific operation of a RAM buffer 33, a synchronization determination circuit 31, and a memory access circuit 32 in the embodiment of FIG.

FIG. 4 is a diagram showing an overall configuration of a reproducing system using a second embodiment of the present invention (which is a more specific version of the content of the embodiment of FIG. 1).

5 (a) to 5 (c) are diagrams each showing an example of an installation mode of the synchronization device of the present invention.

FIG. 6 is a diagram showing a configuration example of a conventional example.

[Explanation of symbols]

 10 VTR 11 DAT 14 Drum 15 Head 16 Data reproduction and data / code separation circuit 20 Display 30 Synchronizer 31 Synchronization determination circuit 32 Memory access circuit 33 RAM buffer 34 Time code comparison circuit 35 Offset calculation circuit 40 Speaker

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location 7734-5C H04N 5/91 C 7734-5CN

Claims (5)

[Claims] 1. A signal synchronizer for synchronizing a signal processed by a slave machine (that is, a slave signal) with a signal processed by a master machine (that is, a master signal), comprising: To each of them, a synchronization signal used for synchronizing with each other (that is, a master synchronization signal and a slave synchronization signal, respectively) is added for each predetermined signal unit required to be synchronized, Realize signal synchronization using this synchronization signal,
As a means for realizing it, a synchronization determination circuit that separates the master signal and the slave signal, compares the master synchronization signal and the slave synchronization signal, and obtains an offset between the corresponding master signal and the slave signal, and A buffer memory for temporarily storing slave signals; and a memory access circuit for addressing the buffer memory so as to give a delay necessary to eliminate the offset obtained by the synchronization determination circuit. A signal synchronizer characterized by. 2. The signal synchronizer according to claim 1, wherein the signal synchronizer is provided in the slave machine. 3. The signal synchronization device according to claim 1, wherein the signal synchronization device is formed as an independent device separate from the slave device. 4. The signal synchronizer according to claim 1, wherein the buffer memory and the memory access circuit have the following configurations, and the following timings are used as data processing timings. [Structure of Buffer Memory] The address of the memory is in a ring format, and when the address goes around, it returns to the original address again. A write pointer for designating an address to write data and a read pointer for designating an address to read data can be freely set independently. The data of the slave signal is written to the address pointed by the write pointer, and the data is read from the address designated by the read pointer. The read pointer is set to an address designated by being addressed by the memory access circuit, and
Once the read pointer is set, the read pointer automatically moves in a predetermined direction at predetermined time intervals and sequentially points at different addresses. [Configuration of Memory Access Circuit] When the offset is obtained by the synchronization determination circuit, the predetermined movement direction of the read pointer from the position (address) of the write pointer is moved by the number of times of movement of the read pointer corresponding to the offset time. Addressing is performed at a position (address) going back in the opposite direction, and the read pointer is set at that position (address). [Data Processing Timing] At the same timing when the data of the slave signal is written to the address of the memory buffer pointed by the write pointer, the synchronization determination by the synchronization determination circuit, the offset calculation, and the addressing of the buffer memory by the memory access circuit are performed. Be seen. 5. The master unit is a video device capable of recording / reproducing a video signal, and the slave unit is an audio device capable of recording / reproducing an audio signal. Both the master synchronization signal and the slave synchronization signal are video signals. 4. The signal synchronizer according to claim 2 or 3, wherein the time code is uniquely added in a unit of one frame.