JPH07235618A - Semiconductor package - Google Patents

Abstract

PURPOSE:To provide a low-priced semiconductor package which can be coped with the increase in number of terminals and also on which conventional technique can be used on a printed substrate. CONSTITUTION:A metal base substrate 25, having a patterned copper foil layer 14, is formed on a metal plate 12 through the intermediary of an insulating layer 13, a flange part 16 is formed on the circumference of an aperture part 15 by conducting bending and drawing operations on the above-mentioned metal base substrate 25, and a plurality of protruding parts 17 are provided on the flange part 16. One end of the copper foil layer 14, having a wiring pattern, is exposed to the protruding part 17, and the other end is formed into an inner lead part against a semiconductor integrated circuit element 11. When this semiconductor package 10 is surface-mounted on a printed substrate, the protruding part 17 and the pad on the substrate are corresponded with each other and they are connected by reflow soldering.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package for a semiconductor integrated circuit element, and more particularly to a multi-terminal in which a large number of outer lead parts electrically connected to the semiconductor integrated circuit element are led out from the bottom surface of the package. Regarding semiconductor packages.

[0002]

2. Description of the Related Art There are various types of semiconductor packages for integrated circuits, such as DIP (Dual In-line Package). As a semiconductor package for LSI having a large number of external terminals, QFP, which is one of flat packages, is used. (Quad Fl
at Package) and PGA (Pin Grid Arr) as shown in Fig. 7.
ay) 80 etc. In the QFP, a plurality of leads connected to the semiconductor integrated circuit element (IC chip) are led out to the outer circumference of the package (4 directions) as outer leads. On the other hand, in the PGA 80, the leads connected to the IC chip are led out as terminals (pins) 81 from the lower surface of the package. In QFP, 4 on the outer circumference of the package
Since the outer leads can only be taken out from the side, when increasing the number of pins, that is, the number of outer leads,
Although it is unavoidable to narrow the distance between the outer leads, that is, the pin pitch, in PGA, the entire lower surface of the package can be used as a lead-out space, so that the pin pitch can be increased without making the terminal pitch so narrow. You can With the large-scale integration of semiconductor devices and the increase in size of semiconductor devices, the number of outer leads will be 40
It is expected that the number will increase to about 0 to 1000, and in this case, it is considered that the conventional QFP is difficult to handle.

When a semiconductor integrated circuit device is packaged in a PGA, a ceramic package in which metal pin terminals are brazed on the lower surface and die pads and inner leads are formed on the upper surface by metallization is used. An IC chip is mounted on this ceramic package, and after electrical connection between the IC chip and the inner leads is completed by a bonding wire, a ceramic or metal lid is attached. In addition, by patterning a die pad and inner leads on a ceramic substrate or printed circuit board, then attaching terminals to the lower surface of these ceramic substrate or printed circuit board, mounting an IC chip, and finally molding the whole with resin. There is also a method of packaging in PGA.

Further, as a device which can solve the problems of the conventional QFP and can cope with the narrowing of the outer lead spacing, for example, a semiconductor package described in Japanese Patent Laid-Open No. 1-132147 or a special feature by the present inventors. There is an electronic circuit package described in Kaihei 4-6893. The package described in Japanese Patent Laid-Open No. 1-131247 has aluminum or copper as a base metal and a resin layer made of an epoxy resin having a thickness of several tens of μm is provided as an insulating layer, and then a copper foil is laminated, patterned, and pressed. The IC chip is mounted in the central part and the peripheral part is used as an outer lead. The package described in Japanese Patent Laid-Open No. 4-6893 is a soup dish shape obtained by bending or drawing a metal base substrate, and an IC chip is mounted on the bottom thereof when viewed from the opening side. The peripheral portion of the opening surface is used as an outer lead. In these packages, since the outer leads are formed on the metal substrate via the insulating layer, various problems associated with the deformation of the outer leads can be avoided, and the outer lead interval can be made smaller than that of the QFP. it can. However, in these packages, since the outer lead terminals are basically taken out from the outer periphery 4 direction of the package, there is a limit in increasing the number of outer leads.

After all, in order to realize a higher number of pins and a higher number of terminals, it is indispensable to lead out electrical connection parts such as lead terminals from the lower surface of the package like PGA. In the case of PGA, the package is attached to the printed circuit board by pin insertion type mounting, and it is necessary to insert the outer lead terminals into the through holes provided in the printed circuit board. However, in such pin insertion type mounting, it is difficult to reduce the mounting area during high-density mounting, as compared with surface mounting. Therefore, an outer lead structure suitable for surface mounting is further required. Also, in PGA, it is necessary to braze a large number of outer lead terminals, and the packaging cost is considerably higher than in QFP.

At present, in order to adapt to surface mounting, a short lead PGA having a shorter outer lead terminal, a BGA (Ball Grid Array) having no lead terminal, and the like have been developed. FIG. 8A is a bottom view showing the outline of the configuration of the BGA, and FIG. 8B is a schematic cross-sectional view showing the state in which the BGA is mounted on the printed board. In the BGA 90, ball-shaped solder bumps 91 are formed on the lower surface of the package instead of the PGA outer lead terminals. B on the printed circuit board 92
When the GA 90 is mounted, the solder bumps 91 are electrically connected to the pads on the printed board 92 by reflow heating. In BGA90, I
The C chip 93 is mounted on a ceramic or glass epoxy substrate 94 via a die pad 95,
The copper foil wiring 96 (inner lead) on the substrate 94 is connected by a bonding wire 97. Further, a through hole via 98 penetrating the substrate 94 is provided, and the copper foil wiring 96 and the solder bump 91 are electrically connected via the through hole via 98. Furthermore, I
C chip 93, copper foil wiring 96, bonding wire 97
Molding material 9 made of epoxy or the like for sealing
9 is provided on the upper surface of the substrate 94.

However, in the BGA, the solder bumps formed on the lower surface of the package are apt to be uneven in height,
In addition to the problem that a contact failure is likely to occur at the time of mounting on a printed circuit board, there is a problem that solder bumps need to be formed again when the package is removed after the surface mounting once.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to cope with an increase in the number of terminals, and it is possible to take out a plurality of electrical connection sites from the lower surface of a package without attaching outer lead pins like PGA, and to connect to a printed circuit board. An object of the present invention is to provide an inexpensive multi-terminal semiconductor package that can use conventional surface mounting technology.

[0009]

A multi-terminal semiconductor package according to the present invention is a metal base substrate in which a copper foil layer and a metal plate are laminated via an insulating layer, and the copper foil layer is subjected to circuit processing. In the multi-terminal semiconductor package for mounting a semiconductor element, which is configured by a three-dimensional printed board having a collar portion by bending or drawing the metal base substrate using Is provided with a plurality of protrusions, one end of the circuit-processed copper foil layer is exposed on the surface of the protrusion, and the electrical conductivity between the semiconductor element on which the circuit-processed copper foil layer is mounted and the protrusion. Used for dynamic connection.

[0010]

In the multi-terminal semiconductor package of the present invention, the protruding portion formed on the collar portion and having one end of the copper foil layer exposed is used as an electrical connection site between the multi-terminal semiconductor package and another printed wiring board or the like. It That is, this protrusion is used for the outer lead terminal in the PGA package and the BG.
This corresponds to the solder bump in the A package. In the multi-terminal semiconductor package of the present invention, it is not necessary to attach pin-shaped outer lead terminals as compared with the conventional PGA, and the protrusion can be formed by subjecting the metal base substrate to bending drawing or pressing. The package forming process can be performed at a low price, and the pin pitch can be narrowed as compared with brazing the outer lead terminals, so that the number of terminals and the number of pins can be further increased. Since the protrusion is integrated with the metal base substrate, compared to BGA,
It is possible to remove the semiconductor package that has been surface-mounted once and mount it again as it is.

In the semiconductor package of the present invention, the metal plate constituting the metal base substrate has a thickness of 0.05 to
A material having a thickness of about 2.0 mm is used, but preferably aluminum having a thickness of 0.1 to 1.0 mm, a copper alloy such as nickel silver or brass, copper, copper clad invar, stainless steel, iron, silicon steel, electrolysis. Oxidized aluminum or the like can be used.

Examples of the insulating layer used in the present invention include thermosetting resins such as epoxyphenol and bismaleimide, and thermoplastic resins such as polyamideimide, polysulfone, polyparabanic acid and polyphenylene sulfide, and thermoplastic polyimide. The thing obtained by heating and imidizing the polyamic-acid varnish which is a precursor can be used. Alternatively, a heat-resistant organic polymer film, for example, polyimide, polyamideimide, aramid, polyethersulfone, polyetheretherketone, or the like on both sides of each film, a polyamic acid varnish that is a precursor of a thermoplastic polyimide is applied and heated and imidized. What is obtained can also be used. In the case of a thermoplastic polyimide soluble in an organic solvent, a thermoplastic varnish is cast in the same manner as in the film forming method described above, or a film obtained by coating and drying, or an extruded film or sheet of a thermoplastic polyimide. Can also be used. Further, a polyimide acid varnish or a thermoplastic polyimide may be applied to the back surface of the metal base substrate and / or the copper foil layer to be used, dried and laminated.

It is also possible to use a combination of the above-mentioned insulating layer materials. Furthermore, for the purpose of improving heat dissipation,
An inorganic filler may be added to the insulating layer as long as the machinability such as bending is not impaired. Examples of these fillers include alumina, silica, silicon carbide, aluminum nitride, and boron nitride.

Of these insulating layers, the most preferable one in the present invention is a thermoplastic polyimide having an imide structure in its main chain and having a glass transition temperature (T _g ) of 16
0 ° C to 350 ° C, JIS (Japanese Industrial Standard)
-The elongation percentage at break measured by the method specified in C2318 is 30% or more. By defining the glass transition temperature as described above, both the adhesive strength between the metal plate and the copper foil layer and the thermal reliability during wire bonding become excellent. Further, when the elongation rate is 30% or more, the reliability during machining becomes excellent. In such a thermoplastic polyimide, of course, an inorganic filler can be mixed.

In the present invention, as the copper foil layer used for forming the conductor layer, a commercially available electrolytic copper foil, rolled copper foil or the like which is relatively inexpensive and easily available is used. In the present invention, the circuit-processed copper foil layer corresponds to the inner lead and the outer lead. As a method of processing the circuit of the copper foil layer, a known patterning (etching) method or the like used in a usual printed wiring board can be used.

The patterned copper foil layer surface is preferably subjected to a plating treatment such as Ni / Au plating or Ag plating in order to perform wire bonding described later. This plating process can be performed before bending each part, but it is better to perform after plating.
Excellent in reliability.

As a method for laminating the metal plate, the insulating layer and the copper foil layer on each other, there are a hot roll method, a hot press method and the like. Further, a build-up method of forming an insulating layer on a metal plate and then forming a copper foil layer as a conductor layer by a vapor deposition method or a plating method can also be used.

In the present invention, when the semiconductor integrated circuit element is directly mounted on the metal plate for improving heat dissipation, the insulating layer on the metal base substrate must be removed.
As a method of removing the insulating layer, in the case of the hot pressing method, the removed portion is punched, or is cut and removed by an NC router after the hot pressing, a wet or dry etching method, and a laser processing method.

When the insulating layer is made of polyimide, an alkaline solution etching is used as the wet etching. For example, an alcohol solution such as potassium hydroxide or sodium hydroxide can be used. If necessary, a hydrazine compound may be added thereto. May be added.

As the dry etching, there are a plasma ashing method using oxygen plasma, a reactive ion etching method and the like, and a fluorocarbon type gas such as CF ₄ may be mixed if necessary. As a laser processing method, there is a method using an excimer laser, a carbon dioxide gas laser, a YAG laser, or the like, and examples of the excimer laser include ArF-based and KrF-based lasers.

The drawing and bending mechanical processing in the present invention can be carried out by press processing using an ordinary die. In order to protect the circuit-processed copper foil layer during drawing, the surface of the mold may be coated with a resin, or a concave shape may be provided in the mold according to the wiring pattern shape of the copper foil layer. In deep drawing and bending with a small radius of curvature, processing such as application of heat or processing such as swelling the insulating layer with a solvent or the like may be performed.

The cross-sectional shape of the semiconductor package of the present invention can be appropriately selected, but it is, for example, a soup dish type and has a radius of curvature at its bent portion of 0.1 mm to 5.0 mm because of its superiority in processing.
It is desirable to carry out processing so as to be within the range. In the examples described below, it was set to 1.0 mm.

The shape of the plurality of protrusions formed on the collar portion is, for example, hemispherical, in consideration of processing advantages and reliability of electrical connection to the printed circuit board. Alternatively, this shape can be a cone, a pyramid such as a triangular pyramid, or a square pillar, such as a square pillar. Regardless of the shape, it is desirable that the apexes (top surfaces) of the protrusions are substantially in contact with the same plane. As a method of forming the protrusion provided on the collar portion, it is possible to perform drawing mechanical processing or press processing using an ordinary die. When drawing or bending a soup dish as a three-dimensional printed circuit board, it is possible to form the protrusions on the flange surface by pressing at the same time. It is also possible to form the protrusion by press working using. In order to improve the connection reliability and prevent damage to the insulating layer and the copper foil layer in the protrusion, it is desirable that the radius of curvature thereof be in the range of 0.1 to 2.0 mm. In the examples described later, the radius of curvature was 0.5 mm. Further, in order to prevent a short circuit with the metal plate side at the time of mounting on a printed circuit board, it is desirable that the protruding portion is formed at a distance of 0.05 mm or more from the outer peripheral edge of the flange portion. Further, in order to prevent short-circuiting between the protrusions and to pass a wiring pattern or the like between the protrusions, it is desirable that the individual protrusions be formed at a distance of 0.1 mm or more.

The semiconductor package and the semiconductor integrated circuit device of the present invention are bonded to each other by a thermocompression bonding method using gold-silicon eutectic as a die bonding method or a method using a conductive adhesive resin, solder plating, gold plating, silver plating. Etc. are used. For electrical connection between a semiconductor integrated circuit element and a circuit-processed copper foil layer that is a wiring pattern, a wire bonding method or a flip chip method using bump formation is used.

The number of semiconductor integrated circuit elements mounted on the multi-terminal semiconductor package of the present invention is not limited to one, and a plurality of elements can be mounted. When a plurality of elements are mounted, mutual wiring between the elements employs a method of using a copper foil layer or using a bonding wire together. The mounted semiconductor integrated circuit element is generally hermetically sealed. For the hermetic sealing, transfer molding or potting method using, for example, an epoxy resin can be used. If necessary, the sealing resin should have an inorganic filler (alumina, silica, aluminum nitride,
Silicon nitride, boron nitride, silicon carbide, etc.) are mixed.

When the semiconductor package of the present invention is surface-mounted on a printed circuit board, a usual solder cream printing method is used as the surface mounting method. As a solder cream,
Amorphous or spherical eutectic solder (Sn63%, Pb3
7%) or high temperature solder (Sn 5%, Pb 95%) or the like containing solder particles can be used. After printing the solder cream, the semiconductor package of the present invention is mounted on the printed circuit board by an automatic mounting machine, and soldering is performed using a reflow furnace. As the reflow furnace, it is desirable to use an infrared heating and air combination type, a nitrogen reflow type, and a vapor phase type.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

<< First Embodiment >> FIG. 1A is a top view of a semiconductor package of a first embodiment of the present invention, and FIGS. 1B and 1C are a side view and a top perspective view of the semiconductor package, respectively. Is. FIG. 2 is a sectional view taken along the line AA ′ of FIG.

The semiconductor package 10 mounts a semiconductor integrated circuit element (IC chip) 11. The semiconductor package 10 uses the metal base substrate 25 in which the copper foil layer 14 is laminated on the metal plate 12 via the insulating layer 13, and after forming a circuit pattern on the copper foil layer 14,
The metal base substrate 25 is bent or drawn to form a soup dish having the opening surface 15, and a plurality of protrusions 17 are drawn on the surface of the flange 16 formed on the periphery of the opening surface 15 by drawing. It is formed by providing. In this embodiment, the opening surface 15 is substantially square, and the flange portion 16 is formed in a square shape surrounding four sides of the square formed by the opening surface 15. And
The protrusions 17 are arranged in two rows on each side, and a total of 72 protrusions 17 are provided. Further, on the surface of the copper foil layer 14 on which the circuit pattern is formed, after bending and drawing, a nickel (Ni) layer (not shown) having a thickness of 3 to 5 μm is formed by an electroless plating method. On top of this nickel layer,
By electroless plating, the thickness of gold (A
u) layer (not shown) is formed.

The projection 17 has a hemispherical shape and projects in the direction opposite to the bottom surface of the soup dish (downward in FIGS. 1B and 2). The vertices of the protrusions 17 are substantially in contact with the same plane, and this plane corresponds to the printed circuit board on which the semiconductor package is mounted, as will be apparent from the description below. Each of the bent portions of the soup plate-shaped portion, that is, the bent portion 18 that surrounds the bottom surface and the bent portion 19 that is located at the boundary between the collar portion 16 and the opening surface 15 have a curvature radius (inner radius) of 1.0 mm. Has been processed into. The radius of curvature (outer radius) of the hemispherical protrusion 17 is 0.5 mm.

FIG. 3 is a view of the semiconductor package 10 viewed from the opening surface 15 side. The copper foil layer 14 is formed into a wiring pattern corresponding to each protruding portion 17 by circuit processing, and one end side of each wiring pattern reaches a protruding portion 17 and forms a circular portion having a shape along the outer periphery of the protruding portion 17. Has become. Therefore, the surface of the protrusion 17 is covered with the wiring pattern, so that the wiring pattern, that is, the copper foil layer 14 is exposed in the protrusion 17. The other end of each wiring pattern extends to the inner lead region near the semiconductor integrated circuit element 11.

The distance from the outer peripheral portion of the protruding portion 17 to the outer peripheral end of the collar portion 16, that is, x in FIG. 3 is 0.05 mm or more. This is to prevent short-circuiting between the protrusion 17 and the metal plate 12 due to the wraparound of the solder when the semiconductor package 10 is mounted on another printed circuit board or the like. Further, in order to pass a wiring pattern to another protrusion 17 between the adjacent protrusions 17, the distance between the outer peripheral portions of these adjacent protrusions 17, that is, y in FIG. 3, is 0.1 mm or more. Is set to.

A copper plate having a thickness of 0.2 mm is used as the metal plate 12, and a glass transition temperature of 160 ° C. is selected from thermoplastic polyimides manufactured by Mitsui Toatsu Chemicals, Inc. as the insulating layer 13.
A material having a temperature of ˜350 ° C. and an elongation rate specified by JIS-C2318 of 30% or more was selected and used. The thickness of the insulating layer 13 was 20 μm. A copper foil having a thickness of 18 μm was used as the copper foil layer 14, and the metal plate 12, the insulating layer 13 and the copper foil layer 14 were bonded and laminated to each other by a hot pressing method.

The semiconductor integrated circuit element 11 is mounted from the opening surface 15 side to the central portion of the semiconductor package 10, that is, the bottom surface of a soup plate. In this case, the semiconductor integrated circuit element 11 is bonded to a die pad (not shown) on the semiconductor package 10 by a gold-silicon eutectic method, a conductive adhesive, solder, gold, silver plating or the like. Further, as described above, the copper foil layer 14 is processed into a circuit as a wiring pattern, and this wiring pattern extends from the flange portion 16 to the vicinity of the semiconductor integrated circuit element 11, but a bonding area corresponding to the inner lead portion of the wiring pattern. The semiconductor integrated circuit element 11 and the semiconductor integrated circuit element 11 are electrically connected by a bonding wire 20.

Further, in order to hermetically seal the semiconductor integrated circuit element 11 and the bonding wire 20, except for the collar portion 16, an epoxy resin containing filler (alumina, silica, aluminum nitride, boron nitride, etc.) is formed by transfer molding. The resin 21 is filled. By filling the epoxy resin 21 into the semiconductor package 10, the mechanical strength of the semiconductor package 10 is also improved.

Next, surface mounting of this semiconductor package on a printed circuit board will be described with reference to FIG.

Semiconductor package 1 on printed circuit board 22
0 is mounted on the copper foil layer 1 exposed at the protrusion 17.
4 and a pad (not shown) on the printed circuit board 22 are joined by a solder fillet 23, that is, a normal solder cream printing method. First, prepare a printed circuit board having a pad formed at a position facing the protruding portion 17, print solder cream on the pad, mount the semiconductor package on the printed circuit board with an automatic mounting machine, and reflow with a final reflow oven. By heating, the surface mounting of the semiconductor package 10 is completed.

<Second Embodiment> In the first embodiment described above, a total of 72 protrusions 17 were provided in a two-row lattice, but the arrangement and number of protrusions in the multi-terminal semiconductor package of the present invention are arbitrary. Is. In the semiconductor package 30 shown in FIG. 5, the radius of curvature of the hemispherical protrusion 31 is reduced (for example, 0.25 mm), and the radius of curvature is reduced to 3 at the flange of each side surrounding the opening surface.
By arranging the protrusions 31 in rows or more or in a zigzag pattern, it is possible to provide more electrical connection parts within a limited area.

The shape of the protrusion is not limited to the hemispherical shape. As shown in FIGS. 6A to 6C, the insulating layer 13 is formed by drawing or pressing when forming the protrusions.
In addition, the copper foil layer 14 can have various shapes as long as it is not damaged and the connection reliability to the printed circuit board is maintained. In the structure shown in FIG. 6A, the protrusion 32 has a shape in which a hemisphere is elongated in the height direction.
In the structure shown in FIG. 6B, the protrusion 33 has a shape further elongated in the height direction and has a shape close to a conical shape. In the structure shown in FIG. 6C, the protrusion 34 has a prismatic (square) shape. In addition, it is also possible to use triangular pyramid-shaped protrusions.

[0040]

As described above, the present invention uses a metal base substrate having a copper foil layer circuit-processed via an insulating layer, and bends or draws the metal base substrate to form a collar portion. By providing a plurality of protrusions on the surface of the collar portion and forming an electrical connection site with another printed circuit board etc., it is possible to braze the outer lead terminal like in PGA and to use in BGA. There is an effect that a multi-terminal (multi-pin) semiconductor package can be manufactured at low cost without forming a solder bump.

Regarding the number of external connection terminals of the multi-terminal semiconductor package of the present invention, the entire area of the lower surface of the package can be used B
Although inferior to GA, the pitch of the protrusions can be made narrower than the pin pitch of PGA when compared to PGA, so the number of external connection terminals can be increased to about 1.5 to 2 times that of PGA. It is possible. In this case, the pitch between the protrusions does not have to be a narrow pitch of about 0.3 to 0.5 mm, which is a problem during surface mounting by QFP, and a pitch of about 0.8 to 1.0 mm is sufficient. The number of external connection terminals can be secured.

In the multi-terminal semiconductor package of the present invention, the protrusion provided on the flange is formed by the metal base substrate itself by mechanical processing using a die or the like.
The shape stability is better than that of the solder bump used for, and the unevenness of height can be reduced. Even when it is once surface-mounted on the printed circuit board and then removed for repair or the like, the surface-mounting can be performed again as it is.

Since the multi-terminal semiconductor package of the present invention can be applied with conventional techniques such as die bonding, wire bonding technique, or surface mounting technique on a printed circuit board, many packages for semiconductor integrated circuits can be applied. It greatly contributes to pinning.

[Brief description of drawings]

1A is a top view showing a semiconductor package of a first embodiment of the present invention, and FIGS. 1B and 1C are a side view and a top perspective view of the semiconductor package of FIG. 1A, respectively.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

FIG. 3 is a view of the semiconductor package of FIG. 1 (a) as seen from its opening surface side.

FIG. 4 is a cross-sectional view showing a state in which the semiconductor package of FIG. 1 (a) is mounted on a printed board.

FIG. 5 is a diagram showing an arrangement of protrusions in a semiconductor package according to a second embodiment of the present invention.

6 (a), (b), and (c) are cutaway perspective views showing the shapes of the protrusions, respectively.

FIG. 7 is a perspective view showing a configuration of a PGA which is an example of a conventional semiconductor package.

FIG. 8A is an example of a conventional semiconductor package B.
The bottom view showing the structure of GA, (b) is B on the printed circuit board
It is a schematic cross section which shows the mounting method of GA.

[Explanation of symbols]

 10,30 Semiconductor package 11 Semiconductor integrated circuit element 12 Metal plate 13 Insulating layer 14 Copper foil layer 15 Opening surface 16 Collar portion 17,31 to 34 Protrusion portion 18,19 Bending portion 20,97 Bonding wire 21 Epoxy resin 22,92 Print Substrate 23 Solder fillet 25 Metal base substrate 80 PGA 81 Terminal 90 BGA 91 Solder bump 93 IC chip 94 Substrate 95 Die pad 96 Copper foil wiring 98 Through hole via 99 Molding material

Front page continuation (72) Inventor Hoshino ▲ Tatsumi ▼ Mitsui Toatsu Chemical Co., Ltd. 1190 Kasama-cho, Sakae-ku, Yokohama-shi, Kanagawa

Claims (8)

[Claims] 1. A metal base substrate, in which a copper foil layer and a metal plate are laminated via an insulating layer, and the copper foil layer is subjected to circuit processing, and the metal base substrate is bent or drawn. In a multi-terminal semiconductor package for mounting a semiconductor element, which is configured by a three-dimensional printed board having a shape with a brim portion by performing, a plurality of protrusions are provided on the surface of the collar portion, and the circuit processing One end of the copper foil layer exposed on the surface of the protrusion,
A multi-terminal semiconductor package, which is used for electrical connection between a semiconductor element on which the circuit-processed copper foil layer is mounted and the protrusion. 2. The multi-terminal semiconductor package according to claim 1, wherein the protrusions are arranged so that the vertices of the protrusions are substantially in contact with the same plane. 3. The multi-terminal semiconductor package according to claim 1, wherein the protrusion has a hemispherical shape. 4. The semiconductor package according to claim 1, wherein the shape of the protrusion is a cone or a prism. 5. The semiconductor package according to claim 1, wherein the shape of the three-dimensional printed board is a soup dish shape, and the radius of curvature of the bent portion is 0.1 mm or more and 5 mm or less. 6. The radius of curvature near the apex of the protrusion is 0.
The semiconductor package according to claim 3, which is 1 mm or more and 2 mm or less. 7. The insulating layer is made of a thermoplastic polyimide having an elongation of 30% or more and a glass transition temperature of 160 ° C. or higher and 350 ° C. or lower, according to claim 1. The semiconductor package described. 8. The projecting portion has a distance of 0.
Separated by more than 05mm and each protrusion is 0.1mm
8. The method according to any one of claims 1 to 7, which are formed apart from each other.
The semiconductor package according to item.