JP3939707B2 - Resin-sealed semiconductor package and manufacturing method thereof - Google Patents

Description

The present invention relates to a stacked semiconductor package suitable for high-density mounting and a method for manufacturing the same.

  In order to reduce the size of electronic equipment, it is required to increase the mounting density of semiconductor chips in the electronic equipment.

  Here, the purpose is to increase the mounting density of semiconductor chips by providing external terminals on the front and back surfaces of a semiconductor package on which a semiconductor chip is mounted, and contacting each external terminal to stack a plurality of semiconductor packages vertically. In addition, there is a technique of a stacked semiconductor package (see, for example, Patent Document 1).

JP 2002-343899 (2nd page)

  However, even in the stacked semiconductor package using the technology described in Patent Document 1, there is still room for improvement in order to further increase the mounting density of the semiconductor chips in the electronic device.

  An object of the present invention is to increase the mounting density of semiconductor chips in an electronic device, and more specifically, to reduce the thickness of a stacked semiconductor package.

  FIG. 9 is a sagittal sectional view showing a stacked semiconductor package according to the prior art. The stacked semiconductor package according to this prior art includes a lower substrate 101 provided with a metal terminal 108 on one side and a solder bump 103 connected to the metal terminal 108 on the other side (the back side of the multilayer substrate). A multilayer substrate comprising a through-hole provided on one surface of the lower substrate 101 and an upper substrate 102 having metal terminals 107 on the surface opposite to the lower substrate 101 (the surface of the multilayer substrate). Furthermore, a semiconductor chip 104 is mounted in the through hole of the upper substrate 102, the semiconductor chip 104 and the metal terminal 107 or the metal terminal 108 are connected by a connection wire 106, and the connection wire 106 and the semiconductor are connected. The chip 104 is covered with a sealing resin 105.

  In the stacked semiconductor package according to this conventional technique, the electrical connection between the front and back of the multilayer substrate, that is, between the metal terminal 107 and the solder bump 103 is indirectly established. That is, by connecting the connection wires 106 from the semiconductor chip 104 to the metal terminals 108 on the lower substrate 101 and the metal terminals 107 on the upper substrate 102 via the semiconductor chip 104, electrical connection between the front and back of the multilayer substrate can be achieved. Has been taken. For this reason, the wire layout when the semiconductor chip is mounted is complicated.

  Further, in the stacked semiconductor package according to this conventional technique, since the connection wire 106 is extended from the semiconductor chip 104 toward the surface of the upper substrate 102, the swell of the connection wire 106 is increased. Further, the thickness of the sealing resin 105 sufficient to protect the semiconductor chip 104 and the depth of the through hole, that is, the thickness of the upper substrate are also increased.

In order to solve the above problems, a stacked semiconductor package according to the present invention in which a semiconductor chip is sealed with a resin includes an upper wiring substrate and a lower wiring substrate. Upper wiring board has a size of the through-hole in which the semiconductor chip is fitted, and has a metal lands on both sides, these both sides of the metal lands are electrically connected by through holes. The lower wiring board has metal lands on both sides, and the metal lands on both sides are electrically connected by through holes. The upper wiring board and the lower wiring board bonded, and two substrates are electrically connected via the bumps bonded Ri mating portion has been performed. A semiconductor chip is arranged in a recess derived from the through hole, which is generated by bonding the two substrates, and the semiconductor chip is electrically connected to an internal connection terminal that is a part of a metal land of the lower wiring substrate exposed in the recess. that has been. A resin sealing portion is formed in the recess so as to seal the semiconductor chip 4 with resin .
The thickness of the base material of the lower wiring board is preferably set to 100 μm or more and 150 μm or less.

If it is stacked semiconductor package of this configuration, the protrusion of the connecting wires to wire bonded to the semi-conductor chip is reduced, it is possible to thin the semiconductor package by setting the thickness of the upper wiring board. In addition, since the upper and lower wiring boards are electrically connected, the wire layout when mounting the semiconductor chip can be simplified.

  In the stacked semiconductor package according to the present invention, the upper surface of the resin sealing portion that covers the semiconductor chip and the connection wire with resin and the upper surface of the upper wiring board are present on the same plane. be able to.

  If the top surface of the resin-sealed part that seals the semiconductor chip and connection wires is provided so that it protrudes from the top surface of the upper wiring board, the stacking interval can be determined when multiple stacked semiconductor packages are stacked. It cannot be made narrower than the thickness of the resin-sealed portion. On the other hand, if the upper surface of the resin sealing portion is provided in a state of being retracted from the upper surface of the upper wiring substrate, the upper wiring substrate has a thickness that can be reduced to reduce the thickness of the semiconductor package. Become.

  Therefore, when the above-described configuration is such that the upper surface of the resin sealing portion and the upper surface of the upper wiring substrate are on the same plane, the individual semiconductor packages can be thinned while narrowing the stackable intervals of the semiconductor packages. Therefore, the mounting density of the semiconductor chip in the electronic device is further increased.

  In the stacked semiconductor package according to the second aspect of the present invention, the upper surface of the resin sealing portion that covers the semiconductor chip and the connection wire with the resin and the upper surface of the upper wiring substrate are coplanar. The distance between the upper surface of the resin sealing portion and the upper portion of the connection wire that is wire-bonded to the semiconductor chip is 30 μm or more and 50 μm or less.

  When the semiconductor chip and the connection wires are covered with resin, they can be protected from external impacts. Here, from the aspect of protection against external impact, it is preferable to set the thickness of the resin covering the object to be protected as thick as possible. However, unnecessarily thickening the resin cover makes the semiconductor package thinner. It goes against the purpose.

  Thus, the inventors have examined that the semiconductor chip and the connection wire can be sufficiently protected from external impact if the distance between the upper surface of the resin sealing portion and the upper portion of the connection wire is not less than 30 μm and not more than 50 μm. It was done. Therefore, with the above configuration, the semiconductor package can be thinned while sufficiently protecting the semiconductor chip and the connection wires from external impact.

  The stacked semiconductor package according to the second aspect of the present invention may further be configured such that the base material of the lower wiring substrate has a thickness of 100 μm or more and 150 μm or less.

  With this configuration, as described above, while using a thin lower wiring board, the amount of thermal deformation during package assembly can be suppressed to 20 μm or less, so that the stacked semiconductor package can be thinned and stacked. The package assembly property of the type semiconductor package can be improved.

In order to solve the above problems, in the method of manufacturing a stacked semiconductor package according to the present invention in which a semiconductor chip is sealed with a resin , first, the semiconductor chip has a through-hole that fits into the semiconductor chip. An upper wiring board having metal lands on both sides and electrically connecting the metal lands on both sides by through holes is prepared . A lower wiring board having metal lands on both surfaces and electrically connecting the metal lands on both surfaces by through holes is prepared . The upper wiring board and the lower wiring board are bonded together so that electrical connection is made between both boards via bumps. An internal connection terminal which is a part of a metal land of the lower wiring board in which the semiconductor chip is disposed in a concave portion derived from the through hole generated by bonding the two substrates, and the semiconductor chip is exposed in the concave portion Electrically connect to A resin sealing portion is formed in the recess so as to cover the semiconductor chip and the internal connection terminals.

With the manufacturing method having this configuration, the stacked semiconductor package according to the present invention can be provided. Further, with this configuration, as described above, the contents of the prepreg forming step can be simplified by forming the through hole of the upper wiring substrate after the prepreg is formed.

  The method for manufacturing a stacked semiconductor package may be configured such that the thickness of the base material of the lower wiring substrate is not less than 100 μm and not more than 150 μm.

  With this configuration, as described above, it is possible to provide a stacked semiconductor package in which the package assembly property is improved while reducing the thickness.

  The manufacturing method of the stacked semiconductor package may further include a configuration in which the connection wire is covered with a resin so that a distance from an upper portion of the connection wire wire-bonded to the semiconductor chip is 30 μm or more and 50 μm or less. it can.

  With this configuration, as described above, it is possible to provide a stacked semiconductor package in which the semiconductor chip and the connection wires are sufficiently protected from external impacts while being thinned.

  According to the present invention, the internal connection terminals are provided only on the upper surface portion of the lower wiring substrate corresponding to the bottom surface of the concave portion of the multilayer substrate, and the upper and lower wiring substrates are electrically connected, thereby wire bonding to the semiconductor chip. The electrical connection between the semiconductor chip and the external terminal can be achieved while reducing the rise of the connection wire.

  Thereby, the thickness of the upper wiring substrate and the resin sealing portion can be set thin, and the multilayer substrate and the semiconductor package can be thinned, so that the mounting density of the semiconductor chips in the electronic device is improved.

The best mode of the multilayer substrate for a stacked semiconductor package used in the present invention will be described below using the first embodiment as an example. The stacked semiconductor package according to the present invention will be described later using the second embodiment as an example.

[Embodiment 1]
As shown in the front view (a) and the rear view (b) of FIG. 1, the multilayer substrate 1 for the stacked semiconductor package according to the first embodiment has a rectangular plate shape and penetrates substantially at the center. An annular upper wiring board 8 provided with holes 14 and a lower wiring board 7 whose outer shape is the same as that of the upper wiring board 8 are provided.

  Further, in the first embodiment, metal lands 2 are provided on both surfaces of the upper wiring substrate 8 and both surfaces of the lower wiring substrate 7, as shown in FIG. The pair of metal lands 2 on both sides of each wiring board are electrically connected inside each board.

  The upper wiring board 8 and the lower wiring board 7 are electrically connected to each other by the bumps 9 and are bonded to each other through the prepreg 10. The prepreg 10 has a through hole having the same shape as the through hole 14.

  The upper surface portion of the lower wiring substrate 7 closes the lower opening of the through hole 14 of the upper wiring substrate 8, and the multilayer substrate recess 11 in the multilayer substrate 1 is formed by the through hole 14 and the upper surface portion of the lower wiring substrate 7. It is.

  The internal connection terminals 12 for wire bonding to the semiconductor chip are provided only on the upper surface portion of the lower wiring substrate 7, that is, the bottom surface of the multilayer substrate recess 11. Although not shown, a wiring pattern for connecting the internal connection terminals 12 and the corresponding metal lands 2 is provided on the upper surface of the lower wiring board 7.

  As shown in FIG. 4, in such a multilayer substrate for a semiconductor package, the semiconductor chip 4 is mounted on the lower wiring substrate 7 in the multilayer substrate recess 11, and the internal connection terminal 12 and the semiconductor are connected via the connection wires 6. The chip 4 can be used by being electrically and mechanically connected.

  Therefore, in the multilayer substrate for the laminated semiconductor package, the connection wire 6 for wire bonding extends toward the internal connection terminal 12 provided only on the bottom surface of the multilayer substrate recess 11. The distance between the uppermost portion of the substrate and the bottom surface of the concave portion of the multilayer substrate is reduced. That is, since the rising of the connection wire 6 wire-bonded to the semiconductor chip 4 is reduced, the depth of the multilayer substrate recess 11 required for sufficiently storing and protecting the semiconductor chip 4 and the connection wire 6 is reduced.

  Thereby, the thickness of the upper wiring substrate 8 can be set thin, and the multilayer substrate for semiconductor packages can be thinned.

  Further, in the multilayer substrate for the stacked semiconductor package, since the upper and lower wiring substrates are electrically connected, the connection wires 6 connected to the semiconductor chip 4 are provided only on the upper surface portion of the lower wiring substrate. By simply connecting to the internal connection terminal 12, the metal land 2 arranged on the exterior surface (front surface and back surface) of the multilayer substrate and the semiconductor chip 4 can be electrically connected.

  Thereby, the wire layout at the time of mounting a semiconductor chip can be simplified.

  The multilayer substrate for a stacked semiconductor package according to the first embodiment was produced as follows.

<Fabrication of upper wiring board>
In order to produce the upper wiring substrate, first, a through hole was formed in a glass epoxy resin substrate using a drill or a laser. Thereafter, both surfaces of the substrate and the inside of the through hole were laminated with copper foil, a metal pattern was formed by etching, and then a solder resist was applied to both surfaces of the substrate so as to cover the metallic pattern.

  Although detailed contents will be described in the second embodiment to be described later, the thickness of the glass epoxy resin substrate can be set thin in accordance with the thickness of the semiconductor chip mounted on the multilayer substrate for semiconductor package. preferable.

  Subsequently, the solder resist at the position corresponding to the metal land 2 is removed and opened, and then the opening is plated with nickel / gold, so that the metal land 2 as shown in FIG. The provided substrate was prepared.

  It should be noted that the through hole and the metal pattern need not be formed at a location where a through hole 14 to be described later is formed. The metal lands 2 were formed with a pitch of 0.5 mm and a diameter of 0.25 mm.

  Next, as shown in FIG. 5 (a2), a metal bump 9 having a thickness of 120 μm was formed on the metal land 2 on the lower surface of the substrate.

  Thereafter, as shown in FIG. 5 (a3), a prepreg 10 made of a non-flow type glass epoxy material or modified polyimide was formed on the lower surface of the substrate with a thickness of 80 μm while exposing the tip of the metal bump 9.

  Subsequently, a portion corresponding to the through hole 14 was formed by punching a part of the polyimide resin substrate and the prepreg 10 with a mold, and the upper wiring substrate 8 having the through hole 14 was produced.

  As the upper wiring board 8 having the through holes 14, a glass epoxy resin substrate in which the through holes 14 are provided in advance may be used. However, an elaborate work of forming the prepreg 10 so as to avoid the through holes 14 is performed. Therefore, the above manufacturing method is preferable because the contents of the prepreg forming step can be simplified.

<Production of lower wiring board>
Through holes were formed in a polyimide resin substrate having a thickness of 100 μm to 150 μm. Thereafter, both surfaces of the substrate and the inside of the through hole were laminated with copper foil, a metal pattern was formed by etching, and then a solder resist was applied to both surfaces of the substrate so as to cover the metallic pattern.

  Subsequently, after removing or opening the solder resist at the position corresponding to the metal land 2, the opening was plated with nickel / gold. The metal lands 2 were formed with a pitch of 0.5 mm and a diameter of 0.25 mm.

  Further, the internal connection terminals 12 are formed only on a part of the upper surface (upper surface portion) of the substrate so as to be arranged in the vicinity of the mounting region of the semiconductor chip, and the metal land as shown in FIG. The lower wiring board 7 in which 2 was provided on both surfaces and the internal connection terminals 12 were provided only on the upper surface portion was produced.

<Production of multilayer substrate>
After the upper wiring board 8 and the lower wiring board 7 are manufactured, as shown in FIG. 5C, the upper wiring board 8 and the lower wiring board 7 are bonded together using an epoxy-based adhesive, and are used for a semiconductor package. The multilayer substrate 1 was completed.

  The metal land 2 provided on the surface of the upper wiring substrate 8 or the lower wiring substrate 7 that forms the exterior surface (front surface and back surface) of the multilayer substrate 1 is an external terminal on the motherboard of the electronic device on which the multilayer substrate 1 is mounted. Are arranged in correspondence with the arrangement pattern.

  As shown in FIG. 4, such a multilayer semiconductor package multilayer substrate has a semiconductor chip 4 mounted on the upper surface portion of the lower wiring substrate 7 in the multilayer substrate recess 11, and internal connection terminals via connection wires 6. 12 and the semiconductor chip 4 are electrically and mechanically connected to each other, but since the rise of the connecting wire 6 wire-bonded to the semiconductor chip 4 is reduced, the thickness of the upper wiring board 8 can be set thin. A multilayer substrate for a semiconductor package is made thinner.

  Further, as described above, since the upper and lower wiring substrates are electrically connected, the semiconductor chip 4 is wire-bonded to the internal connection terminals 12 provided only on the upper surface portion of the lower wiring substrate. Electrical connection between the chip 4 and the metal land 2 disposed on the exterior surface (front surface and back surface) of the multilayer substrate can be established, and the wire layout when the semiconductor chip is mounted can be simplified.

  Incidentally, in assembling a semiconductor package (during package assembly), generally, a process of heating the substrate to about 150 ° C. is essential. As a result of investigations by the present inventors, it is necessary to suppress the amount of thermal deformation of the lower wiring substrate 7 to 20 μm or less in order to obtain a package assembly property that allows the semiconductor chip 4 to be stably mounted on the bottom of the multilayer substrate recess 11. Found that there is.

  And even for a thin lower wiring board 7 having a base material thickness of 100 μm or more and 150 μm or less, the amount of thermal deformation of the lower wiring board can be suppressed to 20 μm or less with respect to a general heating temperature at the time of package assembly. I also found.

  As a result, it was found that the multilayer substrate for a stacked semiconductor package according to the first embodiment can exhibit a stable package assembly property while realizing a reduction in thickness.

[Embodiment 2]
Next, a stacked semiconductor package according to a second aspect of the present invention will be described below using the second embodiment as an example.

  The stacked semiconductor package 13 according to the second embodiment is a semiconductor package in which the semiconductor chip is wire-bonded to the first embodiment, as shown in the front view (a) and the rear view (b) of FIG. A 150 μm thick upper wiring board 8 having a rectangular plate-like outer shape and provided with a resin sealing portion 5 in the approximate center, and a base material thickness of 100 μm, the outer shape being the same as that of the upper wiring board 8. The lower wiring board 7 having a thickness of 150 μm or less is provided.

  Further, in the second embodiment, as shown in FIG. 4 which is an end view of the cross section taken along the line CD in FIG. 3, the semiconductor chip 4 is mounted on the upper surface portion of the lower wiring substrate 7 which is the bottom of the multilayer substrate recess 11. The internal connection terminals 12 and the semiconductor chip 4 are electrically and mechanically connected via the connection wires 6 made of gold (Au). The semiconductor chip 4 and the connection wire 6 are covered with a resin sealing portion 5.

  In addition, description about the member which is common in the multilayer substrate concerning the said Embodiment 1 is abbreviate | omitted.

  The stacked semiconductor package according to the second embodiment was manufactured as follows.

  As shown in FIG. 6, the multilayer substrate 1 according to the first embodiment is prepared, and the internal connection terminal 12 is exposed to the upper surface portion of the lower wiring substrate 7 that is the bottom of the multilayer substrate recess 11, and the thickness is 70 μm. The semiconductor chip 4 was mounted (die bonding process).

  When mounting the semiconductor chip 4, an insulating adhesive sheet is attached to the back surface (opposite surface of the circuit element forming surface) of the semiconductor wafer, which is an aggregate of the semiconductor chips 4, and the semiconductor wafer is separated into pieces by dicing. Equipped with.

  Subsequently, as shown in FIG. 6, the electrode pad portion of the semiconductor chip 4 and the internal connection terminal 12 of the lower wiring substrate 7 were connected by a connection wire 6 made of a highly conductive metal (wire bonding step).

  As these connection wires 6, gold (Au) wires of 25 μmφ were used. Further, the connection wires 6 were connected so as not to contact each other. In addition, although the part connected with the electrode pad part of the semiconductor chip 4 swells about 70 micrometers from the upper part of the semiconductor chip 4, this is unavoidable structurally of the wire bond.

  Next, as shown in FIG. 6, the semiconductor chip 4, the connection wires 6, and the internal connection terminals 12 are covered, and the resin surface is on the same plane as the upper surface of the upper wiring substrate 8, that is, the upper surfaces of both. The resin sealing portion 5 made of an epoxy resin was formed so that the multilayer substrate recess 11 was sealed (resin sealing step).

  The resin sealing portion 5 was formed such that the upper surface thereof had a distance of 30 μm or more and 50 μm or less from the upper portion of the connection wire 6 wire-bonded to the semiconductor chip 4. The reason for such an interval will be described later.

  The resin sealing portion 5 can be formed by a potting drawing method. However, as long as the surface of the resin sealing portion 5 does not protrude from the upper wiring substrate 8, a top gate type transfer molding method, A resin printing method using a screen mask can also be used.

  Subsequently, as shown in FIG. 6, a 0.3 mmφ solder bump 3 is formed on the 0.25 mmφ metal land 2 arranged on the exterior side (lower surface side) of the lower wiring substrate 7, and the laminated semiconductor A package 13 was produced.

  The solder bump 3 may be formed by a solder ball mounting method or by solder paste printing. Further, the solder bumps 3 may be formed on the metal lands 2 arranged on the exterior side of the upper wiring substrate 8 according to the use of the semiconductor package.

  Further, this semiconductor package may be a land grid array (LGA) type semiconductor package without providing the solder bump 3.

  When the multilayer substrate has a plurality of multilayer substrate recesses 11 and is processed for a plurality of semiconductor packages, it is a matter of course that each device portion is cut into individual semiconductor packages. .

  In this second embodiment, since the multilayer substrate according to the first embodiment is provided, the rising of the connection wire 6 wire-bonded to the semiconductor chip 4 is reduced, and the thickness of the semiconductor chip 4 to be mounted is reduced. Accordingly, since the thickness of the upper wiring substrate 8 can be set thin, the multilayer substrate for the semiconductor package can be thinned.

  Further, since the upper and lower wiring boards are electrically connected, the semiconductor chip 4 is wire-bonded to the internal connection terminals 12 provided only on one side of the board, so that the semiconductor chip 4 and the multilayer board are packaged. Electrical connection with the arranged metal lands 2 can be achieved, and the wire layout when the semiconductor chip is mounted can be simplified.

  Further, in assembling a semiconductor package (during package assembly), generally, for example, a process of heating the substrate to about 150 ° C., such as a bonding process of a connecting wire, a resin sealing process of a semiconductor chip, or an external terminal forming process. Although necessary, since the thickness of the base material of the lower wiring board 7 is set to 100 μm or more and 150 μm or less, the amount of thermal deformation of the lower wiring board can be suppressed to 20 μm or less, and stable package and assembly properties are exhibited. Can do.

  Further, as a result of studies by the present inventors, it is preferable to make the cover of the resin sealing portion 5 as thick as possible from the side of protecting the semiconductor chip and the connection wire from external impact, but as in the second embodiment. Furthermore, it has been found that when the distance between the upper surface of the resin sealing portion and the upper portion of the connection wire is 30 μm or more and 50 μm or less, the semiconductor chip and the connection wire can be sufficiently protected from external impact.

  Further, in the second embodiment, since the upper surface of the resin sealing portion 5 and the upper surface of the upper wiring substrate 8 are present on the same plane, individual semiconductor packages are formed while reducing the stackable interval of the semiconductor packages. Thinning can be achieved.

  This is because, when the upper surface of the resin sealing portion 5 protrudes from the upper surface of the upper wiring substrate 8, when a plurality of stacked semiconductor packages are stacked, the stacking interval is set to the thickness at which the resin sealing portion 5 protrudes. On the other hand, when the upper surface of the resin sealing portion 5 is recessed more than the upper surface of the upper wiring substrate 8, there is still room for the upper wiring substrate 8 to be thinner. Because.

  As described above, in the stacked semiconductor package according to the second embodiment, the thickness of the upper wiring substrate and the resin sealing portion is set to be thin, and the individual semiconductor packages are thinned while narrowing the interval where the semiconductor packages can be stacked. Therefore, the mounting density of the semiconductor chip in the electronic device is improved. In addition, stable package assembly and sufficient impact resistance can be obtained.

[Other matters]
(1) “Upper” and “lower” in the upper wiring board 8 and the lower wiring board 7 are convenient names, and do not limit the upper and lower sides of the actual arrangement when mounted on the motherboard. That is, for example, as shown in FIG. 8, the semiconductor package is inverted according to the use of the semiconductor package, and the solder bump 3 is formed on the metal land 2 arranged on the exterior side of the upper wiring board 8 and mounted on the motherboard. You can also

  (2) In the first and second embodiments, the case where there is one upper wiring substrate 8 is shown, but it is needless to say that two or more upper wiring substrates 8 may be laminated.

  (3) In the second embodiment, the case where one semiconductor chip 4 is mounted in the concave portion of the multilayer substrate is shown, but the number of semiconductor chips to be mounted is not limited. That is, for example, as shown in FIG. 7A, a semiconductor package in which two semiconductor chips 4 are stacked one above the other and mounted in a concave portion of the multilayer substrate, and each of them is wire-bonded to the internal connection terminal 12 is manufactured. Good. Further, for example, as shown in FIG. 7B, two semiconductor chips 4 may be arranged side by side and mounted in the multilayer substrate recess. When a plurality of semiconductor chips are stacked one above the other, the lowermost semiconductor chip may be mounted using a flip chip method instead of the wire bond method.

  (4) When a plurality of stacked semiconductor packages of the present invention are stacked, the stacking intervals of the packages are close to each other, so that it is possible to improve the mounting density of the semiconductor chips in the electronic device. Needless to say, the package can be stacked by combining the stacked semiconductor packages according to the prior art.

  As described above, according to the present invention, the thickness of the upper wiring substrate and the resin sealing portion can be set to be thin, and the multilayer substrate and the semiconductor package can be thinned, thereby improving the mounting density of the semiconductor chip in the electronic device. Therefore, the industrial applicability is great.

FIG. 1 is a front view and a rear view showing a multilayer substrate for a semiconductor package according to the present invention. FIG. 2 is an end view showing an example of a cross section taken along line AB of FIG. FIG. 3 is a front view and a rear view showing the semiconductor package according to the present invention. FIG. 4 is an end view showing a cross section taken along line CD of FIG. FIG. 5 is a diagram for explaining a manufacturing process of a multilayer substrate for a semiconductor package according to the present invention. FIG. 6 is a diagram for explaining a manufacturing process of a semiconductor package according to the present invention. FIG. 7 is an end view showing another example of the cross section taken along the line AB of FIG. FIG. 8 is a sagittal sectional view showing another example of the semiconductor package according to the present invention. FIG. 9 is a sagittal sectional view showing a stacked semiconductor package according to the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Multilayer board | substrate for semiconductor packages 2 Metal land 3 Solder bump 4 Semiconductor chip 5 Resin sealing part 6 Connection wire 7 Lower wiring board 8 Upper wiring board 9 Bump 10 Prepreg 11 Multilayer board recessed part 12 Internal connection terminal 13 Semiconductor package 14 Through-hole 101 Lower substrate 102 Upper substrate 103 Solder bump 104 Semiconductor chip 105 Sealing resin 106 Connection wire 107 Metal land 108 Metal land

Claims (9)

A stacked semiconductor package in which a semiconductor chip is sealed with a resin,
Wherein the semiconductor chip has a through hole sized to fit, and has a metal lands on both sides, and the upper wiring board which these both sides of the metal lands are electrically connected by through-holes,
A lower wiring board having metal lands on both sides and electrically connecting the metal lands on both sides by through holes;
Wherein the upper wiring board lower wiring board is Awa bonding, and both substrates are made electrically connected via the bumps caused Awa bonding portion,
Caused by allowed Awa bonding the substrates, wherein the recess from the through-hole semiconductor chip is disposed, the internal connection the semiconductor chip is part of the metal lands of the lower wiring substrate exposed in said recess Is electrically connected to the terminal ,
A stacked semiconductor package, wherein a resin sealing portion is formed in the recess so as to seal the semiconductor chip with resin. The stacked semiconductor package according to claim 1, wherein a thickness of a base material of the lower wiring substrate is 100 μm or more and 150 μm or less. 3. The stacked semiconductor package according to claim 1 , wherein a plurality of semiconductor packages including the upper wiring substrate, the lower wiring substrate, and the semiconductor chip are stacked . 4. The stacked type according to claim 1, wherein an upper surface of a resin sealing portion that covers the semiconductor chip with a resin and an upper surface of the upper wiring substrate are on the same plane. 5. Semiconductor package. The electrical connection between the semiconductor chip and a part of the metal land of the lower wiring board is made by a connection wire,
And the upper surface of the resin sealing portion, the distance between the top of the connecting wires of wire bonding to the semiconductor chip, laminate according to any one of claims 1 4, characterized in that at 30μm or 50μm or less Type semiconductor package. A method of manufacturing a stacked semiconductor package in which a semiconductor chip is sealed with a resin ,
A step of said semiconductor chip has a through hole sized to fit, and has a metal lands on both sides, these both sides of the metal lands to prepare an upper wiring board are electrically connected by through-holes,
A step of preparing a lower wiring board having metal lands on both sides and electrically connecting the metal lands on both sides by through holes;
A step of Awa bonded to electrical connections are made via the bumps between the upper wiring board the lower wiring board, the two substrates,
The semiconductor chip is disposed in a recess from the through hole caused by allowed Awa adhesion of both substrates, interconnect is further part of the metal lands of the lower wiring board and the semiconductor chip is exposed to the recess Electrically connecting to the terminals ;
It said semiconductor chip and to cover the internal connection terminals, and forming a resin sealing portion in the recess, the method of fabricating the multilayer semiconductor package with. 7. The method for manufacturing a stacked semiconductor package according to claim 6, wherein the thickness of the base material of the lower wiring substrate is not less than 100 μm and not more than 150 μm. 8. The method of manufacturing a stacked semiconductor package according to claim 6, further comprising a step of stacking a plurality of resin-sealed semiconductor packages including the upper wiring substrate, the lower wiring substrate, and a semiconductor chip. The electrical connection between the semiconductor chip and a part of the metal land of the lower wiring substrate is performed by a connection wire,
7. The connection wire is covered with a resin so that an interval between an upper surface of the resin sealing portion and an upper portion of a connection wire wire-bonded to the semiconductor chip is 30 μm or more and 50 μm or less. method for manufacturing a stacked semiconductor package according to any one of 1-8.

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