JPH07226583A - Manufacture of multilayer wiring board - Google Patents
Manufacture of multilayer wiring boardInfo
- Publication number
- JPH07226583A JPH07226583A JP1704894A JP1704894A JPH07226583A JP H07226583 A JPH07226583 A JP H07226583A JP 1704894 A JP1704894 A JP 1704894A JP 1704894 A JP1704894 A JP 1704894A JP H07226583 A JPH07226583 A JP H07226583A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- recessed
- wiring board
- adhesive material
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000463 material Substances 0.000 claims abstract description 69
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000011889 copper foil Substances 0.000 claims abstract description 18
- 238000007639 printing Methods 0.000 claims abstract description 15
- 238000001035 drying Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000000945 filler Substances 0.000 claims abstract description 7
- 239000000853 adhesive Substances 0.000 claims description 35
- 230000001070 adhesive effect Effects 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims description 9
- 239000011256 inorganic filler Substances 0.000 claims description 7
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 7
- 238000003486 chemical etching Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 13
- 229920000647 polyepoxide Polymers 0.000 abstract description 13
- 238000010030 laminating Methods 0.000 abstract description 12
- 238000007747 plating Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract description 4
- 238000003475 lamination Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract 2
- 230000017525 heat dissipation Effects 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000020169 heat generation Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- WNROFYMDJYEPJX-UHFFFAOYSA-K aluminium hydroxide Chemical compound [OH-].[OH-].[OH-].[Al+3] WNROFYMDJYEPJX-UHFFFAOYSA-K 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000013034 phenoxy resin Substances 0.000 description 1
- 229920006287 phenoxy resin Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層配線板の製造法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board.
【０００２】[0002]
【従来の技術】近年、多層配線板の高密度化、薄型化が
進展し、薄物ガラス−エポキシプリプレグを回路基板の
間に挟んで積層多層化する方法、もしくはガラスクロス
を使用しないで、可とう性を有するシート状接着材料を
回路基板の間に挟んで積層多層化する多層配線板製造法
が検討されている。また、隣接する配線層のみ接続を行
う、いわゆるインタースティシャルバイアホールを形成
する方法が検討され、例えば、特開平５−２５９６４９
号公報に開示されているように、層間接続用穴をあらか
じめ明けた絶縁接着材料付き銅箔を回路基板に積層する
方法が知られている。さらにまた、回路間の間隙にレジ
ストなどの樹脂を印刷した後、穴明けした絶縁材料を積
層する方法が、特開平１−２５９６４９号公報に開示さ
れ、レジストインクなどの樹脂を塗工または印刷した
後、穴明けした絶縁材料を積層する方法が、特開平１−
２５９６４９号公報に開示されている。2. Description of the Related Art In recent years, multi-layer wiring boards have been made higher in density and thinner, and a method of laminating a thin glass-epoxy prepreg between circuit boards to form a multi-layer structure or using no glass cloth is possible. A multilayer wiring board manufacturing method has been studied in which a sheet-like adhesive material having a property is sandwiched between circuit boards to form a multilayer structure. Further, a method of forming a so-called interstitial via hole in which only adjacent wiring layers are connected has been studied, and for example, Japanese Patent Laid-Open No. 5-259649.
As disclosed in the publication, a method is known in which a copper foil with an insulating adhesive material in which holes for interlayer connection are preliminarily formed is laminated on a circuit board. Furthermore, a method of printing a resin such as a resist in a gap between circuits and then laminating a perforated insulating material is disclosed in JP-A-1-259649, in which a resin such as a resist ink is applied or printed. After that, a method of laminating a perforated insulating material is disclosed in JP-A-1-
It is disclosed in Japanese Patent No. 259649.
【０００３】[0003]
【発明が解決しようとする課題】上記した従来技術のう
ち、薄物ガラス−エポキシプリプレグを使用して積層多
層化する方法については、樹脂の流動量が十分でないた
め、成形性、回路充填性が十分でないという課題が有っ
た。また、可とう性を有するシート状接着材料を、回路
基板の間に挟んで多層化する方法についても、回路銅箔
の厚さが３５μｍ以上になると回路充填性が十分でなか
った。また、層間接続用穴をあらかじめ明けた絶縁接着
材料付き銅箔を回路基板に積層する方法では、回路充填
性の向上と、層間接続用穴からの絶縁接着材料の流動量
低減の両立が難しく、特に回路の厚さが３５μｍ以上の
場合には、平坦性と、回路充填性と、層間接続の信頼性
の高い多層配線板は得られていなかった。Among the above-mentioned prior arts, the method of laminating and laminating using thin glass-epoxy prepreg has insufficient moldability and circuit filling because the resin flow amount is not sufficient. There was a problem that was not. Also, in the method of sandwiching a flexible sheet-shaped adhesive material between circuit boards to form a multilayer, the circuit filling property was not sufficient when the thickness of the circuit copper foil was 35 μm or more. Further, in a method of laminating a copper foil with an insulating adhesive material having a hole for interlayer connection preliminarily formed on a circuit board, it is difficult to improve the circuit filling property and reduce the flow amount of the insulating adhesive material from the hole for interlayer connection. In particular, when the circuit thickness is 35 μm or more, a multilayer wiring board having high flatness, circuit filling property, and reliability of interlayer connection has not been obtained.
【０００４】さらにまた、回路間凹部に充填材を印刷す
る方法では、印刷時のずれなどにより、回路と凹部充填
材に間隙が発生するか、または回路と凹部充填材が重な
るため凹凸の原因になるなどの課題が発生しており、こ
れを回避するためには、研磨による平滑化などの手段を
取る必要があり、製造コストの上昇を招いていた。ま
た、絶縁接着材料と凹部充填材との接着性が低く、この
界面で剥離が起こり易いという課題が有った。さらに、
絶縁接着材料を積層する際に回路と凹部充填材との界面
に応力が集中しクラックが発生し信頼性が低下し易いと
いう課題があった。Furthermore, in the method of printing the filling material in the recesses between the circuits, a gap may be generated between the circuit and the filling material for the recesses due to misalignment at the time of printing, or unevenness may be caused because the circuit and the filling material for the recesses overlap. However, in order to avoid this, it is necessary to take measures such as smoothing by polishing, which causes an increase in manufacturing cost. Further, there is a problem that the adhesiveness between the insulating adhesive material and the recess filling material is low, and peeling easily occurs at this interface. further,
When laminating the insulating adhesive material, there was a problem that stress concentrates on the interface between the circuit and the recess filling material, cracks occur, and the reliability tends to decrease.
【０００５】本発明は、回路充填性の向上と、層間接続
用穴からの絶縁接着材料の流動量低減の両立ができ、か
つ層間接続の信頼性に優れた多層配線板の製造法を提供
することを目的とする。The present invention provides a method for manufacturing a multilayer wiring board which is capable of both improving the circuit filling property and reducing the flow rate of the insulating adhesive material from the interlayer connection hole and having excellent reliability of interlayer connection. The purpose is to
【０００６】[0006]
【課題を解決するための手段】本発明の多層配線板の製
造法は、回路基板上の凹部に、ＡまたはＢステージで流
動性を有する凹部充填材を印刷または塗布する工程、そ
の凹部充填材を乾燥し、ＡまたはＢステージに硬化する
工程、この上にシート状絶縁性接着材料を重ね、加圧加
熱して積層一体化する工程からなることを特徴とする。A method for manufacturing a multilayer wiring board according to the present invention comprises a step of printing or applying a recessed filling material having fluidity at the A or B stage on a recessed portion on a circuit board, and the recessed filling material. Is dried and cured to the A or B stage, and a sheet-like insulating adhesive material is superposed on this, and heated under pressure to be laminated and integrated.
【０００７】例えば、以下の工程のように行う。 （ａ）回路基板上の凹部に、ＡまたはＢステージで流動
性を有する凹部充填材を印刷または塗布する工程 （ｂ）凹部充填材を乾燥し、ＡまたはＢステージに硬化
する工程 （ｃ）回路基板上に、予め穴明けしたシート状絶縁接着
材料付き銅箔を回路と接着材料とが接するように重ね、
加圧加熱して積層一体化する工程 （ｄ）層間接続を含む回路形成を行う工程 （ｅ）必要に応じて前記工程（ａ）〜（ｄ）を繰り返し
多層化する工程For example, the following steps are performed. (A) A step of printing or applying a recessed filler having fluidity in the A or B stage on the recessed part on the circuit board (b) A step of drying the recessed filler and curing it in the A or B stage (c) Circuit Pre-drilled copper foil with sheet-shaped insulating adhesive material on the substrate so that the circuit and the adhesive material are in contact,
Step of pressurizing and heating to integrate and laminate (d) Step of forming circuit including interlayer connection (e) Step of repeating steps (a) to (d) as required to form a multilayer
【０００８】また、以下のようにすることもできる。 （ａ）回路基板上の凹部に、Ｂステージで流動性を有す
る凹部充填材を印刷または塗布する工程 （ｂ）凹部充填材を乾燥し、Ｂステージに硬化する工程 （ｃ）回路基板上に、ケミカルエッチングにより穴明け
可能なシート状絶縁接着材料付き銅箔を重ね、加圧加熱
して積層一体化する工程 （ｄ）回路形成を行う工程 （ｅ）回路をレジストとし、層間接続穴をケミカルエッ
チングにより形成し、層間接続を行う工程 （ｆ）必要に応じて前記工程（ａ）〜（ｅ）を繰り返し
多層化する工程Further, the following is also possible. (A) a step of printing or applying a recessed filling material having fluidity in the B stage on the recessed portion on the circuit board; (b) a step of drying the recessed portion filling material and curing it on the B stage; (c) a circuit board; Step of stacking copper foil with sheet-like insulating adhesive material that can be punched by chemical etching, and pressurizing and heating to integrate and laminate (d) Step of forming circuit (e) Using resist as circuit and chemical etching of interlayer connection hole And (f) repeating the above steps (a) to (e) to form a multilayer structure.
【０００９】また、この凹部充填材には、高熱伝導の無
機フィラーを含ませることもできる。Further, the recess filling material may contain an inorganic filler having a high thermal conductivity.
【００１０】本発明に用いる回路基板には、ガラス布−
エポキシ樹脂を用いた銅張り積層板、紙−フェノール樹
脂を用いた銅張り積層板、金属ベース基板、金属コア基
板等がある。The circuit board used in the present invention is made of glass cloth.
There are a copper clad laminate using an epoxy resin, a copper clad laminate using a paper-phenol resin, a metal base substrate, a metal core substrate and the like.
【００１１】凹部充填材の組成に関しては、ＡまたはＢ
ステージ状態で流動性を有することが必要である。絶縁
信頼性の良好であることが好ましく、例えばエポキシ樹
脂系、フェノール樹脂系が示される。またこれらの樹脂
系と無機フィラーとの混合物を用いることができる。無
機フィラーとしては、シリカ、アルミナなどを用いるこ
とができる。また市販の熱硬化型ソルダーレジストＣＣ
Ｒ−５０６ＧＴＨ（アサヒ化研株式会社製、商品名）、
紫外線硬化型ソルダーレジスト（アサヒ化研株式会社
製、商品名）などを用いても良い。Regarding the composition of the recess filling material, A or B
It is necessary to have fluidity in the stage state. It is preferable that the insulation reliability is good, and examples thereof include epoxy resin type and phenol resin type. Also, a mixture of these resin systems and an inorganic filler can be used. As the inorganic filler, silica, alumina or the like can be used. Commercially available thermosetting solder resist CC
R-506GTH (Asahi Kaken Co., Ltd., trade name),
An ultraviolet curable solder resist (trade name, manufactured by Asahi Kaken Co., Ltd.) may be used.
【００１２】また凹部充填材の流動性を調節するため、
または機械的強度を向上する、または熱膨張率の調整、
あるいはコストを低減するなどのために各種フィラーを
加えても良い。その例としては、シリカ、アルミナ、水
酸化アルミニウム、タルクなどが挙げられる。In order to control the fluidity of the recess filling material,
Or improve the mechanical strength, or adjust the coefficient of thermal expansion,
Alternatively, various fillers may be added to reduce the cost. Examples thereof include silica, alumina, aluminum hydroxide, talc and the like.
【００１３】また、配線板の放熱性を向上させるため、
凹部充填材に高放熱無機フィラーを含有せしめることが
できる。その例としては、アルミナ、窒化ホウ素、窒化
アルミニウムなどが挙げられる。In order to improve the heat dissipation of the wiring board,
The recess filling material can contain a high heat dissipation inorganic filler. Examples thereof include alumina, boron nitride, aluminum nitride and the like.
【００１４】なお、ここでＡ，Ｂ，Ｃステージとは、以
下に定義するものである。本発明でいうＡ，Ｂ，Ｃステ
ージは、接着剤の硬化の程度を示すものであり、Ａステ
ージとは、ほぼ未硬化でゲル化していない状態を示し、
全硬化発熱量の０〜２０％の発熱を終えた状態であり、
Ｂステージとは若干硬化、ゲル化が進んだ状態を示し、
全硬化発熱量の２０〜６０％の発熱を終えた状態であ
り、Ｃステージとはかなり硬化が進みゲル化した状態を
示し、全硬化発熱量の６０〜１００％の発熱を終えた状
態であることとする。The A, B, and C stages are defined below. The A, B, and C stages referred to in the present invention indicate the degree of curing of the adhesive, and the A stage indicates a substantially uncured and non-gelled state.
It is in a state where the heat generation of 0 to 20% of the total curing heat value is finished,
B stage is a state where it is slightly cured and gelled,
It is a state in which heat generation of 20 to 60% of the total heat generation amount for curing has been completed, C stage shows a state in which curing has considerably progressed and gelled, and is a state in which heat generation of 60 to 100% of the total heat generation amount for curing has been completed. I will.
【００１５】絶縁接着材料については特に制限するもの
ではないが、エポキシ樹脂、イミド樹脂などの電気的特
性の良好なものが好ましい。また、可とう性成分とし
て、ゴム、フェノキシ樹脂、高分子量エポキシ樹脂、超
高分子量エポキシ樹脂などを加えることができる。ま
た、これらを銅箔に塗布したものか、または、これらの
絶縁接着材料をフィルム化したものと銅箔を積層一体化
したものを用いても良い。また絶縁接着材料に高放熱性
の無機フィラーを含有せしめることにより、多層配線板
の放熱性を向上させることができる。また、この場合、
金属ベース基板などの放熱性の高い回路基板と組み合わ
せることにより放熱性向上の効果が大きくなる点で好ま
しい。The insulating adhesive material is not particularly limited, but an epoxy resin, an imide resin or the like having good electrical characteristics is preferable. Further, as the flexible component, rubber, phenoxy resin, high molecular weight epoxy resin, ultra high molecular weight epoxy resin, etc. can be added. Moreover, you may use what apply | coated these to copper foil, or what made these insulating adhesive materials into a film, and laminated | stacked and integrated copper foil. Further, the heat dissipation of the multilayer wiring board can be improved by incorporating the insulating adhesive material with a high heat dissipation inorganic filler. Also in this case,
Combining with a circuit board having a high heat dissipation property such as a metal base substrate is preferable in that the effect of improving the heat dissipation property becomes large.
【００１６】絶縁接着材料に関しては、積層後にドリル
により穴を明けてもよいが、予めドリルまたはパンチン
グにより穴を明ける方式、あるいはケミカルエッチング
より積層後に穴明けする方式等があり、特に制限するも
のではない。先に穴明けした後積層する場合には、穴明
け部からのしみだしが少ないものである必要がある。Regarding the insulating adhesive material, holes may be drilled after laminating, but there are methods such as drilling or punching in advance, or chemical laminating followed by boring, and the like. Absent. When the holes are first drilled and then the layers are laminated, it is necessary that the exudation from the holes is small.
【００１７】続いて、製造法について説明する。凹部充
填材の印刷、または塗工方法に関しては、スクリーン印
刷法などがある。これらの方法を用いて回路基板の凹部
に印刷を行った後、乾燥を行う。凹部充填材の量につい
ては凹部を埋めるに十分な量を印刷もしくは塗布する必
要がある。Next, the manufacturing method will be described. As a method of printing or coating the recess filling material, there is a screen printing method or the like. Printing is performed on the concave portion of the circuit board using these methods, and then drying is performed. Regarding the amount of the recess filling material, it is necessary to print or apply a sufficient amount to fill the recess.
【００１８】印刷パターンについては回路と凹部充填材
が重ならないように０．０５〜０．２ｍｍ程度の間隙を
置くことが望ましい。間隔については印刷精度により調
整をすることが望ましい。なお回路間隙が０．４ｍｍよ
り小さい場合には、この間に印刷を行うことが難しく、
その場合には回路上に層間接続がない場合には、全面に
印刷する。回路上の凹部充填材は積層時の圧力により流
動するため、良好な基板平坦性が得られる。凹部充填材
を印刷または塗布した回路基板と接着材料を積層する。
この際に凹部充填材に流動性が有るため積層時に流動
し、その結果、回路と凹部充填材の間隙を気泡などが発
生しないように充填することができる。積層後、必要に
応じて導電ペースト、めっき、ワイヤボンディングなど
により層間接続を図ることができる。Regarding the print pattern, it is desirable to set a gap of about 0.05 to 0.2 mm so that the circuit and the recess filling material do not overlap each other. It is desirable to adjust the spacing according to the printing accuracy. If the circuit gap is smaller than 0.4 mm, it is difficult to print during this period.
In that case, if there is no interlayer connection on the circuit, the entire surface is printed. Since the recess filling material on the circuit flows due to the pressure at the time of stacking, good substrate flatness is obtained. The circuit board on which the recess filling material is printed or applied and the adhesive material are laminated.
At this time, since the recess filling material has fluidity, it flows at the time of stacking, and as a result, the gap between the circuit and the recess filling material can be filled without generating bubbles or the like. After lamination, interlayer connection can be achieved by a conductive paste, plating, wire bonding, etc., if necessary.
【００１９】次に絶縁接着材料の積層方法については、
プレス、真空プレス、ホットロールラミネータ、真空ラ
ミネータなどを使用することができる。続いてエッチン
グレジストを形成し、不要な銅をエッチング除去して、
基板の必要な箇所に導体回路を形成する。以上の製造工
程を１回または必要に応じて経ることによって目的の多
層配線板を得ることができる。Next, regarding the method of laminating the insulating adhesive material,
A press, a vacuum press, a hot roll laminator, a vacuum laminator, etc. can be used. Subsequently, an etching resist is formed, and unnecessary copper is removed by etching,
Conductor circuits are formed on the required portions of the substrate. The desired multilayer wiring board can be obtained by performing the above manufacturing process once or as necessary.
【００２０】[0020]
【作用】絶縁接着材料と回路層を複数を配した多層配線
板において、回路間の凹部を樹脂により平坦化を行った
後、接着材料を積層することによって多層配線板を構成
することにより、多層配線板の成形性向上、表面平坦
化、薄型化を図ることができた。絶縁接着材料と回路層
を複数を配した多層配線板において、回路間の凹部を樹
脂により平坦化を行った後、予め層間接続を行う部分に
穴明け加工を施した絶縁接着材料付き銅箔もしくは接着
材料を積層することによって多層配線板を構成すること
により、上記の効果に加えて層間接続信頼性向上を図る
ことができた。凹部充填材及びもしくは絶縁接着材料に
高熱伝導の無機フィラーを含むことにより上記の効果に
加えて、基板の放熱性を向上することが出来た。In the multilayer wiring board in which a plurality of insulating adhesive materials and circuit layers are arranged, the recesses between the circuits are flattened by the resin, and then the adhesive material is laminated to form the multilayer wiring board. We were able to improve the formability of the wiring board, flatten the surface, and make it thinner. In a multi-layer wiring board in which a plurality of insulating adhesive materials and circuit layers are arranged, the recesses between the circuits are flattened with a resin, and then copper foil with an insulating adhesive material is pre-drilled on the portions to be interlayer-connected. By constructing the multilayer wiring board by laminating the adhesive material, the interlayer connection reliability could be improved in addition to the above effects. In addition to the above effects, the heat dissipation of the substrate could be improved by including the inorganic filler having high thermal conductivity in the recess filling material and / or the insulating adhesive material.
【００２１】[0021]
実施例１ （１）回路を作製した銅箔の厚さが３５μｍであるガラ
スエポキシ片面板にソルダーレジスト（ＣＣＲ−５０６
ＧＴＨ（アサヒ化研株式会社製、商品名）を、乾燥後の
膜厚が３５μｍになるように印刷した後、１１０℃にて
１０分乾燥する。 （２）低分子エポキシ樹脂と高分子量エポキシ樹脂を主
成分とするシート状絶縁接着材料（厚さ１００μｍ）
を、前記の凹部充填材料を印刷した配線板２枚の間に挟
んで加熱加圧一体化する。 （３）めっきにより層間接続を行う。Example 1 (1) Solder resist (CCR-506) was formed on a glass epoxy single-sided plate having a thickness of 35 μm of a copper foil on which a circuit was manufactured.
GTH (trade name, manufactured by Asahi Kaken Co., Ltd.) is printed so that the film thickness after drying is 35 μm, and then dried at 110 ° C. for 10 minutes. (2) Sheet-shaped insulating adhesive material containing low-molecular epoxy resin and high-molecular-weight epoxy resin as main components (thickness 100 μm)
Is sandwiched between two wiring boards printed with the above-mentioned recess filling material, and integrated under heating and pressure. (3) Interlayer connection is made by plating.
【００２２】実施例２ （１）銅箔の厚さが７０μｍである配線板にソルダーレ
ジスト（ＣＣＲ−５０６ＧＴＨ（アサヒ化研株式会社
製、商品名）を乾燥後の膜厚が７０μｍになるように印
刷した後、１１０℃にて１０分乾燥硬化する。 （２）低分子エポキシ樹脂と高分子量エポキシ樹脂を主
成分とする絶縁接着材料（５０μｍ）付き銅箔の層間接
続を行う部所にパンチングで穴明けを行い、これと前記
の凹部充填材料を印刷した配線板を加熱加圧一体化す
る。 （３）めっきにより層間接続を行う。 （４）銅箔のエッチング処理によりパターンを形成す
る。Example 2 (1) A wiring board having a copper foil thickness of 70 μm was coated with a solder resist (CCR-506GTH (manufactured by Asahi Kaken Co., Ltd., trade name) so that the film thickness after drying was 70 μm. After printing, it is dried and cured for 10 minutes at 110 ° C. (2) Punching is performed on the part where the interlayer connection of the copper foil with the insulating adhesive material (50 μm) containing a low molecular weight epoxy resin and a high molecular weight epoxy resin as a main component is performed. Holes are formed and the wiring board printed with the above-mentioned recess filling material is integrated under heating and pressure (3) Interlayer connection is performed by plating (4) A pattern is formed by etching the copper foil.
【００２３】実施例３ （１）銅箔の厚さが７０μｍである配線板にソルダーレ
ジスト（ＣＣＲ−５０６ＧＴＨ（アサヒ化研株式会社
製、商品名）を乾燥後の膜厚が７０μｍになるように印
刷した後、１１０℃にて１０分乾燥硬化する。 （２）低分子エポキシ樹脂と高分子量エポキシ樹脂を主
成分とする絶縁接着材料（５０μｍ）付き銅箔の層間接
続を行う部所にパンチングで穴明けを行い、これと前記
の凹部充填材料を印刷した配線板を加熱加圧一体化す
る。 （３）めっきにより層間接続を行う。 （４）銅箔のエッチング処理によりパターンを形成す
る。Example 3 (1) A wiring board having a copper foil thickness of 70 μm was coated with a solder resist (CCR-506 GTH (trade name, manufactured by Asahi Kaken Co., Ltd.) so that the film thickness after drying was 70 μm. After printing, it is dried and cured for 10 minutes at 110 ° C. (2) Punching is performed on the part where the interlayer connection of the copper foil with the insulating adhesive material (50 μm) containing a low molecular weight epoxy resin and a high molecular weight epoxy resin as a main component is performed. Holes are formed and the wiring board printed with the above-mentioned recess filling material is integrated under heating and pressure (3) Interlayer connection is performed by plating (4) A pattern is formed by etching the copper foil.
【００２４】比較例１ 凹部充填材料によって回路間の凹部の充填を行わない他
は、実施例１と同様である。Comparative Example 1 The same as Example 1 except that the recesses between the circuits were not filled with the recess filling material.
【００２５】比較例２ 凹部充填材料の乾燥硬化条件が１６０℃、３０分であ
り、流動性のない状態に硬化した以外は実施例２と同様
である。Comparative Example 2 The same procedure as in Example 2 was carried out except that the recess filling material was dried and cured at 160 ° C. for 30 minutes and was cured to have no fluidity.
【００２６】以上述べたようにして作製した多層配線板
の特性を、表１に示す。本発明による多層配線板は比較
例に比べて表面平坦性の点で優れている。Table 1 shows the characteristics of the multilayer wiring board manufactured as described above. The multilayer wiring board according to the present invention is superior in surface flatness to the comparative example.
【００２７】[0027]
【表１】 １）耐電圧は上下パターン間で測定。[Table 1] 1) Withstand voltage is measured between upper and lower patterns.
【００２８】ここで、評価の判断基準を説明する。 （回路充填性）顕微鏡観察により、下層回路と絶縁接着
材料との間に、直径１０μｍ以上の空隙の発生があるも
のを不良とし、空隙が直径１０μｍ以下であれば良好と
した。 （耐電圧）２５℃で、上下回路間に、交流電圧を０Ｖか
ら、１００Ｖ／ｓｅｃで増加し、電流１ｍＡ以上流れた
ときの電圧とした。 （はんだ耐熱性）基板を、２６０℃のはんだ浴に１８０
秒間浸漬し、膨れや剥がれの発生しないものを良好とし
た。Here, the evaluation criteria will be described. (Circuit Filling Property) Microscopic observation made defects in which voids having a diameter of 10 μm or more were generated between the lower layer circuit and the insulating adhesive material, and made good when the voids had a diameter of 10 μm or less. (Withstand voltage) At 25 ° C., the AC voltage was increased between 0 V and 100 V / sec between the upper and lower circuits, and the voltage when the current was 1 mA or more was used. (Soldering heat resistance) The substrate is placed in a solder bath at 260 ° C for 180
It was soaked for a second, and those that did not cause swelling or peeling were regarded as good.
【００２９】[0029]
【発明の効果】以上に説明したように、本発明によっ
て、回路充填性の向上と、層間接続用穴からの絶縁接着
材料の流動量低減の両立ができ、かつ層間接続の信頼性
に優れた多層配線板の製造法を提供することができる。As described above, according to the present invention, it is possible to improve the circuit filling property and reduce the flow rate of the insulating adhesive material from the hole for interlayer connection, and the reliability of the interlayer connection is excellent. A method for manufacturing a multilayer wiring board can be provided.
【図１】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
Claims (4)
で流動性を有する凹部充填材を印刷または塗布する工
程、その凹部充填材を乾燥し、ＡまたはＢステージに硬
化する工程、この上にシート状絶縁性接着材料を重ね、
加圧加熱して積層一体化する工程からなることを特徴と
する多層プリント配線板の製造方法。1. A step of printing or applying a recessed filling material having fluidity in the A or B stage on a recessed portion on a circuit board, a step of drying the recessed filling material and curing it in the A or B stage, and Overlay the sheet-shaped insulating adhesive material on
A method for manufacturing a multilayer printed wiring board, comprising a step of heating under pressure to integrate the layers.
リント配線板の製造方法。 （ａ）回路基板上の凹部に、ＡまたはＢステージで流動
性を有する凹部充填材を印刷または塗布する工程 （ｂ）凹部充填材を乾燥し、ＡまたはＢステージに硬化
する工程 （ｃ）回路基板上に、予め穴明けしたシート状絶縁接着
材料付き銅箔を回路と接着材料とが接するように重ね、
加圧加熱して積層一体化する工程 （ｄ）層間接続を含む回路形成を行う工程 （ｅ）必要に応じて前記工程（ａ）〜（ｄ）を繰り返し
多層化する工程2. A method for manufacturing a multilayer printed wiring board, comprising the following steps. (A) A step of printing or applying a recessed filler having fluidity in the A or B stage on the recessed part on the circuit board (b) A step of drying the recessed filler and curing it in the A or B stage (c) Circuit Pre-drilled copper foil with sheet-shaped insulating adhesive material on the substrate so that the circuit and the adhesive material are in contact,
Step of pressurizing and heating to integrate and laminate (d) Step of forming circuit including interlayer connection (e) Step of repeating steps (a) to (d) as required to form a multilayer
リント配線板の製造方法。 （ａ）回路基板上の凹部に、Ｂステージで流動性を有す
る凹部充填材を印刷または塗布する工程 （ｂ）凹部充填材を乾燥し、Ｂステージに硬化する工程 （ｃ）回路基板上に、ケミカルエッチングにより穴明け
可能なシート状絶縁接着材料付き銅箔を重ね、加圧加熱
して積層一体化する工程 （ｄ）回路形成を行う工程 （ｅ）回路をレジストとし、層間接続穴をケミカルエッ
チングにより形成し、層間接続を行う工程 （ｆ）必要に応じて前記工程（ａ）〜（ｅ）を繰り返し
多層化する工程3. A method of manufacturing a multilayer printed wiring board, comprising the following steps. (A) a step of printing or applying a recessed filling material having fluidity in the B stage on the recessed portion on the circuit board; (b) a step of drying the recessed portion filling material and curing it on the B stage; (c) a circuit board; Step of stacking copper foil with sheet-like insulating adhesive material that can be punched by chemical etching, and pressurizing and heating to integrate and laminate (d) Step of forming circuit (e) Using resist as circuit and chemical etching of interlayer connection hole And (f) repeating the above steps (a) to (e) to form a multilayer structure.
高熱伝導の無機フィラーを含むことを特徴とする請求項
１〜３のうちいずれかに記載の多層配線板の製造方法。4. A recess filling material and / or an insulating adhesive material,
The method for producing a multilayer wiring board according to claim 1, further comprising an inorganic filler having a high thermal conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1704894A JP4021501B2 (en) | 1994-02-14 | 1994-02-14 | Manufacturing method of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1704894A JP4021501B2 (en) | 1994-02-14 | 1994-02-14 | Manufacturing method of multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07226583A true JPH07226583A (en) | 1995-08-22 |
| JP4021501B2 JP4021501B2 (en) | 2007-12-12 |
Family
ID=11933115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1704894A Expired - Fee Related JP4021501B2 (en) | 1994-02-14 | 1994-02-14 | Manufacturing method of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4021501B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0804061A1 (en) * | 1995-11-10 | 1997-10-29 | Ibiden Co, Ltd. | Multilayered printed wiring board and its manufacture |
| JP2007096185A (en) * | 2005-09-30 | 2007-04-12 | Sanyo Electric Co Ltd | Circuit board |
-
1994
- 1994-02-14 JP JP1704894A patent/JP4021501B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0804061A1 (en) * | 1995-11-10 | 1997-10-29 | Ibiden Co, Ltd. | Multilayered printed wiring board and its manufacture |
| EP0804061A4 (en) * | 1995-11-10 | 2000-01-05 | Ibiden Co Ltd | Multilayered printed wiring board and its manufacture |
| JP2007096185A (en) * | 2005-09-30 | 2007-04-12 | Sanyo Electric Co Ltd | Circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4021501B2 (en) | 2007-12-12 |
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