JPH0637740A - Bit buffer circuit - Google Patents

Abstract

PURPOSE:To prevent a circuit from being large by devising the circuit such that a slip takes place only at a location allowed by a frame format and the frame format is unchanged. CONSTITUTION:An address load signal generating means (36-38) generates an address load signal commanding loading of an optimum read address from an enable signal at a prescribed location. Slip discrimination means (30, 31) discriminates the presence of a slip representing missing or duplicate data based on a phase difference between output data of an expansion section and the read address. A read address generating section (32) receives a prescribed address by an address load signal from an address load signal generating means when the presence of the slip of the slip discrimination means is discriminated and generates the read address synchronously with a clock signal in the device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit buffer circuit, and more particularly to a bit buffer circuit used in a synchronous terminal device.

Generally, the clock extracted from the data transmitted through the transmission line contains jitter and wander and is not synchronized with the clock in the synchronous terminal device. For this reason, a bit buffer circuit is used to synchronize the transmission data with the clock in the device. However, slippage may occur due to the phase difference between the clock of the transmission data and the clock in the device, resulting in data loss or duplication. .

For this reason, when transmitting data, it is necessary to control such that there is no loss or duplication in the valid portion of the data, and there is a loss or duplication in the invalid portion of the data. It should be noted that when transmitting voice such as a telephone, the effective portion is data of the voice itself, and the invalid portion is device control data such as parity data.

[0004]

2. Description of the Related Art FIG. 4 is a block diagram showing an example of a conventional data buffer circuit. In the figure, a terminal 10 receives an enable signal for indicating each bit of the transmitted data, that is, pre-transfer data and an effective portion of the pre-transfer data at H level, and a terminal 11 for writing extracted from the pre-transfer data. A clock comes in, and the enable signal comes in at the terminal 12. The data and the enable signal from the terminal 10 are latched by the flip-flop 13 in synchronization with the write clock and supplied to the selection unit 14.

The rising edge detection section 15 detects the rising edge of the enable signal in synchronization with the write clock, and the rising edge detection signal causes the write address generation section 1 to operate.
6 is reset. After the reset, the write address generator 16 counts the write clock and generates the write address. The expansion unit 14 is composed of three registers, and the write address indicates the address of each of these three registers. By this write address, the pre-transfer data and the enable signal are sequentially written and expanded in the three registers of the expanding unit 14, and the contents of each of the three registers are supplied to the selector 20 in parallel.

The rising edge detection signal output from the rising edge detecting section 15 is latched by the flip-flop 21 in synchronization with the internal clock of the device from the terminal 22, that is, the reading clock, and supplied to the reading address generating section 23 as a reset signal. . Read address generator 23
After reset, counts the read clock and generates the read address. The selection unit 20 selects the output designated by the read address from the three outputs of the expansion unit 14 and supplies the output to the flip-flop 24 to synchronize with the read clock so that each bit of the data after transfer and the enable signal are transferred. It is output from the terminal 25.

[0007]

[Problems to be Solved by the Invention] FIG.
The frame format defined in 708 is shown.

In the figure, one frame consists of 9 lines, and the first 3 bytes of each line are the overhead area of the invalid part, and the following 87 bytes are the actual data area of the valid part. Become. Therefore, the enable signal becomes H level in the L level effective part in the ineffective part of each row. The frame is transmitted in 8-bit parallel. Also, the actual data area excludes the overhead area,
It consists of an area of 783 bytes starting from the 274th byte of the 4th row of the frame and ending at the 270th byte of the next frame. The 273rd and 274th bytes of the 4th row are data for missing or duplication due to jitter correction. Is allowed.

When the above-mentioned CCITT, G708 format transmission data is supplied to the conventional circuit, there is a risk that the data format will be lost or duplicate slip will occur when the invalid portion of each row changes to the effective portion, and the frame format will change. is there. In order to prevent the change of the frame format, a format conversion circuit such as an elastic memory having a capacity for one frame is required, which causes a problem that the circuit scale becomes large.

The present invention has been made in view of the above points,
An object of the present invention is to provide a bit buffer circuit that prevents a slippage from occurring only at a position permitted by a frame format and does not change the frame format, thereby preventing an increase in circuit scale.

[0011]

SUMMARY OF THE INVENTION A bit buffer circuit of the present invention is a bit buffer circuit for synchronizing data transmitted in frame units with an enable signal indicating a valid portion and an invalid portion of a data string to a clock in a device. A write address generation unit that generates a write address that is synchronized with a write clock extracted from the transmission data; a development unit that writes and develops the transmission data according to the write address; and an enable signal at a predetermined position in the frame. Address load signal generating means for generating an address load signal for instructing the loading of the optimum read address at the central position of the invalid portion of the predetermined position, and data loss or duplication based on the phase difference between the output data of the expanding section and the read address. The slip that determines the presence or absence of slip And a read address generator that generates a read address in synchronization with the clock in the device when a predetermined address is loaded by the address load signal from the address load signal generator when the slip determining unit determines that there is a slip. A selecting unit for selecting and outputting the data expanded by the expanding unit according to the read address.

[0012]

According to the present invention, the address load signal is generated only at a predetermined position in the frame, and the read address is changed according to the address load signal in the state where the slip occurs, and the data is lost or duplicated. That is, the slip occurs only at a predetermined position in the frame, and the frame format does not change.

[0013]

1 shows a block diagram of an embodiment of the circuit of the present invention. In the figure, those parts which are the same as those corresponding parts in FIG. 4 are designated by the same reference numerals, and a description thereof will be omitted.

In FIG. 1, a write address generator 1
6 is not reset and counts a write clock to generate a write address.

The prohibited area setting section 30 has the first data output from the first register of the expanding section 14 shown in FIG.
The prohibited area signal shown in FIG. 2C indicating that the area is the prohibited area when it is supplied with the write clock shown in FIG. 2B and becomes H level in two clock cycles centering on the boundary of the first data. Is generated and supplied to the slip determination unit 31. If the time point at which the read address supplied from the read address generation unit 32, which will be described later, changes to a value instructing selection of the first data is the H level period of the prohibition region signal, the slip determination unit 31 loses or duplicates data. Assuming that a slip has occurred, an H level slip determination signal is generated and supplied to the gate circuit 39.

Further, the terminal 35 becomes L level only in the invalid portion of the fourth line of the frame format of FIG. 5 in the enable signal of the pre-transfer data. The enable signal shown in FIG. 3A is input, synchronized with the write clock from the terminal 11 shown in FIG. 3B by the flip-flop 36, and then supplied to the expansion unit 37. The expansion unit 37 is 3
The enable signal of the fourth row is sequentially written into a register composed of one register and designated by the write address from the write address generator 16, and the contents of each register are supplied to the optimum address load unit 38.

The optimum address load unit 38 indicates at H level the central position of the L level period of the second falling signal of the enable signals of the three systems from the expansion unit 37.
A system address load signal is generated and supplied to the gate circuit 39. For example, as shown in FIGS. 3C to 3E, when the enable signal falls in the order of the first, second, and third systems marked with an asterisk, FIG. 3 showing the central position of the enable signal of the second system. The address load signal of the second system shown in (L) is generated and output from the terminal 38b. The address load signals of the first and third systems hold the L level. Also, FIG.
When the enable signal falls in the order of the second, third, and first systems marked with an asterisk as shown in (F) to (H), the center position of the enable signal of the third system is shown in FIG. The third system address load signal shown is generated and output from the terminal 38c. The address load signals of the first and second systems are L
Hold the level. Further, as shown in FIGS. 3 (I) to (K), when the enable signals fall in the order of the starred third, third, and second systems, a diagram showing the central position of the first system enable signals. The first-system address load signal shown in FIG. 3 (L) is generated and output from the terminal 38a. The address load signals of the second and third systems hold the L level.

The gate circuit 39 reads the address load signals of the three systems supplied from the optimum address load unit 38 only when the H-level slip judgment signal is supplied from the slip judgment unit 31, and the load terminal 32 a of the address generation unit 32. , 32b, 32c, respectively. The read address generator 32 loads a read address for instructing selection of the first data when the address load signal of the first system supplied to the terminal 32a becomes H level, and similarly, each of the terminals 32b and 32c has the H level first signal. When the address load signals of the second and third systems are supplied, the read address for instructing selection of the second and third data is loaded, and then the read clock from the terminal 22 is counted up to generate the read address.

Therefore, a slip occurs only in the invalid portion of the fourth row of the frame, and there is no possibility that other data will be lost or duplicated by only missing or duplicating the data of 273 bytes and 274 bytes. The frame format does not change. Therefore, there is no need to provide a format conversion circuit, and it is possible to prevent the circuit scale from increasing.

Further, the slip resistance can be improved by increasing the number of registers in the expanding section 14 to 4 or more and correspondingly increasing the number of systems selected by the selecting section 20 to 4 or more.

[0021]

As described above, according to the bit buffer circuit of the present invention, the slip occurs only at the position permitted by the frame format, there is no change in the frame format, and it is possible to prevent the circuit scale from increasing. Extremely useful.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a circuit of the present invention.

FIG. 2 is a signal waveform diagram of the circuit of the present invention.

FIG. 3 is a signal waveform diagram of the circuit of the present invention.

FIG. 4 is a circuit diagram of a conventional circuit.

FIG. 5 is a diagram showing a frame format.

[Explanation of symbols]

 14, 37 Expansion unit 16 Write address generation unit 20 Selection unit 30 Prohibited area setting unit 31 Slip determination unit 32 Read address generation unit 38 Optimal address load unit 39 Gate circuit

Claims (3)

[Claims] 1. A bit buffer circuit for synchronizing data transmitted on a frame-by-frame basis with an enable signal indicating a valid portion and an invalid portion of a data string to a clock in a device, in synchronization with a write clock extracted from the transmitted data. A write address generating unit (16) for generating the write address, a developing unit (14) for writing and expanding the transmission data according to the write address, and an enable signal at a predetermined position in the frame to determine an invalid portion at the predetermined position. Address load signal generating means (36 to 38) for generating an address load signal for instructing the loading of the optimum read address at the central position, and data loss or duplication based on the phase difference between the output data of the expanding section and the read address. Slip determination means for determining the presence or absence of slip that occurs (30, 31) and a read address generating section which generates a read address in synchronization with the clock in the device when a predetermined address is loaded by the address load signal from the address load signal generating means when the slip determining means determines that there is a slip ( 32), and a selection unit (20) for selecting and outputting the data expanded by the expansion unit according to the read address, and a bit buffer circuit. 2. The bit buffer circuit according to claim 1, wherein a gate unit (39) extracts an address load signal from the address load signal generation circuit and supplies the address load signal to the address generation unit (32) by the slip determination means determining the presence of slip. 3. The bit buffer circuit according to claim 1, further comprising: 3. The expansion unit (14) is composed of three or more registers, according to claim 1 or 2.
The described bit buffer circuit.