JPH03101431A - Bit synchronization system - Google Patents

Abstract

PURPOSE:To stably reproduce a data by fetching an external input data with an internal clock even when there is any phase difference between the external clock and the internal clock to synchronize the external data with the internal clock. CONSTITUTION:An input data DATAIN(D0) is latched by a flip-flop (ESFF1) at a leading edge of a clock whose frequency is twice that of an external clock CK1 and generated from the clock CK1 and then outputted. It is the function of the bit synchronization circuit that the D0 data is formed into an output data (DATAOUT) synchronously with the internal clock (CK2) and the circuit is normally operated even when any phase difference exists between the clocks CK1 and CK2. Thus, the data is reproduced stably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a bit synchronization method for synchronizing data input to a communication path section of an exchange with an internal clock of a communication path device and regenerating a signal.

[Conventional technology]

In conventional exchange communication path devices, there is a method as disclosed in Japanese Patent Application Laid-Open No. 101595/1983 as a method of bit synchronizing signals input with different phases using an internal clock of the device.

The conventional bit synchronization method, which synchronizes an input signal synchronized with an external clock with an internal clock and reproduces the signal, has been replaced with a third method.
In FIG. 3, 1 is an external clock, 2 is an input data, 7 is an internal clock, and 10 is an output data. The right side of the 0-dot line indicates the internal clock, and the left side operates in synchronization with the external clock.

11 is a circuit that creates two-phase clocks 3 and 4 from external clock 1; 14 is a circuit that creates clock 8 which is obtained by dividing clock 7; and 12 and 13 are two-phase clocks 3 and 4.
15: a data latch circuit that receives input data 2 through 4;
16 shows a selector circuit that selects either signal 5 or 6 using clock 8.
This shows a data latch circuit that captures data.

In the case of this example, there is a problem that if the phases of the external clock 1 and the internal clock 7 reach a certain phase relationship, normal operation will not be possible. An example of this is shown in FIG. 5, where the numbers in FIG. 5 are the same as those in FIGS. 3 and 4. The phase relationship between external clock 1 and internal clock 7 is that of case internal clock 7.
From the shaded area to the shaded range 8 (T
It will work normally if the material is T2, but it will not work properly if it is other than Ti.

[Problem to be solved by the invention]

As shown in the prior art, no matter what phase difference there is between the external clock and the internal clock, stable operation is not achieved and there are limits to the phase relationship.

It is effective if the phase difference between the external clock and the internal clock can be defined, but if it cannot be defined, the signal may not be regenerated stably.

[Means to solve the problem]

The above purpose consists of a clock circuit that doubles the pulse width of an external clock signal, two data latch circuit flip-flops that alternately capture input data using the output of the clock circuit, and an AND condition between the output of the clock circuit and the internal clock signal. a flip-flop of the set/reset circuit which is set by this AND signal, and a flip-flop of the data selection circuit 1 which takes in the output of this flip-flop at the rising edge of the internal clock. The flip-flop of the data selection circuit 2 takes in the output of this flip-flop at the rising edge of the internal clock.

Also, a flip-flop that takes in the signal obtained by EXORing the outputs of the data selection circuits 1 and 2 at the falling edge of the internal clock and detects an error. This can be achieved by selecting a data latch circuit data with a data selection circuit, and then providing one flip-flop for retiming when an error is detected, and a synchronization circuit flip-flop that captures data at the falling edge of the internal clock. An AND condition is taken between a clock signal that doubles the pulse width of the external clock signal and the internal clock signal, and the flip-flop of the set/reset circuit set by this AND signal takes in data at the rising edge of the internal clock. The flip-flop of the data selection circuit 1 absorbs the phase difference between the external clock and the internal clock. Furthermore,
By taking in the output data of the data latch circuit selected by the flip of the data selection circuit 1 at the edge of the internal clock, output data synchronized with the internal clock can be obtained. Also, the outputs of data selection circuits 1 and 2 are EXORed.
When an L mismatch is detected, stable data can be reproduced by setting the clock used inside the bit synchronization circuit to a reverse phase clock.

〔Example〕

An embodiment of the present invention is shown in FIG. Toughlock in FIG. 1, DATAOUT indicates output data.

ESFFI・2 is a flip-flop in which input data is written alternately by the output of CKFFI. DATAFF is a flip-flop that outputs output data in synchronization with internal clock CK2, and CKFFl is external clock CKI.
A flip-flop that creates a clock twice as large as the . 5R
FF is a set-reset type flip-flop for absorbing the phase difference between the external clock CKI and the internal clock CK2.

CKFF2 is a flip-flop that generates a pulse synchronized with the rising edge of internal clock GK, and this output selects the output of ESFFI.2.

CKFF3 is a flip-flop that latches the output of CKFF2. ERRFF is the Q output of CKFF2 and CKF
If the Q outputs of F3 do not match, a flip-flop, RET, is used to select the reverse phase clock of internal clock CK2.
FF is a flip-flop for timing when an anti-phase clock is used.

Next, the operation will be explained with reference to FIG.

■DATAIN (Do) is generated by the rising edge of the clock ■ which is twice the CKI created from the CKI of ■.
It is latched into SFFI, and its output becomes ■. This Do data of ■ is synchronized with the internal clock CK2 (D
ATAOUT) is the function of the bit synchronization circuit. In this case, the example of the present invention operates normally even if there is any phase difference between the external clock and the internal clock. , 3/4 phase delay case 1,
The explanation will be divided into three parts: 2.3.

Case 1 is a case of 1/4 phase delay. The internal clock ■ and the clock ■ created from the external clock ■ are ANDed, and 5RFF is set by this output.
The output is ■. When this ■ signal is rHJ, CKFF2 is set at the next rising edge of internal clock GK, and its output [phase] becomes "H". At this time, ESF
Select FI output ■. This is ■. This ■ is taken in at the falling edge of the internal clock CK2■, and the DATA
The FF output becomes ■. This is output data synchronized with internal clock CK2.

Case 2. The same applies to case 3, and normal operation is possible. This means that even if there is a phase difference between the external clock and the internal clock, the internal clock GK is always synchronized with the external clock CK1 within 1/2T time of the clock ■.
Since it is in the "H" region of 5RFF, the output ■ of 5RFF rises within 172T time of clock ■, and this pulse width is T.
becomes. There is always a rising edge of the internal clock CK within the pulse @T of this 5RFF output ■, so C
The output [phase] of KFF2 rises in synchronization with the rise of CK, and its pulse width is also T. Due to this [phase], ESFF
The output ■ of I is selected and becomes the input ■ of DATAFF.

This data (■) is punched out at the falling edge of the internal clock CK2 (2), and its output becomes output data (2).

Case 3(b) with a 3/4 phase delay is the most efficient case and will be explained. In case 3, the clock of ■ is divided into two within the period T, and due to the difference in jitter and the operating sensitivity of the elements, 5R is generated in front of the pulse divided into two.
There is a possibility that FP cannot be set and data of ESFFI and 2 cannot be selected alternately. At this time, CKFF2
By EXORing the [phase] of CKFF3 with O of CKFF3, a mismatch (error) is detected, and the clock used inside the bit synchronization circuit is made to have the opposite phase. This results in the same state as a 2/4 phase delay. RETF the output of ESFFI, 2
By retiming using F and punching out at the falling edge of the internal clock GK2■, the output can be reproduced normally.

〔Effect of the invention〕

The present invention is capable of capturing input data from the outside using the internal clock and regenerating data in synchronization with the internal clock, regardless of the phase difference between the external clock and the internal clock, which has a very large effect.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 1 is an explanatory diagram of the operation, FIG. 3 is an explanatory diagram of the conventional example, FIG. 4 is an explanatory diagram of the operation of FIG. 3, and FIG. 5 is an explanatory diagram of problems in the conventional example. 1...External clock. 2...Input data. 7...Internal clock. 10... Output data. Akira 4 Prisoner P+2 Prisoner Akira 50

Claims (1)

[Claims] 1. In a circuit that synchronizes an external clock and external data synchronized with that clock with an internal clock in the device, a clock circuit that doubles the external clock and a two-phase clock of that clock circuit alternately transmit external data. A data latch circuit to take in, a set/reset circuit that takes an AND condition between the two-phase clock and the internal clock, and sets/resets it using this AND signal, and then takes in the output of the set/reset circuit at the rising edge of the internal clock. The output data of the data selection circuit and the data latch circuit is monitored by the data selection circuit, which latches data at the rising edge of the internal clock, and monitors the alternate operation of the synchronization circuit and the data selection circuit, and selects the internal clock. A bit synchronization method featuring an error detection circuit.