JPH0667996A - Velocity conversion circuit with erroneous operation detecting function - Google Patents

Abstract

PURPOSE:To provide a velocity conversion circuit capable of returning data reading/writing operations back to an initial state and letting a normal operation continue by detecting the generation of the competition of the writing and the reading on the same buffer to temporarily store input data concerning the velocity conversion circuit with an erroneous operation detecting function. CONSTITUTION:The velocity conversion circuit with an erroneous operation detecting function is composed of a buffer part 1 having plural buffers which temporarily stores inputted serial data, a writing selection part 2 selecting a buffer to write input data and writing input data into the buffer, a reading selection part 3 selecting a buffer to real out data written into the buffer and reading data from the buffer and a writing/reading competition detection circuit 4 detecting the generation of the competition of the writing and the reading on the same buffer and restoring the operation of the velocity conversion circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speed conversion circuit with a malfunction detection function, and more specifically, it detects the occurrence of competition between writing and reading in the same buffer for temporarily storing input data and restores the operation. Speed conversion circuit with malfunction detection function.

[0002]

2. Description of the Related Art Normally, a speed conversion circuit uses a FIFO circuit to write and read data at timings corresponding to synchronous clocks having different speeds. Further, the operations of the write clock and the read clock are monitored so that an error does not occur in the read data due to the occurrence of an abnormality in the write clock and the read clock.

Generally, a plurality of buffers for temporarily storing input data for speed conversion are prepared, and control is performed so that timings of writing and reading do not occur in the same buffer. This is because when the timing of writing and reading occurs in the same buffer,
This is because there is a possibility that normal data cannot be read.

FIG. 5 shows a block diagram of a conventional configuration. The buffer unit 51 temporarily stores input data and is generally composed of a plurality of buffers. Here, the buffer unit 51 is composed of four buffers A, B, C and D. Input data is written in the buffer selected by the write selection unit 54 and stored in the buffer selected by the read selection unit 55. Data is read and output.

The write control section 52 is a section for generating a write timing signal indicating the timing of starting writing in the buffer by a write clock and a write control signal indicating the beginning of the input data. The read control unit 53 is a unit that generates a read timing signal that indicates the timing of starting reading from the buffer in response to the read clock and the read control signal that indicates the beginning of the output data.

The buffer shift control unit 54 selects a buffer to be written by using the write timing signal, generates a buffer write signal designating a writing period, and selects a buffer to be read by using the read timing signal. This is a part for generating a buffer read signal that specifies a period for reading.

The write selection section 55 utilizes the buffer write signal input from the buffer shift section to sequentially select the buffer in which the input data should be written and write the data. The read selection unit 56 uses the buffer read signal input from the buffer shift unit to sequentially select the buffer from which the input data should be read and read the data.

The write clock monitoring unit 57 monitors a counter or the like that the write clock and the write control signal are generated in a regular number during a fixed period and there is no gap, and thereby a malfunction of the clock serving as a reference for writing is detected. This is detected and the buffer shift control unit 54 is notified of the abnormality.

The read clock monitoring unit 58 monitors a counter or the like that a normal number of read clocks and read control signals are generated during a fixed period and that there is no gap, and thus a malfunction of the clock that is the reference for reading is detected. This is detected and the buffer shift control unit 54 is notified of the abnormality.

FIG. 6 shows a time chart for writing and reading data in the related art. The data input here is 8-bit serial data (D1 to D8),
The write timing signal W8K is a signal indicating the beginning of the input data, and the read timing signal R8K is a signal indicating the beginning of the output data.

FIG. 7 and FIG. 8 are time charts for detecting a timing difference between writing and reading and returning to a normal state in the conventional example. In this conventional example, the initial state in the normal case is set (buffer A: write, buffer C: read).
And write at buffer A → B → C → D at regular intervals.
It is assumed that the buffer shift control unit 54 controls so as to cycle through → A and read through buffers C → D → A → B → C, so that the same write and read operations do not simultaneously access the same buffer. .

Further, in order to detect a malfunction before the write and read operations are performed on the same buffer,
For example, the buffer A and the buffer D are monitored, and when an abnormal state in which the buffer A and the buffer D are simultaneously accessed is detected, the writing or reading operation with respect to the buffer D is performed twice in succession. Then, the shift of access to the buffer is returned to the normal state.

In FIG. 7, when data is being written in the buffer D and a state in which data is being simultaneously read in the buffer A is detected, the data is written and written in the buffer D twice. The buffer shift control unit 54 controls the timing so that the buffer A is in a normal state where the buffer A reads and the buffer C writes at the next timing.

In FIG. 8, data is written in the buffer A.
If it is detected that the data is read in the buffer D at the same time while the data is being read in, the buffer D is detected.
The buffer shift control unit 54 controls so that the data is read twice, the read timing is shifted, and at the next timing, the buffer C reads the data and the buffer A writes the normal state.

As described above, in the prior art, in the serial data speed conversion circuit, the timing difference between the writing and reading is detected before the timing of writing and reading with respect to the same buffer occurs, and a certain specific buffer is detected. By writing to or reading from twice,
I am trying to return to a normal state.

Further, the write clock monitor 57 and the read clock monitor 58 monitor the malfunction of the clock which is the reference of the operation, and when an abnormality of the clock is detected,
The operation of the buffer shift control unit 54 is initialized.

[0017]

However, in the above-mentioned conventional example, there is a possibility that timing may occur such that writing and reading are simultaneously performed on the same buffer due to jitter or noise. Therefore, even if an attempt is made to prevent the timing at which writing and reading operations are performed on the same buffer by using conventional monitoring, unpredictable jitter and noise may occur, so writing and reading operations may be completed completely. It is difficult to prevent access to the same buffer. Further, in order to detect and prevent malfunction of the write and read clocks, a complicated circuit in which a counter or the like is combined is required, which leads to an increase in cost.

The present invention has been made in consideration of the above circumstances, and detects the occurrence of contention between writing and reading in the same buffer, thereby making the data reading and writing operations into the initial state. It is intended to provide a speed conversion circuit with a malfunction detection function capable of continuing a normal return operation.

[0019]

FIG. 1 shows a block diagram of the configuration of the present invention. As shown in FIG.
In a speed conversion circuit for converting the transfer rate of serial data, a buffer section 1 having a plurality of buffers for temporarily storing input data, a buffer for writing the input data, and a write selection for writing the input data in the buffer are selected. Part 2
And a read selection unit 3 for selecting a buffer for reading the data written in the buffer and reading the data from the buffer.
And a speed conversion circuit with a malfunction detection function, which comprises a write / read conflict detection unit 4 for recovering the operation of the read speed conversion circuit when a conflict between writing and reading in the same buffer has occurred.

Further, in FIG. 1, the write / read conflict detector 4 generates a write timing signal indicating the timing of starting writing in the buffer by the write clock and the write control signal indicating the beginning of the input data. , A read control unit 7 for generating a read timing signal indicating the timing of starting reading from the buffer by a read clock and a read control signal indicating the beginning of the output data.
And a buffer for specifying a period for writing by selecting a buffer to be written by using a write timing signal, and a buffer for specifying a period for reading and selecting a buffer for reading by using a read timing signal A buffer shift control unit 5 for generating a read signal, and a same buffer access detection unit 9 for detecting a simultaneous writing and reading in the same buffer and generating a malfunction detection signal.
A speed conversion circuit with a malfunction detection function is provided, which includes a malfunction recovery signal and a motion recovery unit 8 that recovers the speed conversion circuit by eliminating the conflict between writing and reading in the same buffer.

In the parallel data speed conversion circuit, the speed conversion circuit with the malfunction detection function is connected to each bit of the parallel data to form the speed conversion circuit with the malfunction detection function for parallel data. Good.

[0022]

According to the present invention, the same buffer access detection section 9 in the write / read contention detection section 4 detects the occurrence of contention between writing and reading in the same buffer, and restores operation based on this detection signal. Since the unit 8 is designed to restore the operation of the speed conversion circuit, even if the write clock or the read clock malfunctions and a write / read conflict occurs in the same buffer, the data read and write operations are initialized. It is possible to return to the state and continue normal operation.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the embodiments shown in the drawings. The present invention is not limited to this. 2 and 3 show a circuit of a portion corresponding to the configuration block diagram of FIG. 1 in the speed conversion circuit in the embodiment of the present invention.

In FIG. 2, reference numeral 21 denotes a buffer section,
It is a part which consists of four buffers and temporarily stores the input 8-bit data. Reference numeral 22 denotes a write selection unit, which is a portion for selecting a buffer to write input data from among four buffers and writing the input data to the buffer. Reference numeral 23 is a read selection unit, which selects a buffer from which data should be read out from the four buffers,
This is the part that reads data from the buffer and outputs it.

In FIG. 3, reference numeral 31 is a write control section, which is a section for generating a write timing signal indicating the timing of starting writing in the buffer by the write clock WCK and the write control signal WR indicating the beginning of the input data. The write timing signal is generated after the WR is delayed by the number of input data bits by the bit shift register to confirm the write data.

Reference numeral 32 denotes a read control unit, which is a read control signal RR indicating the read clock RCK and the beginning of output data.
Is a portion for generating a read timing signal indicating the start timing of reading from the buffer, and the read timing signal is generated when the output data is read.

Numeral 33 is a buffer shift control unit, which uses the write timing signal input from the write control unit 31 to select a buffer to be written and to specify a write period (WA1 to WA4). ) Is generated, and a read timing signal input from the read control unit 32 is used,
And a read shift control unit 332 for generating buffer read signals (RA1 to RA4) for selecting a buffer to be read and designating a reading period.

Reference numeral 34 designates the same buffer access detection section, which is a section for detecting that writing and reading to the same buffer occur at the same time, and for generating a malfunction detection signal notifying that a malfunction of the buffer access has occurred.

Reference numeral 35 is an operation restoration unit, which is a portion for resolving the speed conversion circuit by using the malfunction detection signal from the same buffer access detection unit 34 to eliminate the conflict between writing and reading in the same buffer.

The same buffer access detection section 34 and the operation recovery section 35 are the characteristic parts in the configuration of the present invention, and are provided in the case of a write and read operation or a malfunction in which the same register is simultaneously operated. , Is a part for returning the data write and read operations in the speed conversion circuit to the initial state and performing normal operation.

The operation of the embodiment of the present invention will be described with reference to FIGS. 2, 3 and 4. First, the normal operation will be described. In this example, at the time of initial setting, the write buffer is set to the buffer A and the read buffer is set to the buffer C.

At this time, the buffer shift control unit 33 outputs the "H" level to WA1 as the buffer write signal only for the 8-bit period of the input data. In addition, the "H" level is output to RA3 as a buffer read signal only during the 8-bit period of output data. Other WA2, WA3
WA4, RA1, RA2 and RA4 remain at "L" level.

In response to the buffer write signal WA1, the write selection unit 22 uses the buffer A as a write buffer.
Is selected, and the input data is written in the buffer A during the "H" level period of WA1. Buffer read signal R
By A3, the buffer C is selected as a read buffer in the read selection unit 23, and the output data is read from the buffer C during the "H" level period of RA3.

Next, when the writing of the input data to the buffer A is completed, the "H" level is output to the buffer write signal WA2 so as to write the data to the buffer B. When the reading from the buffer C is completed, the buffer D
The "H" level is output to the buffer read signal RA4 so that the data is read from. In the buffer write signals WA1 to WA4, two or more buffer write signals do not become “H” level at the same time, and in the buffer read signals RA1 to RA4, two or more buffer read signals at the same time “H” level. It is controlled not to become.

In this way, the write buffer is changed from A → B → C.
→ D → A cycle, read buffer C → D → A → B →
By circulating with C, the buffer shift control unit 33 controls so that write and read accesses are not performed to the same buffer or adjacent buffers (for example, A and B, A and D, B and C, etc.). Then, the write and read operations are repeated.

Next, an example in the case of a write / read malfunction will be described. In FIG. 3, the buffer shift control unit 33 monitors the buffer A and the buffer D, and when the write or read access to the buffer A and the buffer D is performed at the same timing, the continuous read of the buffer D or the buffer D is performed. Control is performed so that D is continuously written.

For example, when data is written to buffer D, that is, when buffer write signal WA4 indicates "H" level, when data is read from buffer A, that is, buffer read signal RA.
When 1 indicates "H" level, AND1 element and OR
One element controls the writing to the buffer D again. As a result, during the second writing to the buffer D, the buffer B is read and normal operation can be restored.

Similarly, when the data is read from the buffer D and the data is written to the buffer A at the same timing, RA4 and WA1 both indicate the "H" level, and the AND2 element and the OR2 element cause the buffer D to change from the buffer D. Is controlled to be read again. As a result, writing to the buffer B is performed during the second reading from the buffer D, and normal operation can be restored.

An example of the above malfunction is a case where the adjacent buffers A and D are accessed for writing and reading, but this malfunction preventing method is also realized by the configuration shown in the prior art. It is what is done.

Next, description will be given of the case of a malfunction in which writing and reading are performed at the same timing with respect to the same buffer, which is a feature of the present invention. In the embodiment shown in FIG. 3, the same buffer access detection unit 34 monitors the simultaneous write and read accesses to the buffer C.

FIG. 4 shows the same buffer access detection unit 34.
Shows a time chart of. In FIGS. 3 and 4, W
A3 is a buffer write signal of the buffer C, and RA3
Is a buffer read signal of the buffer C.

When simultaneous write and read access to the buffer C occurs, both WA3 and RA3 indicate "H" level, and at this time, the write control signal WR shifted by the 4-bit shift register is clocked in. The flip-flop FF1 that outputs "H" level.

After that, the flip-flops FF2 and NAN
The D element NA1 outputs an "L" level malfunction detection signal A indicating that the same buffer access has occurred.

The operation recovery section 35 receives XRST which is a reset signal for the entire speed conversion circuit and the malfunction detection signal A which is an input signal from the same register access detection section 34, and one of XRST and A is set to "L". When it becomes "level", it outputs "L" level, and sets each flip-flop of the buffer shift control unit 33 to the initial state. After that, according to the normal operation, data read and write operations are performed.

In the above embodiment, the serial data is handled as the target of the data for speed conversion.
The speed conversion circuit with the malfunction detection function can also be applied to speed conversion of parallel data.

That is, the parallel data is decomposed into each bit, the speed conversion circuit with the malfunction detection function shown in the embodiment is connected to each bit to convert the speed, and the speed converted data is converted into each bit. Are synchronized and combined into one parallel data.

[0047]

According to the present invention, the same buffer access detection unit 9 detects that a conflict between writing and reading in the same buffer has occurred, and the operation restoration unit 8 causes the speed conversion circuit to detect the contention based on this detection signal. Even if the write clock or read clock malfunctions and write / read conflicts occur in the same buffer, the data read and write operations are returned to the initial state and normal operation is performed. Can be continued.

Further, it is not necessary to add a complicated circuit for constantly monitoring the write and read clocks and detecting a malfunction so that the conflict between the write and the read in the same buffer does not occur, and the cost increase can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a partial view-1 of the speed conversion circuit in the embodiment.

FIG. 3 is a partial view-2 of the speed conversion circuit in the embodiment.

FIG. 4 is a time chart of the same buffer access detection unit in the embodiment.

FIG. 5 is a block diagram showing a conventional configuration.

FIG. 6 is a time chart of writing / reading in a conventional example.

FIG. 7 is a time chart-1 when a malfunction occurs in the conventional example.

FIG. 8 is a time chart-2 when a malfunction occurs in the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 buffer section 2 write selection section 3 read selection section 4 write / read conflict detection section 5 buffer shift control section 6 write control section 7 read control section 8 operation recovery section 9 same buffer access detection section

Claims (2)

[Claims] 1. A speed conversion circuit with a malfunction detection function for converting a transfer rate of serial data, wherein a buffer section (1) having a plurality of buffers for temporarily storing input data and a buffer for writing the input data are selected. And a write selection unit (2) for writing input data to the buffer, and a read selection unit (3) for selecting a buffer for reading the data written in the buffer and reading the data from the buffer.
A speed conversion circuit with a malfunction detection function comprising a write / read conflict detection unit (4) that detects the occurrence of competition between writing and reading in the same buffer and restores the operation of the speed conversion circuit. 2. A write control unit (6) for generating a write timing signal indicating a write start timing in a buffer by a write / read conflict detection unit (4) according to a write clock and a write control signal indicating the beginning of input data. , A read control section (7) for generating a read timing signal indicating a start timing of reading from the buffer by a read clock and a read control signal indicating the beginning of output data, and selecting a buffer to be written by using the write timing signal And a buffer shift control unit (5) that generates a buffer write signal that specifies a write period, selects a buffer to be read by using a read timing signal, and generates a buffer read signal that specifies a read period. Generates a malfunction detection signal by detecting that writing and reading to the buffer occur simultaneously The same buffer access detection unit (9) and an operation restoration unit (8) for restoring the speed conversion circuit by using the malfunction detection signal to resolve the conflict between writing and reading in the same buffer. Speed conversion circuit with malfunction detection function.