JPH0554289A - Alarm signal detecting circuit - Google Patents

Abstract

PURPOSE:To flexibly cope with all reset and set values without changing a circuit scale as to an alarm signal detecting circuit which detects an alarm signal. CONSTITUTION:This circuit is provided with a differentiating circuit 1 which differentiates a leading edge in each cycle of a timing signal, a counter part 2 which counts input data by using the output of the differentiating circuit 1 as a reset signal, a comparison part 3 which compares the counting result of the counter part 2 with detection set and resetting set values and judges whether the detection and resetting of the alarm signal in the input data are required or not, and a latch part 4 stored with the judgement result outputted by the comparison part 3; and the detection set values and resetting set values are varied to optionally set the detection and resetting conditions of the alarm signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm signal detecting circuit for detecting an alarm signal. In recent years, with the development of transmission systems, downsizing / downsizing of systems and flexibility have been required. Therefore, although an alarm signal detection circuit using a flip-flop is provided, the alarm signal (hereinafter referred to as AIS) detection / cancellation set value becomes a fixed value, and depending on the set value, it becomes a large-scale circuit. Therefore, an alarm signal detection circuit that can flexibly deal with the miniaturization and miniaturization of the circuit scale is required.

[0002]

2. Description of the Related Art A conventional embodiment will be described below with reference to FIGS. FIG. 4 is a circuit and FIG. 5 is a time chart.

In FIG. 4, reference numeral 21 is a differentiating circuit which outputs a reset signal (b) obtained by differentiating the rising edge of the timing signal (a). 22 is A only when the input data (c) is "1" over one cycle T of the timing signal (a).
An AIS detection unit that detects IS and latches the detection result at the rising edge of the timing signal (a), and 23 is input data (c) twice during one cycle T of the timing signal (a). The above is an AIS canceling unit that cancels AIS when "0" comes and latches the detection result at the rising edge of the timing signal.

Further, 24 is an AND for obtaining a logical product of two inputs
A gate, 25 is a latch unit for latching the output of the AND gate 24 with a timing signal. FIG. 5 is the same as the signal described in the circuit of FIG. 4, (a) is a timing signal, (b)
Is a reset signal output from the differentiation circuit 21, (c) is input data, (d) is a signal output from the AIS detection unit 22,
(e) is a signal output from the AIS canceling unit 23. or,
(f) is an alarm signal (AIS) output from the latch unit 25.

In FIG. 4 and FIG. 5, when the timing signal (a) having a certain fixed period T is input to the differentiating circuit 21, the differentiating circuit 21 raises the timing signal (a) at time t = 0. The reset signal (b) obtained by the differentiation is set to '1' in addition to the AIS detector 22 and the AIS canceler 23.

Now, the state of the data (c) is indefinite until the timing. In the period A of the timing signal (a), if there is one "0" in the data (c) during one cycle, A
The IS detector 22 detects the rising edge of the data (c) from "0" to "1", and the output (d) of the detection result continues to be "0" for the rest of one cycle. On the other hand, the output (e) of the AIS canceling unit 23 remains "1" because the data (c) is "0" once, and the output of the AND gate 24 is the next reset signal (b). The previous state of "0" is continued until the timing. Therefore, the signal (f) output from the latch unit 25 at the timing becomes “no AIS detection”.

In the period B of the timing signal (b), 1
If the data (c) between cycles is all '1', the data
Since there is no change from "0" to "1" in (c), the output (e) of the AIS detection unit 22 and the AIS cancellation unit 23 remains "1", and the output of the AND gate 24 is reset next. It keeps '1' until the signal (b) is output. Therefore,
The signal (f) output from the latch unit 25 at the timing becomes “AIS detection”.

Further, in the period C of the timing signal (b), when the data "c" is "0" more than once in one cycle, the data "c" is read from the first "0" to "1". AIS detection unit 22 detects the rising edge to and the signal (d) is set to "0".
Also, from the second time onward for data (c), it is from "0" to "1".
Is detected by the AIS cancellation unit 23 and the signal
Set (e) to "0". Therefore, the output of the AND gate 24 continues to be "0" from the rising of the data (c) to the timing when the next reset signal (b) is output. Therefore, at the timing, the latch section 25 becomes "AIS release".

[0009]

Therefore, when the detection / release setting is fixed as in the conventional circuit, the AIS is used.
The circuit scale increases as the release set value increases, and the release set value is also determined from the circuit scale, so that there is a problem that it is not possible to flexibly deal with all release set values.

It is an object of the present invention to provide a circuit which can flexibly deal with any release setting value without changing the circuit scale.

[0011]

In order to achieve the above object, the present invention uses a differentiating circuit 1 for differentiating a rising edge of a timing signal for each cycle and an output from the differentiating circuit 1 as a reset signal. The counter unit 2 that counts the number of input data is compared with the count result of the counter unit 2 and the detection set value / release set value to determine whether it is necessary to detect or release the alarm signal in the input data. And a latch unit 4 for storing the judgment result output by the comparison unit 3 are provided, and the detection / cancellation condition of the alarm signal is arbitrarily set by varying the detection set value / cancellation set value. Configure so that you can.

[0012]

According to the present invention, as shown in FIG. 1, a differentiating circuit 1 sends a reset signal for each cycle of a timing signal, and the counter section 2 counts the number of data in one cycle by the reset signal. The comparator 3 compares the count value output by the counter 2 with the detection setting value / release setting value to determine whether to detect or release the alarm signal.

Therefore, if the judgment result of the comparison section 3 is stored in the latch section 4 and then sent out as an alarm signal, the detection set value and the release set value can be changed so that the alarm signal detection / release condition can be changed. It can be set arbitrarily.

[0014]

Embodiments of the present invention will be described below with reference to FIGS. 2 is a circuit and FIG. 3 is a time chart.

In FIG. 2, 11 is a differentiating circuit, 12 is a binary counter, 13 is a first comparator, and 14 is a second comparator. or,
Reference numeral 15 is an AND gate, 16 is an OR gate, and 17 is a latch unit. FIG. 3 shows signals of each circuit of FIG. 2, where (a) is a clock, (b) is a timing signal, (c) is a reset signal output from the differentiating circuit 11, and (d) is data. Also, (e) is 12
The count value of the decimal counter 12, (f) is AIS.

As shown in FIGS. 2 and 3, the differentiating circuit 11 outputs a reset signal (c) of one clock (a) width with a negative polarity by differentiating the rising edge of the timing signal (b).
Further, a reset signal (c) from the differentiating circuit 11 which enables the data (d) is applied to the binary counter 12 of the clock (a).

The 12-decimal counter 12 is cleared by the reset signal (c), and counts up sequentially from "0" as shown in the signal (e). If the data (d) is "1",
The decimal counter 12 is enabled and counts up, but when "0" comes to data (d), it is disabled and does not count up, and the count is incremented by "0" (m).

Count value (e) that comes from the 12-decimal count 12
Are input to the first comparator 13 and the second comparator 14, respectively.
The first comparator 13 compares the detected setting value'B 'with the data.
When the number of "0" s in (d) is 0, the count is increased to "B" and "H" is output. On the other hand, when the number of "0" s in the data (d) is one or more, it is counted up to "A"("B-1") or "A or less" and "L" is output.

Further, the second comparator 14 compares it with the release set value "9", and when the number of "0" in the data (d) is 0 to 1, it is counted up to "9" and "H". 'Is output. On the other hand, when the number of "0" s in the data (d) is two or more, the count up to "9" and "L" is output.

The AND gate 15 takes the logical product of the output of the second comparator 14 and AIS (f) fed back from the latch section 17. Therefore, the logic of the output of the OR gate 16 is
If the number of '0's in (d) is 0 to 1 time, it is'H', and if '0' is 2 or more times in data (d), it is'L '. Therefore, in the latch unit 17, the number of “0” s in the data (d) is 0.
If the number of times is'AIS detection 'at the timing, data (d)
If the number of '0' is 1, the timing is'AI
When the number of “0” in the data “d” is more than twice, “AIS is released” at the timing.

[0021]

As is apparent from the above description, according to the present invention, it is possible to arbitrarily set the alarm signal detection / cancellation conditions, thus contributing to the miniaturization and miniaturization of the circuit scale and universality. The effect of doing.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a circuit of an embodiment of the present invention.

FIG. 3 is a diagram showing a time chart of a circuit according to an embodiment of the present invention.

FIG. 4 is a diagram showing a circuit of a conventional example.

FIG. 5 is a diagram showing a time chart of a conventional example circuit.

[Explanation of symbols]

 1 is a differentiation circuit 2 is a counter unit 3 is a comparison unit 4 is a latch unit

Claims (1)

[Claims] 1. A differentiating circuit (1) for differentiating a rising edge of a timing signal in each cycle and an output from the differentiating circuit (1) is used as a reset signal,
The counter unit (2) that counts the number of input data is compared with the count result of the counter unit (2) and the detection set value / release set value to detect and release the alarm signal in the input data. A comparison unit (3) that determines whether or not it is necessary, and a latch unit that stores the determination result output by the comparison unit (3)
(4) The alarm signal detection circuit according to claim 4, wherein the alarm signal detection / cancellation condition can be arbitrarily set by varying the detection setting value / cancellation setting value.