JPH02189026A - Detector for overflow and underflow of counter - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by having only to supervise the state of two bits being a sign bit and the most significant bit(MSB) of a count of a counter to detect overflow and underflow of the counter. CONSTITUTION:With a pulse signal 2 fed to a counter 1, a count 4 is incremented by 1 to be '1000' and both a sign bit 10 and the MSB 11 are changed. Since level '0' of the sign bit 10 before the change and level '1' of the sign bit 10 after the change are applied to an exclusive OR gate 13 in this case, its output is inverted to a level 1. Since two inputs '10' after the change are fed to an exclusive OR gate 14, its output goes to the level '1'. Thus, a detection signal of level 1 being the result of detecting overflow is outputted from an AND gate 15. Thus, the circuit constitution is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an overflow and underflow detection device for a counter that counts pulse signals.

[Conventional technology]

Figure 2 is “Basic Computers Revised Edition” (Jitsuzai Publishing, p.
74-75 (issued March 5, 1981) is a block diagram showing a conventional counter overflow and underflow detection device, in which 1 indicates 4, for example, which counts up or counts down an input pulse signal.
Bit counter, 2 is the pulse signal 1 counted up by counter 1, 3 is the pulse signal counted down by counter 1, 4 is the count value expressed by 4 bits of counter 1, 5 is the count value 4 of counter 1 and the above pulse signal 2 are added to the AND gate, and only the most significant sign bit of the count value 4 is added in negative logic. 6 is an AND gate to which the count value 4 of the counter 1 and the above-mentioned pulse signal 3 are added, and 3 bits of the count value 4 other than the sign bit are added in negative logic. 7 is an OR gate to which the output signals of AND gates 5 and 6 are added; 8 is an AND gate 5
．． An overflow/underflow detection device includes an overflow/underflow detection device 6 and an OR gate 7, and 9 is a detection signal output from the OR gate 7 for detecting an overflow/underflow.

Next, the operation will be explained. Counter 1 outputs a binary count value 4 according to the number of inputs of pulse signal 2.3, and when pulse signal 2 is added, count value 4 is incremented by 1, and pulse signal 3 is If added, the count value 4 is subtracted by "1". Here, since the count value 4 expresses both positive and negative characteristics by using its most significant bit as a sign bit, the detection device 8 uses the 4 bits of the count value 4 including the sign bit and the pulse signal 2 when detecting overflow and underflow. Alternatively, all the signals including the pulse signal 3 are inputted, the status is monitored, and overflow and underflow are detected by their combination logic. That is, in the detection device 8, the count value 4 is rollJ
(binary number), when the pulse signal 2 is applied, the AND gate 5 outputs a signal, and this signal is output through the OR gate 7 as an overflow detection signal 9. Further, when the count value 4 is in the state of rl 0OOJ (binary number), when the pulse signal 3 is added, the AND gate 6 outputs a signal, and this signal is transmitted to the OR gate 7.
The underflow detection signal 9 is outputted as an underflow detection signal 9.

[Problem to be solved by the invention]

Since the conventional counter overflow and underflow detection device is configured as described above, all the output bits of the count value 4 and the pulse signal 2.3 must be input, so the number of gates in the device is limited. increases in proportion to the output bit of count value 4, which causes problems such as a complicated circuit configuration and a corresponding increase in cost.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a counter overflow and underflow detection device that is not affected by the number of output bits of a count value.

[Means to solve the problem]

The counter overflow and underflow detection device according to the present invention monitors only the sign bit and MSB (most significant bit) of the count value, and can detect overflow and underflow by using changes in these states and combinatorial logic. That is.

(Operation) The counter overflow and underflow detection device of the present invention is configured to input the sign bit and MSB of a count value and detect that they have changed from mutually different states.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and their explanation will be omitted.

10 is the most significant sign bit of the 4-bit count value 4, and 11 is the next bit after the sign bit. Here, this bit is referred to as the most significant bit (hereinafter referred to as MSBII).

Reference numeral 12 denotes a storage means for storing the state of the sign bit 10 before it changes, and a flip-flop 12 is used in this embodiment. 13 is a first comparison circuit to which the output of the flip-flop 12 and the sign bit 10 are added; in this embodiment, an exclusive OR gate 13 is used. 14 is a second comparison circuit to which sign bit 10 and MSBII are added; in this embodiment, exclusive OR gate 14 is used. 15 is an AND circuit to which the outputs of exclusive OR gates 13 and 14 are added and outputs a detection signal 9; in this embodiment, AND gate 15 is used.

Next, the operation will be explained. The count value 4 of counter 1 is r
When in the state olllJ, its sign bit 10 r
□ is held by the flip-flop 12. Therefore, the two-man power of the exclusive OR gate 13 is "00", and its output is "O". Also exclusive or gate 14
The two-man power is "01", and the output is "1". Therefore, the output of the AND gate 15 is "0".

In this state, when pulse signal 2 is applied to counter 1, "1" is added to count value 4 to become "1000", and sign bit 10 and MSBII both change.

In this exclusive OR gate 13, the "0" of the sign bit 10 before the change and the "1" of the sign bit 10 after the change are added, so its output is inverted to "1". Furthermore, since the changed two-man power "10" is added to the exclusive OR gate 14, its output becomes "1". Therefore, the AND gate 15 outputs a detection signal of "1" indicating that an overflow has been detected.

Next, when the count value 4 of the counter 1 is in the state of rl 0OOJ, the output of the flip-flop 12 is "1". Therefore, the two-man power of Exclusive OR Gate 13 is “
11" and its output is "0". Also, the two-person power of exclusive OR gate 14 is "10", and its output is "1".
”. Therefore, the output of the AND gate 15 is "
0".

In this state, when pulse signal 3 is applied to counter 1, "1" is subtracted from count value 4, resulting in rollJ. Therefore, the two members of Exclusive OR Gate 13 and 14 are each riot.

The output changes to "01" and both outputs become "1". As a result, the AND gate 15 outputs a detection signal 9 that detects underflow.

〔Effect of the invention〕

As described above, according to the present invention, overflow and underflow of the counter are detected by only monitoring the sign bit and the MSB 2 bits of the count value of the counter, so that the circuit configuration is simplified. This has the effect of being simplified and making the device cheaper.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a counter overflow and underflow detection device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional counter overflow and underflow detection device. 1 is a counter, 2 is a pulse signal that is counted up,
3 is a pulse signal to be counted down, 4 is a count value, 8
is an overflow and underflow detection device, 9 is a detection signal, 1o is a sign bit in the count value, 11 is the MSB in the count value, 12 is a flip-flop for holding the sign bit,
13.14 is an exclusive or gate, 15 is an and gate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1

Claims (1)

[Claims] a storage means for storing a sign bit of a count value of a counter for counting pulse signals; a first comparator circuit to which the output of the storage means and the current sign bit of the count value are added;
Overflow and underflow of a counter comprising a second comparator circuit to which the current sign bit and the most significant bit of the count value are added, and an AND circuit to which the outputs of the first and second comparator circuits are added. Flow detection device.