JPH0530067A - Channel detector - Google Patents

Abstract

PURPOSE:To provide the channel detection device realized by a low-speed processing circuit without increasing the worst channel recovery time in a resolution part of a synchronization multiple converter of an electronic communication equipment. CONSTITUTION:A frame pattern detection circuit 11, frame synchronization detection/protection circuit 10, and a control circuit 12 controlling this are provided as low-speed synchronization parts 3, 4, 5, and 6. The immediate synchronization is realized by detecting the advancement of the channel phase from the frame pattern detection position or the frame specification position detected by each low-speed synchronization part 3, 4, 5, 6 by a phase decision circuit 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel detecting device provided in a disassembling unit of a synchronous multiplexing converter.

[0002]

2. Description of the Related Art In recent years, CCITT (International Telegraph
and Teleph-one Consultative Committee: The SDH (Synchronous Digital Hie
STM (Synchronous Transport Modul) based on rarchy
e: Synchronous multiplex transmission method) was recommended as a universal standard. In the conventional synchronous multiplex converter corresponding to this, (1)
The decomposing unit can be selected by either the method of performing synchronization detection and channel detection in the high-speed processing unit (serial signal processing unit), or (2) the method of performing synchronization detection and channel detection for each channel after dividing the signal into the number of channels. I am configuring.

FIG. 4 is a block diagram showing a structure of a conventional STM-N synchronous multiplex converter disassembling section, which is based on the method (1). As shown in FIG. 4, the conventional ST
The MN synchronous multiplex converter disassembling unit includes an STM-N frame synchronization detecting / protecting circuit 50, an N channel disassembling circuit 51, and a control circuit 52. Here, 53 is a serial STM-N signal and 54 is an STM-N frame synchronization detection /
Control signal for protection circuit 50, N channel decomposition circuit 55
Reference numeral 51 is a control signal, and reference numeral 56 is an initialization signal of the control circuit 52.

In this synchronous multiplex converter disassembling section, the input of the serial STM-N signal 53 is synchronously detected by the STM-N frame synchronous detection / protection circuit 50, and the control circuit 52 is issued by the initialization signal 56 based on this. Is initialized. The control circuit 52 is N
The timing for disassembling the channel disassembling circuit 51 is controlled by the control signal 55, and the serial STM-
The N signal 53 is decomposed into regular N channel (4 channels in FIG. 4) STM-1 signals 101, 102, 103, 104.

Here, the control circuit 52 outputs a control signal 54 to the STM-N frame synchronization detection / protection circuit 50 which is generated in a frame cycle. For this reason, the control circuit 52 requires a frame counter, which increases the circuit scale. Furthermore, the STM-N frame synchronization detection / protection circuit 50
When trying to detect a perfect frame pattern with, the circuit scale becomes large. These circuits are high-speed processing circuits of 600 MHz or higher, and the amount of heat generation increases as the circuit scale increases, causing problems in reliability and integration.

In order to reduce the circuit scale, the STM-N
There is a method of detecting a part of the frame pattern by the frame synchronization detection / protection circuit 50, but this causes erroneous synchronization when a false frame pattern occurs in the frame cycle.

As described above, in the method (1), the circuit scale of the high-speed processing circuit becomes large, so that the power consumption increases,
There is a drawback that the device becomes larger and the reliability is lowered due to heat generation. Further, if a part of the frame pattern is detected in order to reduce the circuit scale, it may cause erroneous synchronization.

FIG. 5 is a block diagram showing a structure of a conventional synchronous multiplex converter disassembling section, which is based on the method (2). As shown in FIG. 5, this STM-N synchronous multiplex converter disassembling unit includes a bit serial / parallel converting unit 60, a byte serial / parallel converting unit 61, a first low speed synchronizing unit 62, and a second low speed synchronizing unit. 63, a third low speed synchronization unit 64, and a fourth low speed synchronization unit
Each of the low-speed synchronization units 62, 63, 64, 65 includes a frame synchronization detection / protection circuit 66, a frame pattern detection circuit 67, a channel synchronization detection / protection circuit 68, and a channel phase shift calculation circuit 69. And a control circuit 70. Here, 71 is a serial STM-4 multiplexed signal, 72
Is an 8-bit parallel STM-4 multiplexed signal.

In this synchronous multiplex converter disassembling section, when the frame sync detection / protection circuit 66 outputs the out-of-frame signal 77, the frame pattern detection circuit 67 detects the frame pattern and initializes the control circuit 70. By outputting the signal 78 and the bit shift command 90, the frame synchronization is established. However, establishing frame synchronization does not necessarily lead to channel synchronization. Also, the STM identifier cannot be detected. Therefore, after the frame synchronization is established, the channel is detected by the STM identifier and the channel synchronization is established. Here, 101, 102, 103, 104 are STM-1 signals decomposed into correct channels.

As described above, according to the above method (2), the channel cannot be detected by the STM identifier until the synchronization is established by the synchronization detection. Therefore, the worst channel recovery time is τ + 1 frame (τ: worst frame synchronization time), which is longer than the worst frame synchronization time τ of the method (1).

Furthermore, channel detection is disabled when the STM identifier is not inserted.

[0012]

As described above, in the conventional synchronous multiplexing converter disassembling unit, it is difficult to reduce power consumption and miniaturize the device without using the STM identifier. is there.

The present invention solves the above problems, and an object of the present invention is to provide a channel detection device which can be realized by a low-speed processing circuit without increasing the worst channel recovery time in the disassembling unit of a synchronous multiplexing converter. It is what

[0014]

In order to solve the above problems, the present invention provides a low-speed synchronizing section having a frame pattern detection circuit, a frame synchronization detection / protection circuit, and a control circuit for controlling the same, in a channel for receiving signals. The number of frame phase detection amounts is determined by determining whether the frame pattern detection position or frame specific position detected by each low-speed synchronization section is missing or generated due to a false frame or a failure of the low-speed synchronization section. A channel phase determination circuit for estimating is provided.

[0015]

With the above construction, since the amount of advance of the channel phase is estimated by the channel phase determination circuit, it is possible to immediately establish the channel synchronization based on this.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a synchronous multiplexer / demultiplexer disassembling unit according to an embodiment of the present invention, which is for synchronously detecting a multiple signal called STM-4.

As shown in FIG. 1, the channel detecting device of the synchronous multiplex converter disassembling unit includes a bit serial-parallel converter 1, a byte serial-parallel converter 2, a first low-speed synchronization unit 3, and a second low-speed synchronization unit 3. In addition to the low speed synchronization unit 4, the third low speed synchronization unit 5, and the fourth low speed synchronization unit 6, a channel phase determination circuit 9 is provided. Here, 7 is a serial STM-4 multiplexed signal,
Reference numeral 8 is an 8-bit parallel STM-4 multiplexed signal.

Each of the low-speed synchronization units 3, 4, 5, 6 has a frame pattern detection circuit 10 for detecting a frame pattern having a bit shift, and a frame synchronization detection / detection for detecting a frame synchronization pattern to perform a synchronization / protection operation. A protection circuit 11, a control circuit 12 for controlling the operation of the frame cycle in the frame cycle detection / protection circuit, AND circuits 13, 14 and an OR circuit 15 are provided, respectively. The frame synchronization detection / protection circuit 11 can be generally composed of a contention counter.

In the channel phase determination circuit 9, the frame pattern detection positions or frame specific positions detected by the respective low speed synchronization units 3, 4, 5, 6 are the false frames or the low speed synchronization units 3, 4, 5, 6. The amount of advance of the channel phase is estimated by determining whether or not it is missing or generated due to a failure. As shown in FIG. 2, the channel phase determination circuit 9 includes a flip-flop 110 for delaying the frame position designation signal 41 by 1 clock and a flip-flop 11 for delaying the frame position designation signal 43 by 1 clock.
1 and a flip-flop 112 for delaying the frame position designation signal 45 by one clock, and a frame position designation signal
Philip flop 113 to delay 47 one clock
, A frame position determination circuit 114 for determining the frame position for the false frame pattern, and a channel determination circuit 115.
It consists of and.

The operation of the synchronous multiplex converter disassembling unit will be described below. First, the signal flow in the synchronous multiplex converter disassembling unit will be described. The serial STM-4 multiplexed signal 7 is converted into an 8-bit parallel STM-4 multiplexed signal 4 in the bit serial-parallel converter 1. Further, the 8-bit parallel STM-4 multiplexed signal 4 is divided into four 8-bit parallel STM-1 signals 20, 35, 36, 37 by the byte serial parallel conversion unit 2, and four low speed synchronization units 3, 4.
It is sent to 4,5,6. 8-bit parallel STM-1 signal divided into four by the byte-serial / parallel conversion unit 2, 35, 3
The STM-1 signal 20, which is one of 6,37, is input to the first low speed synchronizing section 3. Similarly, the other STM-1 signals 35, 36 and 37 are also input to the second low speed synchronizing unit 4, the third low speed synchronizing unit 5 and the fourth low speed synchronizing unit 6.

In the first low speed synchronizing section 3, the STM-1 signal 20
Is input to the frame pattern detection circuit 10 and the frame synchronization detection / protection circuit 11. Frame pattern detection circuit
The reference numeral 10 outputs a frame pattern detection signal 21 to the AND circuit 14 and the OR circuit 15 when detecting a frame pattern having a bit shift. At this time, the frame pattern detection circuit 10 outputs the bit advance value as the bit phase signal 22 to the AND circuit 13, and the AND circuit 13 detects that the frame synchronization detection / protection circuit 11 is out of frame synchronization (out of frame synchronization). When the signal 25 is at H level), the bit phase signal 22 is output as the bit shift instruction 40.

In the frame synchronization detection / protection circuit 11, when the synchronization is lost, the frame out-of-sync signal 25 is ANDed.
Output to 14. Further, the control circuit 12 detects the frame sync.
The control signal 23 is output to the protection circuit 11. In the control circuit 12, the frame synchronization detection / protection circuit 11 is out of frame synchronization (frame out of sync signal 25 is at H level).
In this case, when the frame pattern detection circuit 10 detects a pattern, it is initialized by the initialization signal 24 of the AND circuit 14.

A detailed description of the channel detection operation will be given below. First, consider a state in which the frame synchronization is pulled in (the frame synchronization loss signal 25 is at the L level).

Since the frame synchronization is pulled in, the control signal 23 of the control circuit 12 is output at the frame cycle and also indicates a specific position of the frame, here the head position. Therefore, the frame position designation signal 41, which is the output of the OR circuit 15, becomes the control signal 23 of the control circuit 12 in the state where the frame synchronization is pulled in, so that the frame position designation signal 41 indicates the head of the frame.

Now, the channel of the STM-4 multiplex signal 4 is 1
Assuming that the channel is advanced, as shown in FIG. 3, channel 4 (fourth low-speed synchronization unit 6), channel 1 (first low-speed synchronization unit 3), channel 2 (second low-speed synchronization unit 4), Signals 1, 2, ... In the order of channel 3 (third low-speed synchronizing section 5)
・ Will be sent. Assuming that the head of the frame is the signals 1 to 4, the frame position designation signal 41, the frame position designation signal 43, the frame position designation signal 45, and the frame position designation signal 47 are generated at the timings shown in FIG. Therefore, only the frame position designation signal 47 of the fourth low speed synchronization unit 6 is advanced by one clock with respect to the frame position designation signal 41 of the first low speed synchronization unit 3.

In the same way, when the channel is advanced by two channels, the frame position designation signal 41 of the first low-speed synchronization unit 3 and the frame position designation signal 45 of the third low-speed synchronization unit 5 are compared with the frame position designation signal 45 of the third low-speed synchronization unit 5. The frame position designation signal 47 of the low-speed synchronizing unit 6 of 4 is advanced by 1 clock. Further, when the channel is advanced by 3 channels, the frame position designation signal 41 of the second low-speed synchronization unit 4 and the frame position designation signal 43 of the second low-speed synchronization unit 4 and the third low-speed synchronization unit 5 are advanced. The frame position designation signal 45 and the frame position designation signal 47 of the fourth low-speed synchronizing section 6 are advanced by one clock.

The channel phase determination circuit 9 compares the frame position designation signal 41, the frame position designation signal 43, the frame position designation signal 45, and the frame position designation signal 47 with the frame position designation signal one clock before.

In general, the number of channels N is the number of medium channels x
When the frame position designation signal of is input to the frame position determination circuit 114, A = {(F-2p + 1) × (n / 2 ^np )} ^Nx (where F: frame length (word), p: frame synchronization) It is considered to be a regular frame pattern in which the frame position designation signal is missing due to a false frame with a probability of the pattern length (word) and the number of bits of n: 1 word).

On the other hand, a frame position designation signal by a false frame is generated with a probability of B = (N / 2 ^np ) ^x . When A> B, it is determined that the frame position designation signal is missing due to a false frame, that is, a normal frame pattern. At this time, x is x> N / 2. Therefore, in the case of the STM-4 multiplexed signal, the frame position determination circuit 114 inputs the inputs a and e.
, The logical sum of inputs b and f, the logical sum of inputs c and g,
The logical sums of the inputs d and h are respectively obtained, and when two of the four logical sums are output, it is determined as the frame position.

If the function of the frame position determination circuit 114 is written by a logical expression, (a + e) × (b + f) + (a + e) × (c
+ G) + (a + e) × (d + h) + (b + f) × (c +
g) + (b + f) × (d + h) + (c + g) × (d +
h). When the frame position determination circuit 114 determines that the position is the frame position, the frame position determination pulse 117 is output to the channel determination circuit 115. The channel determination circuit 115 determines the lead value of the channel phase. Generally, in the channel determination circuit 115, the x-th channel in the channel number N is
The logical product of the (x-1) th channel before the clock is calculated, and when this is true, it is determined that the channel phase advance is (N-x + 1). Also, the x-th channel or x-1
If a false frame occurs in any of the second channels, the phase advance of the channel cannot be determined. Therefore, the logical product of the x-th channel and the x-2th channel one clock before is also obtained, and when this value is true, the logical product of the x-th channel and the x-1th channel one clock before is false. However, it is determined that the channel phase is advanced by (N−x + 1) or (N−x + 2). At this time, the advance of the channel phase is (N-x + 1) or (N-x +).
2) Either of them will occur with a probability of 1/2. Therefore, depending on the value of the flip-flop 116 that toggles, for example, "H"
Is (N−x + 1), and “L” (N−x + 2). The channel determination circuit 115 outputs this determination result as a channel shift command 48. As a result, the channel synchronization can be pulled in even if the signal necessary for determining the advance of the channel phase is lost due to the false frame.

On the basis of the channel shift command 48 of the channel phase determination circuit 9, the byte / serial converter 2 corrects the channel advance. Next, consider a state where the frame synchronization is lost (the frame synchronization loss signal 25 is at the H level).

In the frame pattern detection circuit 10, the STM
-1 Detect the bit advance frame pattern of 1 to 7 bits in the signal 20. Table 1 shows the frame patterns detected by the frame pattern detection circuit 10.

[0033]

[Table 1]

When the frame pattern shown in Table 1 is detected, the frame pattern detection circuit 21 outputs the frame pattern detection signal 21 and the bit phase signal 22 indicating the bit advance value. The logical product circuit 13 calculates the logical product of the bit phase signal 22 indicating the bit advance value and the frame desynchronization signal 25.
Outputs the bit shift instruction 40.

Thus, the bit shift command 40 is output from the first low speed synchronizing section 3. Similarly, the bit shift commands 42, 44, and 46 are also output from the other second low-speed synchronizing unit 4, third low-speed synchronizing unit 5, and fourth low-speed synchronizing unit 6. In the bit-serial / parallel conversion unit 1, these bit shift commands 4
Correct the bit advance based on 0, 42, 44, 46.

On the other hand, the frame position designation signal 41 output from the OR circuit 15 is the frame pattern detection signal of the frame pattern detection circuit 10 when the frame synchronization is lost.
Therefore, the frame position designation signal 41 indicates the frame pattern detection position. Therefore, in the same manner as in the state where the frame synchronization is pulled in, the channel phase determination circuit 9 determines the advance of the channel phase at the frame pattern detection position for the first low speed synchronization unit 3 to the fourth low speed synchronization unit 6, and It can be corrected by the serial-parallel converter 2.

Although the STM-4 multiplexed signal has been described here with reference to the drawings, it is clear that the channel detection can be performed by the same method for the STM-N (N> 2) multiplexed signal. is there.

[0038]

As described above, according to the present invention, a low-speed synchronizing section having a frame pattern detection circuit, a frame synchronization detection / protection circuit, and a control circuit for controlling the same is provided for each of the number of receiving channels. Channel phase judgment to estimate the amount of advance of the channel phase by judging whether the frame pattern detection position or the frame specific position detected by the low-speed synchronization part is missing or generated due to a false frame or the failure of the low-speed synchronization part. By providing the circuit, the amount of advance of the channel phase can be estimated without referring to the STM identifier, and based on this, the channel synchronization pull-in can be performed immediately.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronous multiplexing converter disassembling unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal circuit of a channel phase determination circuit of the synchronous multiplexer / demultiplexer disassembling unit.

FIG. 3 is a diagram showing a relationship between a channel of an STM-4 multiplex signal and a frame position designation signal of the synchronous multiplex converter decomposing unit.

FIG. 4 is a block diagram of a conventional synchronous multiplexing converter disassembling unit.

FIG. 5 is a block diagram of a conventional synchronous multiplexing converter disassembling unit.

[Explanation of symbols]

 1-bit serial-parallel converter 2 Byte serial-parallel converter 3 First low-speed synchronization unit 4 Second low-speed synchronization unit 5 Third low-speed synchronization unit 6 Fourth low-speed synchronization unit 9 Channel phase determination circuit 10 Frame pattern detection circuit 11 Frame sync detection / protection circuit 12 Control circuit

Claims (1)

Claim: What is claimed is: 1. A low-speed synchronization unit having a frame pattern detection circuit, a frame synchronization detection / protection circuit, and a control circuit for controlling the same is provided for each of the low-speed synchronization units. A channel phase determination circuit for estimating the amount of advance of the channel phase by determining whether or not the frame pattern detection position or the frame specific position detected by is missing or generated due to a false frame or a failure of the low-speed synchronization unit is provided. Channel detector.