JP3110387B2 - Multi-frame synchronization detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-frame (multi-frame) synchronization detecting device, and more particularly, to a multi-frame synchronizing detecting device comprising a plurality of frames of digital data.
The present invention relates to a multi-frame synchronization detecting device in a case where data is transmitted in a bit serial format in units of multi-frames.

[0002]

2. Description of the Related Art As a prior art of the present invention, there is, for example, a "multi-frame synchronization method" (hereinafter referred to as a prior art) disclosed in Japanese Patent Application Laid-Open No. 9-307540. In this prior document, a predetermined bit among the status bits indicating the phase (frame number) of each frame in the multiframe is used as a multiframe synchronization bit. In the numerical examples shown in the prior art documents, one multi-frame is composed of 20 frames, and therefore, five bits are required as the state bits representing the phase of each frame. Therefore, on the receiving side, a pattern detector for detecting the position of the synchronization bit in the received data, the synchronization bit data (logic) of each frame is fetched at the synchronization bit position detected by the pattern detector, and the fetched data is stored in the memory. And a reception multi-frame bit counter for writing data to the memory, and performs synchronization detection by comparing the data pattern written to the memory with a predetermined synchronization bit pattern.

[0003]

The above-mentioned prior art method has the following problems. That is, since the state bits are inserted for each frame, when the number of frames forming the multi-frame is large, the number of state bits increases, and the area that can be used as valid data decreases accordingly. In addition, since the format in which the synchronization bits are distributed to each frame is used, a slightly complicated circuit is required for the method of creating the synchronization bits and the method of detecting the synchronization bits.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. A multi-frame synchronization detecting circuit for detecting multi-frame synchronization with a relatively small number of bit patterns and a relatively simple circuit is provided. It is intended to provide. In particular, 320 frames (1 frame 8
It is an object of the present invention to provide a multi-frame synchronization detection circuit suitable for detecting the synchronization of a 2.048 Mbps multi-frame of a primary rate interface (interface) constituting one multi-frame.

[0005]

According to the present invention, two or more frames among frames constituting a multi-frame are set as frames of synchronization bits, and the bit pattern of the frames of the synchronization bits matches a predetermined bit pattern. It is determined whether or not the multi-frame synchronization is detected by checking whether or not this is the case. For example, one frame is composed of 8 bits, and 320
When one frame is composed of one frame, 320 frames are numbered from 0 to 319, and 8 bits of the 0th frame are used as synchronization pattern data 1, and
Synchronization was detected using 8 bits of the ninth frame as synchronization pattern data 2.

That is, in the multi-frame synchronization detecting device of the present invention, one frame is composed of n (n is an arbitrary natural number) bits, and one multi-frame is detected.
e) is composed of N (N is an arbitrary natural number) frames and 1
The N frames in the multi-frame are numbered from 0 to N−1, and the A-th (0 ≦ A <N−1) -th frame is configured by the synchronization pattern 1 and the B-th frame (A <B <N− In the multi-frame synchronization detecting apparatus when the 1st frame is configured by the synchronization pattern 2, a frame counter for counting a frame signal indicating a frame delimiter, a bit serial (bi)
t serial), a serial / parallel conversion circuit for converting a multi-frame signal transmitted in the form of n-bit parallel data into one frame of parallel data. -The output of the parallel conversion circuit is compared with the synchronization pattern 1 for each frame, and if they match, a numerical value A is preset to the count value of the frame counter (pr
eset), after the preset, when the count value of the frame counter is B, the output of the serial / parallel conversion circuit is compared with the synchronous pattern 2 by the synchronous pattern 2 detection circuit, and Means for outputting a synchronization establishment signal to a synchronization protection circuit, wherein when the temporary synchronization establishment signal is continuously received by the first predetermined value by the synchronization protection circuit, the logic of the complete synchronization signal is set to "H", Means for ignoring the output of the synchronization pattern 1 detection circuit while the signal logic is "H", and outputting a temporary asynchronous establishment signal to the synchronization protection circuit when the output of the synchronization pattern 2 detection circuit indicates a mismatch. In the synchronization protection circuit, the temporary asynchronous establishment signal is
Means for setting the logic of the perfect synchronizing signal to "L" when the predetermined number of signals is continuously received, and for starting the resetting of the frame counter by the output of the synchronizing pattern 1 detecting circuit.

The frame number A is A = 0, and presetting A to the count value of the frame counter means resetting the frame counter. I do.

Further, n = 8, N = 320, A = 0, B =
159. It is characterized in that both the first numerical value and the second numerical value are selected from 1 or more and 16 or less. It is characterized in that both the first numerical value and the second numerical value are selected to be 2. The synchronization pattern 1 is set in a register d, and the synchronization pattern 2 is set in a register e.
Is set.

Further, the first numerical value and the second numerical value are both externally set to the synchronization protection circuit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a primary rate interface 2.04.
FIG. 4 is a format diagram showing a configuration of a multi-frame when data of an 8 Mbps interface is time-division multiplexed. Referring to FIG. 1, in the present embodiment, a serial / parallel conversion circuit 11 for converting serial data a input from the line side into 8-bit parallel data b, and the above-described 8-bit parallel data b and externally set The data d of the synchronization pattern 1 is compared with each frame every frame.
A synchronization pattern 1 detection circuit 12 for setting a value of a frame counter (not shown in FIG. 1 and described in FIG. 4) counting up to 9 to 0, and a value of 159 for the frame counter
, The 8-bit parallel data b supplied from the serial-parallel conversion circuit 11 is compared with the data e of the synchronization pattern 2 set from the outside, and a synchronization pattern 2 detection circuit for outputting a temporary synchronization establishment signal i when they match. 13 is provided.

Further, in order to prevent erroneous synchronization, a synchronization protection circuit 14 is provided, and when the temporary synchronization establishment signal i arrives continuously for a predetermined number of times (for example, X times and X is called the number of backward protection stages) during asynchronous operation. Assuming that synchronization has been established, the resetting of the frame counter is stopped, and when the temporary asynchronous establishment signal j arrives for a predetermined number of times (for example, Y times and Y is referred to as the number of forward protection stages) during synchronization, it is determined that the synchronization is lost. It is assumed that the resynchronization operation is started.

FIG. 4 is a detailed block diagram of the block diagram of FIG. 1 for convenience of explanation. In FIG. 4, the same reference numerals and the same reference numerals denote the same parts as in FIG. 1, and reference numeral 41 denotes a frame counter. , Reference numeral 42 denotes a frame counter decoder, reference numeral 43 denotes a register d, reference numeral 44 denotes a register e,
Reference numeral 45 denotes an AND gate.

The operation of this embodiment will be described below with reference to FIGS. 1, 2 and 4. Serial-parallel conversion circuit 11
Converts 8-bit serial data a per frame input from the line side into 8-bit parallel data b. For this conversion, it is necessary that the bit synchronization and the frame synchronization are established, but these are already synchronized, and here, it is assumed that only the synchronization of the multi-frame is a problem. Accordingly, a frame signal c indicating a frame break is also generated, and this is
Count with. Therefore, the count value of the counter 41 indicates the frame number (see FIG. 2).

The data d of the synchronization pattern 1 is externally set in the register d. The synchronization pattern 1 detection circuit 12
The contents of the parallel data b and the register d are constantly compared,
When both match, a logic "H" signal is output. When the synchronization protection circuit 14 does not output the complete synchronization signal at logic "H" and outputs it, the resynchronization request signal k is output at logic "H" (that is, both signals are the opposite logic of the same signal). Can be considered to be represented by
The synchronization detection signal from the detection circuit 12 passes through the AND gate 45, and resets the frame counter 41. That is, the time when synchronization is detected by the synchronization pattern 1 detection circuit 12 is defined as the phase of the count value 0 of the frame counter 41.

The decoder 42 outputs a signal of logic "H" only during a phase in which the count value of the frame counter 41 is 159. The synchronization pattern 2 detection circuit 13 is a decoder 4
2 is controlled so as to operate only when the output is logic "H". That is, only at this time, the parallel data b and the register e4
Compare with the contents of 4. Since the data e of the synchronization pattern 2 is stored in the register e44, the frame number 1
Since the fact that the 59 parallel data b matches the content of the register e44 means that synchronization has been established, the temporary synchronization establishment signal i is output to the synchronization protection circuit 14. Since the values of the rear protection stage number X and the front protection stage number Y are set in advance in the synchronization protection circuit 14, when the temporary synchronization establishment signal i arrives X times in succession, the complete synchronization signal is set to logic "H" and output. I do. In this case, the logic of the resynchronization request signal k becomes "L", and the frame counter 41 is reset by the AND gate 4.
5 is not performed, and only the output of the synchronous pattern 2 detection circuit 13 is monitored.

At the time when the count value of the frame counter 41 is 159, as long as the parallel data b matches the contents of the register e44, the synchronization is complete. The synchronization protection circuit 14 does not perform any operation. When the count value of the frame counter 41 is 159, the parallel data b is stored in the register e4.
If the content does not match the content of No. 4, suspect out of synchronization. However, at this time, I did not conclude that it was out of sync immediately,
The temporary asynchronous establishment signal j is sent to the synchronization protection circuit 14. When the temporary asynchronous establishment signal j arrives Y times in succession, it is determined that the synchronization has been lost, and the complete synchronization signal is set to logic "L". The logic of the resynchronization request signal k becomes “H”, and the synchronization pattern 1 detection circuit 12
, The frame counter 41 is reset, and resynchronization is started.

The values of the number of rear protection stages X and the number of front protection stages Y are appropriately selected depending on the design. However, since it is necessary to ensure the synchronization protection and to shorten the time required for synchronizing, both of them are 1 or more. A number of 16 or less is chosen. As the bit patterns set in the registers d43 and e44, that is, the synchronization pattern data 1 or 2 of the frame numbers 0 and 159, those having a low probability of occurring as bit patterns of other frames are selected.
(However, h indicates hexadecimal notation) Set the bit pattern of the numerical value between.

As described above, when the perfect synchronization is established, the detection signal of the synchronization pattern 1 detection circuit 12 is discarded thereafter, and the frame counter 42 is left to run by the frame signal c. That is, even if the parallel data b is other than the frame number 0 and the coincidence with the data d of the synchronization pattern 1 is erroneously detected, the frame signal c is lost and the frame counter c Is not considered to malfunction. Therefore, as shown in FIG. 1, both the provisional synchronization establishment signal i and the provisional asynchronous establishment signal j
Is output only from.

FIG. 3 is an operation time chart showing the operation of each unit when both the number of rear protection stages X and the number of front protection stages Y in FIG. 1 are set to 2, and while the logic of the complete synchronization signal is "L". The logic of the resynchronization request signal k is “H”, the frame counter 41 is reset by the detection output of the synchronization pattern 1 detection circuit 12, and its count value becomes zero. Next, when the count value is 159, when a match is detected by the synchronization pattern 2 detection circuit 13, the temporary synchronization establishment signal i is sent once to the synchronization protection circuit 14, and then the count value of the frame counter 41 becomes zero. When this happens, a signal is output from the synchronization pattern 1 detection circuit 12 and the frame counter 41 is reset. At this time, since the count value of the frame counter 41 is 0, this is a reset just in case.

Next, when the count value is 159, if a match is detected by the synchronization pattern 2 detection circuit 13, a temporary synchronization establishment signal i is sent once again, and the total number of temporary synchronization establishment signals i is set. Since the number of backward protection stages X has reached, the complete synchronization signal becomes logic "H", the logic of the resynchronization request signal k becomes "L", and the output of the logic pattern 1 detection circuit 12 is ignored. When the temporary asynchronous establishment signal j is output twice consecutively from the synchronization pattern 2 detection circuit 13 while the complete synchronization signal is at logic “H”, the logic of the complete synchronization signal becomes “L”.

In the above, one frame is composed of 8 bits.
The present invention has been described for the case where one multi-frame is composed of 320 frames. However, the present invention
Obviously, the present invention can be applied regardless of the number of bits of a frame and the number of frames of a multi-frame. In the present invention, the synchronization pattern 1 data d is put in the 0th frame, and the frame counter is reset by the detection output of the synchronization pattern 1 detection circuit 12. However, the synchronization pattern 1 data d is put in the Ath frame. Synchronous pattern 1 detection circuit 12
, The frame counter may be preset to a numerical value A at the detection output.

Further, according to the present invention, the data of the synchronization pattern is made into two types, 1 and 2, and when the data of the synchronization pattern 1 arrives, the frame counter 41 is reset. When the data b matches the bit pattern of the synchronization pattern 2, the provisional synchronization establishment signal i is output. However, the data of the synchronization pattern is divided into three types of 1, 2, and 3, and the data of the synchronization pattern 1 is set to the frame number. 0, the data of the synchronization pattern 2 is inserted into the frame of the frame number 100, for example, and the data of the synchronization pattern 3 is inserted into the frame of the frame number 20.
0, the frame counter 41 is reset when it matches the synchronization pattern 1, and after this reset, when the frame numbers are 100 and 200, the temporary synchronization establishment signal i is output every time the bit pattern matches. You may. When the number of synchronization patterns is increased, the synchronization pull-in time can be reduced without reducing the number of rear protection stages and the number of front protection stages.

[0023]

As described above, according to the present invention, the synchronization pattern data for synchronizing is inserted into the head (No. 0) frame and the substantially center (M-th) frame in the multiframe. When the synchronization pattern of the first frame is detected, the frame counter is reset, and after this reset, a temporary synchronization establishment signal i is output when a match is detected in the M-th frame, and the synchronization protection circuit is Since the configuration is provided to prevent erroneous synchronization, there is an effect that reliable multi-frame synchronization can be established with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of the present invention.

FIG. 2 is a format diagram showing a configuration example of a multi-frame to which the present invention is applied.

FIG. 3 is an operation timing chart showing an operation of the device of FIG. 1;

FIG. 4 is a block diagram showing details of the apparatus of FIG. 1;

[Explanation of symbols]

 Reference Signs List 11 serial / parallel conversion circuit 12 synchronization pattern 1 detection circuit 13 synchronization pattern 2 detection circuit 14 synchronization protection circuit 41 frame counter 42 frame counter 43 register d 44 register e

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-264744 (JP, A) JP-A-7-7500 (JP, A) JP-A-6-37746 (JP, A) JP-A-4- 4627 (JP, A) JP-A-56-56058 (JP, A) JP-A-55-44263 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00-3 / 26 H04L 7/00-7/10

Claims (7)

(57) [Claims] 1. One frame (frame) is composed of n (n is an arbitrary natural number) bits, and one multi-frame (multi-
frame) is composed of N (N is an arbitrary natural number) frames, and N frames in one multi-frame have 0 to N−1.
, The A-th (0 ≦ A <N−1) -th frame is configured by the synchronization pattern 1 and the B-th (A <B <N−1) -th frame is configured by the synchronization pattern 2 In the multi-frame synchronization detecting device, a frame counter for counting a frame signal indicating a frame delimiter, and a direct / multi-frame signal for converting a multi-frame signal transmitted in the form of bit serial into n-bit parallel one-frame parallel data. Parallel conversion circuit, While the complete synchronization signal is at logic "L", the output of the serial / parallel conversion circuit is compared with the synchronization pattern 1 for each frame by a synchronization pattern 1 detection circuit, and when they match, the count value of the frame counter Means for presetting the numerical value A to the preset value. After the preset, when the count value of the frame counter is B, the synchronous pattern 2 detecting circuit The output of the serial-parallel conversion circuit compared to the sync pattern 2,
Means for outputting a provisional synchronization establishment signal to the synchronization protection circuit if they match, when the synchronization protection circuit continuously receives the provisional synchronization establishment signal by a first predetermined value, the logic of the complete synchronization signal is set to "H" When the logic of the complete synchronization signal is "H", the output of the synchronization pattern 1 detection circuit is ignored, and when the output of the synchronization pattern 2 detection circuit indicates a mismatch, the temporary asynchronous establishment signal is sent to the synchronization protection circuit. Means for outputting; when the temporary asynchronous establishment signal is continuously received by the synchronization protection circuit by a second predetermined value, the logic of the complete synchronization signal is set to “L”, and the frame is output by the synchronization pattern 1 detection circuit. Means for starting reset of a counter. 2. The multi-frame synchronization detecting device according to claim 1, wherein A of the frame number is A = 0, and presetting A to the count value of the frame counter resets the frame counter. Multi-frame synchronization detecting device. 3. The multi-frame synchronization detecting device according to claim 2, wherein n = 8, N = 320, A = 0, and B = 159. 4. The multi-frame synchronization detecting device according to claim 1, wherein both the first numerical value and the second numerical value are selected from 1 or more and 16 or less. 5. The multi-frame synchronization detecting device according to claim 4, wherein both the first numerical value and the second numerical value are selected to be 2. 6. The multi-frame synchronization detection device according to claim 1, wherein the synchronization pattern 1 is set in a register d, and the synchronization pattern 2 is set in a register e. 7. The multi-frame synchronization detecting apparatus according to claim 1, wherein both the first numerical value and the second numerical value are externally set in the synchronization protection circuit. Detection device.