JPH0448491A - Semiconductor integrated circuit and dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To accurately control the operation of a circuit using a control signal by setting the ratio of a resistance value of the resistance caused by various wiring layers constituting a resistance circuit to be equalized with that of the wiring layer. CONSTITUTION:Time constant by a resistance circuit 3 composed of resistance R1/R2 and a capacitor C is set so that the delay time tau of the control signal PHI2 is approximately equal to delay time tau 0 of potential transition in a signal conductor 2. Therefore, even when the delay time tau 0 of the signal line is fluctuated because there is process fluctuation, a control signal PHI 2, whose delay time is fluctuated following this, can be obtained. Thus, the control signal synchronized with the transition of the signal conductor can be surely generated without taking an excess timing margin.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to large-scale integrated circuit devices such as dynamic semiconductor memory devices, and particularly deals with delays in potential transitions in long signal lines. This invention relates to an improvement in a circuit portion that generates a control signal with a certain delay.

(Prior Art) Due to advances in microfabrication technology, dynamic semiconductor memory devices (DRAM) with large capacity and high speed are being developed one after another. In order to realize high-speed DRAM,
Advances in not only device technology but also circuit design technology are essential.

DRAM typically has a memory cell array with a periodic configuration in which subcell arrays and bit line sense amplifiers are repeatedly arranged. Therefore, a generation circuit for various control signals is required to periodically control these signals. Among these control signal generation circuits, the delay time from starting the selected word line rising to starting bit line sensing, and from starting the word line falling to starting bit line equalization is particularly important. The circuit that sets the delay time is important. If a bit line sensing operation is started before the word line rises and cell data is read onto the bit line, the cell data will be destroyed. Furthermore, if bit line equalization is started before the word line falls and the cell transistors are turned off, the cell data will be similarly destroyed. Conventionally, such a delay circuit has been constructed, for example, by an inverter chain that receives a control signal for charging and discharging the word line or a signal synchronized therewith.

However, in such a simple delay circuit, when the material and film thickness of the wiring layer constituting the word line change due to process variations, and the word line delay changes due to this, it is difficult to respond to the word line delay change. I can't. Furthermore, the word line delay varies depending on variations in chip temperature, power supply potential, and the like. Conventionally, therefore, a large margin has been set so that the DRAM chip operates normally even under such fluctuations. Setting a large margin makes it difficult to access the DRAM at high speed.

(Problems to be Solved by the Invention) As described above, in conventional DRAMs, a control circuit that obtains a control signal having a delay time corresponding to the word line delay in synchronization with word line driving has a problem with the word line delay or fluctuation. In order to ensure that the timing of control signal generation remains constant even in the case of
There was a problem that access time was slow.

Similar problems exist not only in DRAMs but also in other large-scale integrated circuits having long signal lines.

An object of the present invention is to provide a semiconductor integrated circuit device having a control signal generation circuit that solves such problems.

Another object of the present invention is to provide a DRAM having a control signal generation circuit that automatically adjusts the timing of control signal generation in response to process variations in word line delay.

[Structure of the Invention (Means for Solving the Problem) A semiconductor integrated circuit device according to the present invention includes a signal line drive circuit driven by a control signal, and a first signal line drive circuit connected to the output terminal of the drive circuit. A second signal line constituted by at least two types of wiring layers and a control signal generation circuit that generates a control signal delayed by a time corresponding to a delay in potential change on this signal line are set to H. In such a semiconductor integrated circuit device, according to the present invention, the control signal generation circuit includes the first. The first wiring layer is formed using the same wiring layer as the second wiring layer. The first wiring layer has a resistance value ratio set corresponding to the resistance value ratio of the second wiring layer. a resistor circuit in which a second resistor is connected in series; a capacitor connected to one terminal of this resistor circuit and forming a time constant circuit together with the resistor circuit; and two terminals of the resistor circuit connected to a power supply potential and a ground potential, respectively. includes a charging transistor and a discharging transistor connected to the
A charging/discharging circuit in which these charging/discharging transistors are controlled by a control signal of the signal line driving circuit or a signal synchronized therewith to alternately turn on and off; and an input terminal is connected to a connection point between the resistor circuit and the capacitor. and an output buffer.

The present invention also provides a word line drive circuit driven by a control signal, a word line connected to an output terminal of this drive circuit via a word line drive line and a decoder transistor, and a delay in potential change of this word line. In a dynamic semiconductor memory device, the control signal generation circuit includes a control signal generation circuit that generates a control signal delayed by a time corresponding to . A resistor circuit in which a plurality of resistors are connected in series, each of which is formed using the same wiring layer as the plurality of wiring layers that constitute the wiring layer, and whose resistance value ratio is set corresponding to the resistance value ratio of the plurality of wiring layers. , a capacitor that is connected to one terminal of the resistance circuit and forms a time constant circuit together with the resistance circuit, and a charging transistor and a discharging transistor that connect the two terminals of the resistance circuit to a power supply potential and a ground potential, respectively. ,
A charging/discharging circuit in which these charging/discharging transistors are driven on and off alternately under the control of a control signal of the word line drive circuit or a signal synchronized therewith, and an input terminal connected to a connection point between the resistor circuit and the capacitor. and an output buffer.

(Function) As described above, in the present invention, the control signal generation circuit that obtains the control signal with a predetermined delay time in synchronization with the driving of the signal line uses a resistor circuit that uses the same type of wiring layer as the signal line. configured using Therefore, the delay time of the control signal obtained varies in accordance with the variation in the delay of the driven signal line. Moreover, in that case, the resistance value of the resistor due to the various wiring layers that make up the resistor circuit may be affected by process variations in the various wiring layers that make up the signal line, or the resistance value of the resistor due to the various wiring layers that make up the resistor circuit will directly affect the delay time variation of the control signal. The ratio is set equal to that of the wiring layer. As a result, it is possible to obtain a control signal that always has a delay equal to that of the driven signal line. Therefore, circuit operation can be accurately controlled using this control signal.

In the DRAM according to the present invention, the influence of process variations of various wiring layers constituting the word line is directly reflected in the control signal having a delay corresponding to the delay of word line transition. Therefore, the operations of various circuits controlled after detecting a word line transition are performed accurately without taking unnecessary timing margins. This allows DRAM
allows for high-speed access.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a control signal generation circuit section in an integrated circuit device according to an embodiment. The signal line driving circuit 1 is controlled by a control signal φl to drive a long signal line 2 within the chip. The signal line 2 is composed of at least two types of wiring layers.

Here, the term "different types of wiring layers" refers to wiring layers having different wiring materials, wiring manufacturing processes, and the like. In the case of the figure, the signal line 2 is constituted by two types of wiring layers, and each wiring layer portion is equivalently connected to a resistance r1. It is indicated by r2. Each wiring layer has a floating capacitance ff1cI.

These CR distributions cause a delay in the rise and fall of the signal line 2.

C
It is constructed using an R time constant circuit. The time constant circuit is
The resistor circuit 3 is composed of a resistor circuit 3 in which two resistors R1 and R2 are connected in series, and a capacitor C connected to one terminal N of the resistor circuit 3. At both ends of the resistor circuit 3, there is a p
Channel MO3) A transistor Q1 and an n-channel MOS transistor Q2 are provided. The charging p-channel MOS transistor Q1 has a drain connected to the terminal N of the resistance circuit 3 to which the capacitor C is connected, and a source connected to the power supply VCC.

The drain of the discharging n-channel MOS transistor Q2 is connected to the other terminal of the resistance circuit 3, and the source is grounded. The gates of these MOS transistors Ql and Q2 are commonly connected. A control signal φ1 is input to this common gate via an inverter 11. Therefore M
The OS transistors Ql and Q2 are turned on and off alternately. In this embodiment, an output buffer 4 consisting of three stages of inverters 12 to 3 is connected to the terminal N of the time constant circuit.

In this control signal generation circuit, when the control signal φ1 rises, the charging MO5) transistor Q1 turns on, and the discharging MO5
) The transistor Q2 is turned off and the capacitor C of the time constant circuit is charged. This charging takes place only through the MO3I transistor Q1, and the resistor circuit 3 is not involved. Therefore, this charging delay is mostly caused by the inverter 11 and is small. When the capacitor C is charged and the terminal N rises, the output buffer 4 outputs the control signal φ2.
falls down. When the control signal φ1 falls, the charging p
Channel MO5) The transistor Q1 is turned off and the discharging n-channel MOS transistor Q2 is turned on. As a result, the charge in the capacitor C is discharged via the resistance circuit 3. When the potential of the terminal N becomes lower than the circuit threshold of the output buffer 4, the control signal φ2 rises.

FIG. 2 is a timing diagram showing the above operation.

In the circuit of this embodiment, as shown in the figure, a delay τ determined by the time constant circuit is inserted from the fall of the control signal φl to the rise of the control signal φ2.

That is, by detecting the fall of the control signal φ1, the control signal φ2 that rises after a predetermined time delay is obtained.

Here, the time constant of the resistor circuit 3 consisting of resistors R1 and R2 and the capacitor C is set to be approximately equal to the delay time τ of the control signal φ2 or the delay time τ0 of the potential transition on the signal line 2. To simplify the explanation, if we approximate the delay time as a time constant determined by the combined resistance and combined capacitance, we have τ-(R1+R2) C ro = (rl +r2) (C1+C2), and τ-τ0 The values of resistors R1, R2 and capacitor C are set so as to satisfy the following. In this case, the important thing is that the ratio of the resistances R1 and R2 is the resistance rl of the second signal line, the resistance rl of each wiring layer,
It is to be set equal to the ratio of r2. However, the resistance rl of the signal line 2.

The proportion of C2 cannot be measured externally in most cases.

What can be measured externally is the delay time τ0. Therefore, when actually setting the ratio of resistors R1 and R2, the delay time Determine the contribution of resistances r1 and C2 to τ0. This determines the ratio of the resistors rl and r2, so the ratio of the resistors RI to R2 can be set equal to this.

In this way, in this embodiment, the same layers as the signal wiring layer are combined, the ratio of the resistance values R1 and R2 is set equal to that of each wiring layer of the signal wiring, and the resistance circuit is constructed so as to satisfy τ-τ0. Determine the values of resistors R1 and R2. As a result, even if the delay time τ0 of the signal line fluctuates due to process fluctuations, the control signal φ whose delay time fluctuates accordingly.
You can get 2. In other words, a control signal synchronized with the transition of the signal line can be reliably generated without taking any extra timing margin.

The above embodiment can be applied to any integrated circuit that includes a long signal line inside the chip and needs to generate a control signal in synchronization with the rise and fall of the signal line.
It is particularly useful when applied to integrated circuits such as DRAMs, which are becoming larger in scale.

An embodiment in which the present invention is applied to a DRAM will be specifically described below.

FIG. 3 shows the configuration of a word line drive circuit section in a DRAM of such an embodiment. The word line booster circuit 11 includes a boosting capacitor Cp+ and a charging n-channel MOS transistor Q11 that pre-charges one end of this capacitor Cp.
．． p channel M for driving the other end of capacitor Cp
OS transistor Q 12. It also includes a capacitor drive circuit including an n-channel MOS transistor Q13 and the like. The gate of the charging MO3I transistor Qll is controlled by the control signal φpre, and the capacitor drive circuit is controlled by the control signal φll. This word line booster circuit 1
1 is placed in the peripheral circuit section of the DRAM chip. The control signal φ11 is generated, for example, after the row address is determined, and is used to send out a boosted potential from the word line booster circuit 11.

The output terminal of the word line booster circuit 11 is connected to the word line drive line W.
Via DRV, MOS) transistor Q14°Q15.
It is connected to a selected word line WL in the memory cell array through a plurality of stages of decoders (brief decoder and row decoder) indicated by QlB. Only one memory cell is shown in the figure, or a large number of memory cells each consisting of a transfer gate MOS transistor QM and a cell capacitor CM are connected to the word line WL.

FIG. 4 shows the word line WL in such a word line drive circuit.
This configuration includes a control signal generation circuit section that obtains a control signal synchronized with potential transitions. Here, from the output terminal of the word line booster circuit 11, the word line drive selection WD RV,
The resistance of each wiring layer constituting the diffusion layer of the decoder transistor, the word line WL, etc. is r11. r12.
r 13, and the associated capacitance is C11
, C12, and C13.

The control signal generation circuit uses the control signal φ11 for raising the word line of the word line booster circuit 11 to generate a control signal φ12 with a delay corresponding to the delay of the word line WL.
This is what you get. Control signal φ12 is used, for example, as a control signal for activating a bit line sense amplifier. Almost the same as in the previous embodiment, resistors R11 and R1
A time constant circuit is constituted by a resistor circuit 12 in which 2 and R13 are connected in series, and a capacitor C. Resistance circuit 12
There is a p-channel MO5) transistor Q1 for charging on both ends of the
and a discharging n-channel MO5) transistor Q2. These MOS) transistors Ql.

The gates of Q2 are commonly connected and a control signal φ11 is applied here.
is input via the inverter 11. At the node N of the time constant circuit, an output buffer 13 consisting of three stages of inverters I2 to I4 is provided, from which a control signal φ12 is taken out.

Resistors R11, R12 and R13 of the resistance circuit 12 are connected to the output terminal of the word line booster circuit 11, rl].

It is constructed using the same wiring layer as the multiple types of wiring layers shown in rl2 and 13, and the ratio of their resistance values is set to be equal to each other.The method for determining the resistance value is as explained in the previous example. It is similar to

FIG. 5 is a timing chart showing word line selection and generation of control signal φI2 in the DRAM according to this embodiment. In the initial state, the control signal φpre is at “H” level, φ
11 is an "H level", and the word line side terminal of the boosting capacitor Cp is precharged with the potential Vw. By changing the control signals φpre and φII from the "H" level to the "L# level," Potential VW is applied to the other end of capacitor Cp, and the boosted potential is sent to word line drive line WDRV by capacitive coupling. This boosted potential is propagated to the word line WL via a plurality of decoder transistors Q14-Q16, and the selected word line WL rises, for example, as shown in FIG. On the other hand, while the control signal φ11 is at “H” level, the charging MO of the time constant circuit
5) Since transistor Q1 is on and discharging MO5) transistor Q2 is off, capacitor C is charged to Vcc.

When the control signal φ11 becomes “L” level, the charging 5ios
Transistor Q1 is off, discharge MOS transistor Q
2 is turned on, and the charge on the capacitor C is discharged through the resistor circuit 12. When the capacitor node N1 becomes equal to or less than the circuit threshold of the first stage inverter of the output buffer 71B, the control signal φ12 rises. As shown in FIG. 5, this control signal φ12 rises with a delay from the fall of the control signal φ11 with a predetermined delay time τup determined by the time constant circuit. As mentioned above, the delay time τup of the rise of this control signal φ12 is
It is set to correspond to the delay time of the rise of L.

When the control signal φ11 returns from the “L#” level to the “H” level again, the control signal φ12 falls with almost no time delay. The resistor circuit 12 is not involved in the falling of the control signal φ12. It is from.

The control signal φ12 obtained in synchronization with the rise of the word line WL in this manner is used, for example, as an activation signal for the bit line sense amplifier. This allows large-scale D
High-speed access to RAM becomes possible. That is, in a large-scale DRAM, a potential is propagated from a word line booster circuit in a peripheral circuit to a word line via a long wiring line, resulting in a considerable delay in the transition of the word line. Moreover, variations in process parameters cause variations in the delay.

The bit line sense amplifier must be activated after the potential of the word line has risen sufficiently and memory cell data has been read onto the bit line. Failure to do so will lead to data destruction. For this reason, it is usually necessary to activate the bit line sense amplifier with a large timing margin from the drive of the word line booster circuit, which hinders high-speed access.

In this embodiment, since the control signal φ12 is always synchronized with the rising edge of the word line, including the influence of process parameter variations, by using this as the activation signal of the bit line sense amplifier, wasted timing can be avoided.・No margin required.

FIG. 6 shows the configuration of a word line drive circuit section of a DRAM according to still another embodiment. In this embodiment, contrary to the embodiment shown in FIG. 4, a control signal generating circuit is configured to obtain a control signal that falls with a delay corresponding to the delay time when the word line falls. Portions corresponding to those in FIG. 4 are designated by the same reference numerals as in FIG. 4, and detailed description thereof will be omitted. In FIG. 4, the resistance circuit 12 is placed in the discharge path, whereas in this embodiment the resistance circuit 12 is placed in the charge path. Other than that, it is the same as Figure 4.

FIG. 7 is a timing chart showing how the control signal φ12 is generated in this embodiment. In this embodiment, when the control signal φ11 of the word line booster circuit 11 returns to the “H” level and the selected word line WL returns to the “L” level, the control signal φ12 returns to “L° level.

The control signal φ12 of this embodiment is used, for example, as an equalization signal for a bit line equalization circuit. In other words, when the control signal φ12 is at the "H" level, the equalization circuit is released, and the control signal φ12 is at the "L" level to precharge and equalize the bit line. In order to prevent data destruction, it is necessary to do this after the cell transistor is turned off by going to the "L" level.

In this embodiment, since the control signal φ12 that falls with a delay equal to the fall delay of the word line is obtained, by using this as an equalization signal, bit line precharge and equalization that meet such requirements can be achieved. operation can be realized.

FIG. 8 is an embodiment that combines the embodiments of FIGS. 4 and 6. In this embodiment, a first resistance circuit 121 is provided in the charging path, and at the same time, a second resistance circuit 122 having a similar configuration is provided in the discharging path. First resistance circuit 12
1 resistor R11° Material and resistance value of R12, R13, and resistors R21, R22, R23 of the second resistor circuit 122
The material and resistance value of are selected in the same manner as in each of the previous embodiments.

According to this embodiment, it is possible to obtain a control signal with a delay corresponding to the delay at both the rise and fall of the word line WL.

The present invention is not limited to the above embodiments.

For example, when determining the ratio of the resistance values of the respective resistors constituting the resistance circuit, the diffusion layer resistance, which has relatively small process variations, may be fixed.

Even if this is done, the effect on the characteristics obtained is small. Regarding the output buffer, although the embodiment shows a case of three stages of inverters, it may be one stage, or two stages may be used if a control signal having a phase opposite to that of the embodiment is obtained.

[Effect of the Invention J As described above, according to the present invention, it is possible to obtain a control signal that always has a delay equal to the delay of potential transition of a long signal line driven within an integrated circuit chip. Therefore, circuit operation can be accurately controlled using this control signal.

In particular, in the DRAM according to the present invention, the influence of process variations in the various wiring layers constituting the word line path is directly reflected in the control signal having a delay corresponding to the delay in word line transition. Therefore, the operation of various circuits that are controlled after detecting a word line transition is unnecessary.
It is done precisely without taking any margins. This results in
High-speed access to DRAM becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the main part configuration of an integrated circuit device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of generating a control signal, and FIG. 3 is a word line in a DRAM according to another embodiment. FIG. 4 is a diagram showing the configuration of the drive circuit section, FIG. 4 is a diagram showing the configuration of the control signal generation circuit section synchronized with the word line drive, FIG. 5 is a timing diagram showing the operation of generating the control signal, and FIG. 7 is a diagram showing the configuration of a control signal generation circuit synchronized with word line driving in a DRAM according to another embodiment, FIG. 7 is a timing diagram showing the operation of generating the control signal, and FIG. 8 is a diagram showing still another embodiment. FIG. 2 is a diagram showing the configuration of a control signal generation circuit unit synchronized with word line driving of the DRAM. l...signal line drive circuit, 2...signal line, 3...resistance circuit, 4...output buffer, Ql...p-channel MOS transistor for charging, Q2...n-channel MOS for discharging Transistor, 11... word line booster circuit,
WDRV...word line drive line, Ql4. Ql5. Q
l6・decoder transistor, WL・word line,
12...Resistance circuit, 13...Output buffer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 7 Figure 2

Claims (5)

[Claims] (1) A signal line drive circuit driven by a control signal, a signal line configured by at least two types of wiring layers, first and second, connected to the output terminal of this drive circuit; and a control signal generation circuit that generates a control signal delayed by a time corresponding to a delay in potential change, wherein the control signal generation circuit uses the same wiring layer as the first and second wiring layers. a resistor circuit in which first and second resistors are connected in series and have a resistance value ratio set corresponding to a resistance value ratio of the first and second wiring layers; A capacitor connected to one terminal and forming a time constant circuit together with a resistor circuit, and a charging transistor and a discharging transistor connecting two terminals of the resistor circuit to a power supply potential and a ground potential, respectively,
A charging/discharging circuit in which these charging/discharging transistors are driven on and off alternately under the control of a control signal of the signal line driving circuit or a signal synchronized therewith, and an input terminal is connected to a connection point between the resistor circuit and the capacitor. What is claimed is: 1. A semiconductor integrated circuit device comprising: an output buffer; (2) a word line drive circuit driven by a control signal;
A word line connected to the output terminal of this drive circuit via a word line drive line and a decoder transistor, and a control signal generation circuit that generates a control signal delayed by a time corresponding to the delay in potential change of this word line. In the dynamic semiconductor memory device, the control signal generation circuit is formed using the same wiring layer as a plurality of wiring layers constituting a path from the word line drive line to the diffusion layer of the decoder transistor and the word line. , a resistor circuit in which multiple resistors are connected in series and whose resistance values are set in accordance with the resistance value ratios of these multiple wiring layers, and a resistor circuit that is connected to one terminal of this resistor circuit and is connected to the resistor circuit when A capacitor constituting a constant circuit, and a charging transistor and a discharging transistor that connect the two terminals of the resistance circuit to a power supply potential and a ground potential, respectively,
A charging/discharging circuit in which these charging/discharging transistors are driven on and off alternately under the control of a control signal of the word line drive circuit or a signal synchronized therewith, and an input terminal is connected to a connection point between the resistor circuit and the capacitor. What is claimed is: 1. A dynamic semiconductor memory device comprising: an output buffer; (3) The charging transistor is a p-channel MOS transistor with a drain connected to one terminal of the resistance circuit and a source connected to a power supply, and the discharge transistor has a drain connected to the other terminal of the resistance circuit. an n-channel MOS transistor whose source is grounded and whose gate is commonly connected to the gate of the p-channel MOS transistor, and the capacitor and output buffer are connected to the terminal of the resistor circuit on the p-channel MOS transistor side. 3. The dynamic semiconductor memory device according to claim 2, wherein the dynamic semiconductor memory device is connected to. (4) The charging transistor is a p-channel MOS transistor having a drain connected to one terminal of the resistance circuit and a source connected to a power supply, and the discharge transistor has a drain connected to the other terminal of the resistance circuit. an n-channel MOS transistor whose source is grounded and whose gate is commonly connected to the gate of the p-channel MOS transistor, and the capacitor and output buffer are connected to a terminal of the resistor circuit on the n-channel MOS transistor side. 3. The dynamic semiconductor memory device according to claim 2, wherein the dynamic semiconductor memory device is connected to. (5) a word line drive circuit driven by a control signal;
A word line connected to the output terminal of this drive circuit via a word line drive line and a decoder transistor, and a control signal generation circuit that generates a control signal delayed by a time corresponding to the delay in potential change of this word line. In the dynamic semiconductor memory device, the control signal generation circuit is formed using the same wiring layer as a plurality of wiring layers constituting a path from the word line drive line to the diffusion layer of the decoder transistor and the word line. , a first resistance circuit in which a plurality of resistors are connected in series, the ratio of resistance values of which is set corresponding to the ratio of resistance values of the plurality of wiring layers; and a diffusion layer of a decoder transistor from the word line drive line. A plurality of resistors are formed using the same wiring layer as the plurality of wiring layers constituting the path to the word line, and the resistance value ratio is set corresponding to the resistance value ratio of the plurality of wiring layers. a second resistance circuit connected in series and connected to one end of the first resistance circuit; and a time constant circuit connected in parallel to each resistance circuit at the connection point of the first and second resistance circuits. and a charging transistor and a discharging transistor that connect the other ends of the first and second resistance circuits to a power supply potential and a ground potential, respectively, and the gates of these charging and discharging transistors are connected to the word line drive circuit. a charging/discharging circuit that is driven on and off alternately under the control of a circuit control signal or a signal synchronized therewith; an output buffer having an input terminal connected to a connection point between the first and second resistance circuits; A dynamic semiconductor memory device comprising: