KR920003007B1 - Cmos dram having divided bit line sense amp - Google Patents

Abstract

The DRAM includes a separating means for first and second bit lines by separating clocks. A first cell array (160) selects one memory cell in accordance with word line selecting clocks, and a transfer means (140) selects a first bit line in accordance with a column selecting signal. A sensing means of an N latching circuit (150) senses the data of the first bit line in accordance with a first sensing clock, and a restore means of a P latch circuit (170) restores the data of the first memory cell to the selected memory cell. A sensing means of a second N latch circuit (130) senses the data of a second bit line in accordance with a second sensing clock, while a restore means of a second P latch circuit (110) restores the data of the second bit line to the selected memory cell.

Description

CMOS DRAM with Split Bitline Sense Amplifier

1 is a circuit diagram of a conventional DRAM core unit.

2 is a circuit diagram of the DRAM core unit of the present invention.

3 is a sensing and restoring clock generation circuit diagram.

4 is an output timing chart of FIG.

* Explanation of symbols for main parts of the drawings

100: second light circuit 110: second pitch circuit

120: second half cell array 130: second enlated circuit

140: transfer gate circuit 150: first latch circuit

160: first half cell array 170: first stretch circuit

180: first light circuit

The present invention is to improve the operation characteristics and operating speed of the CMOS device of the divided bit line sensing method, and more particularly, to a CMOS DRAM having a split bit line sense amplifier suitable for manufacturing a high density memory of 4 mega DRAM or more. .

As the DRAM density increases, the number of cells connected to the bit line increases, resulting in the extension of the bit line and the decrease in the width between the bit lines. This results in an increase in the resistance of the bit line and an increase in capacitance, thereby reducing the margin of the sensing signal and also decreasing the operating speed of the DRAM.

Therefore, the above-mentioned problem should be solved in manufacturing a high-density memory of 1 mega DRAM or more. In general, the cell array and the sense amplifier configuration circuit are divided into cell arrays, and each of the divided cell arrays is divided into cell segments. A method of sensing the corresponding bit line for each array is used.

Such a divided bit line sensing method is described by the applicant of the present invention, the patent application No. 87-8771 (name: CMOS DRAM with a built-in split mitrain sense amplifier) and application number 87-9401 (name: homology) It is described in detail.

This will be described with reference to FIGS. 1, 3, and 4 of the accompanying drawings.

FIG. 1 is a circuit diagram of a memory core of a 1 mega DRAM, wherein bit lines 47 and 77 are connected through a channel passage of a separation transistor 60 and bit lines 48 and 78 are separated transistors. Connection is made via the channel path of (61).

)이라하고 비트라인(77)(78)은 각각 제1비트라인(BL₁)(

)이라 칭한다.The isolation transistors 60 and 61 are all N MOS transistors and constitute a transfer gate circuit 148. An isolation clock ( _ISO ) is input to each gate of the isolation transistors 60 and 61. The bit lines 47 and 48 each have a second bit line BL ₀ (

) And the bit lines 77 and 78 are respectively the first bit line BL ₁ (

It is called).

)의 최 외측단부에는 제2 등화회로(100)가 연결된다. 제2 등화회로(100)는 노드(30)에 제2비트라인(BL₀)사이에서 채널을 형성하는 엔 모스 트랜지스터(32)와 제2비트라인(

)사이에서 채널을 형성하는 엔 모스 트랜지스터(33)가 연결되고, 제2비트라인(BL₀)(

)사이에서 채널을 형성하는 엔 모스 트랜지스터(34)가 연결되는 구성으로 된다.Second bit line pair BL ₀ ,

The second equalization circuit 100 is connected to the outermost end of The second equalization circuit 100 may include an NMOS transistor 32 and a second bit line forming a channel between the second bit line BL ₀ at the node 30.

NMOS transistors 33 forming channels are connected between the second bit line BL ₀ (

The NMOS transistor 34 forming a channel is connected to each other.

In addition, all gates of the MOS transistors 32, 33, 34 are commonly connected to the node 31, and an equalization clock Ø _EQ is input thereto.

)사이에서 피 모스(P MOS) 트랜지스터(36)(37)는 노드(38)를 통해 직렬로 연결되고, 상기 트랜지스터(36)(37)의 각각의 게이트의 상기 제2비트라인(BL₀)(

)에 각각 교차되게 연결된다.In addition, the second bit line BL ₀ (

P MOS transistors 36 and 37 are connected in series through node 38, and the second bit line BL ₀ of each gate of the transistors 36 and 37 is connected. (

Are intersected with each other.

In addition, the MOS transistors 36 and 37 may include a second latch circuit 110 for restoring data.

)의 우측 단부에는 엔모스 트랜지스터(50)(51)는 노드(52)를 통해 상기 제2비트라인(BL₀)(

)사이에 직렬로 연결되며, 상기 트랜지스터(50)(51)의 각 게이트는 상기 제2비트라인(BL₀)(

)에 교차되게 연결된다.The second restore clock LA ₁ described later is input to the node 38. Second bit line pair BL ₀ (

At the right end of the NMOS transistor 50, 51 is connected to the second bit line BL ₀ through node 52.

Are connected in series, and each gate of the transistors 50 and 51 is connected to the second bit line BL ₀ (

) Are intersected with

)이 입력된다.The NMOS transistors 50 and 51 are configured of a second N Latch circuit 130 for sensing data. In addition, the node 52 has a second sensing clock (

) Is entered.

)에는 제1 하프 셀 어레이(120)를 구성하는 메모리셀(40)(41)이 공지의 접힘 비트라인방식으로 연결되어 있다. 각 메모리셀은 하나의 엔 모스 트랜지스터(45)와 하나의 스토리지 커패시터(46)로 구성된다.In addition, the second bit line pair BL0 between the second stretch circuit 110 and the second envelop circuit 130 is formed.

) Is connected to the memory cells 40 and 41 constituting the first half cell array 120 by a known folded bit line method. Each memory cell consists of one MOS transistor 45 and one storage capacitor 46.

)은 각각 엠 모스 트랜지스터의 전달 트랜지스터(95)(96)를 통해 입.출력라인(97) 및 입.출력라인(98)에 연결된다.First bit line pair BL ₁ ,

Are connected to the input / output line 97 and the input / output line 98 through the transfer transistors 95 and 96 of the MOS transistor, respectively.

All of the gates of the transfer transistors 95 and 96 receive a column select signal Ø _CD from a column decoder.

)사이에서 엔 모스 트랜지스터(68)(69)는 노드(65)를 통해 직렬연결되고 상기 엔 모스 트랜지스터(68)(69)의 각 게이트는 상기 비트라인(BL₁)(

)에 교차로 연결된다.The first bit line pair BL ₁ connected to the transfer gate circuit 140.

NMOS transistors 68 and 69 are connected in series through node 65 and each gate of each of the NMOS transistors 68 and 69 is connected to the bit line BL ₁ .

) Is connected to the intersection.

)이 입력된다. 상기 엔 모스 트랜지스터(68)(69)는 제1 엔래치회로(150)로 구성된다. 또한 상기 전달 트랜지스터(95)(96)와 각각 연결되는 제1비트라인(BL₁)(

) 사이에는 엔 모스 트랜지스터(90)로 구성된 제1 등화회로(180)가 연결되며 상기 엔 모스 트랜지스터(90)의 게이트에는 등화클럭(Ø_EQ)이 입력된다.In addition, the node 65 has a first sensing clock (

) Is entered. The NMOS transistors 68 and 69 are formed of a first enlatch circuit 150. In addition, the first bit line BL ₁ connected to the transfer transistors 95 and 96, respectively,

) Is connected to the first equalization circuit (180) consisting of the MOS transistor 90, the equalization clock (Ø _EQ ) is input to the gate of the MOS transistor (90).

)사이에는, 채널통로가 노드(82)를 통해 직렬연결되고 각 게이트가 상기 비트라인(BL₁)(

)에 교차로 연결된 피 모스 트랜지스터(80)(81)로 구성된 제1 피래치회로(170)가 연결된다.In addition, the first bit line BL _{1 on the} outer side adjacent to the first light circuit 180 (

Are connected in series through node 82 and each gate is connected to the bit line BL ₁ (

Is connected to the first latch circuit 170 composed of the MOS transistors 80 and 81.

)에는 하나의 엔 모스 트랜지스터(75)와 하나의 스토리지 커패시터(76)로 구성된 메모리셀(70)(71)이 접힘 비트라인 방식으로 연결된 제1 하프 셀 어레이(160)가 연결된다.The first bit line pair BL ₁ between the first enlated circuit 150 and the first stretch circuit 170 (

) Is connected to a first half cell array 160 in which one NMOS transistor 75 and one storage capacitor 76 are connected in a folded bit line manner.

One end of the storage capacitors is connected to 1 / 2V _CC , and word line selection clocks Ø _WL01 and _WL11 that select the memory cells from the row decoder are input to the gates of the transistors of the memory cells.

3 is an exemplary view of a sensing clock generation circuit 12 used in the circuit of FIG.

) 및 클럭(Ø_S)이 입력되며 노드(281)(291)에는 5볼트의 공급전압(V_CC)이 입력된다. 또한 노드(310)(320)에는 하프전압(V_CC/G₂)(2,5볼트)이 입력된다.The line 283, 293 and the line 284 each have a row address signal RA ₇ ,.

) And a clock Ø _S are input, and a supply voltage V _CC of 5 volts is input to the nodes 281 and 291. In addition, half voltages (V _CC / G ₂ ) (2,5 volts) are input to the nodes 310 and 320.

Reference numerals 202, 203, 204, and 205 denote delay circuits each composed of inverters, and reference numerals 206 and 207, respectively, are moving circuits.

Reference numerals 230, 240, 250, 252, 260, 261, 262, 270, 272, and 271 are all NAND gates and reference numerals 231, 232, 234 and 241. 242, 244, 251, 253, 254, 263 and 273 are all inverters.

The operation of the sensing clock generation circuit 12 will now be described in detail.

)가 로우레벨(V_SS전압)일 때 낸드게이트(252)의 출력은 하이레벨(V_CC전압)이 된다.Hang address signal RA8 (or

NAND is at a low level (V _SS voltage), the output of the NAND gate 252 is a high level (V _CC voltage).

Therefore, the separation clock Ø _ISO outputted from the line 301 through the two inverters 253 and 254 becomes a high level.

In addition, the outputs of the NAND gates 230 and 240 all become high levels.

Therefore, since the high level is input to the gates of the PMOS transistors 233 and 243 through the inverters 231 and 232 and the inverters 241 and 242, the two transistors 233 and 243 are both turned off. do.

In addition, since the outputs of the NAND gates 262 and 272 are all high level, the outputs of the inverters 263 and 273 are all low level, and the transistors 264 and 274 are all turned off.

In addition, since the outputs of the inverters 234 and 244 are all at a high level, the transistors 321 constituting the equalizing circuit 206 and the transistors 321 constituting the equalizing circuit 207. ) 322 and 323 are all turned on.

), 제2 리스토이클럭(LA₁), 제1 리스토이클럭(LA₂) 및 제1 센싱클럭(

)은 모두 V_CC/2 레벨로 프리차아지된다.Thus, lines 302, 303, and 304, 305 are both equalized to the V _CC / 2 level. That is, the second sensing clock (

), The second restore clock LA ₁ , the first restore clock LA ₂ , and the first sensing clock

) Are all precharged to the V _CC / 2 level.

In addition, since the lines 282 and 292 are both at a high level, the output of the NAND gate 250 is at a low level, and the output of the inverter 251 is at a high level. In addition, since the outputs of the delay circuits 202 and 203 are all at the high level, the delay circuits 204 and 205 are kept at the low level.

)가 하이레벨로 되고 행어드레스신호(RA₇)가 로우레벨(

는 하이레벨)로 되면 낸드게이트(250)와 인버터(251)로 구성되는 엔드게이트 출력이 하이레벨이어서 라인(301)으로 출력되는 분리클럭(Ø_ISO)은 로우레벨로 변한다.The row address signal RA ₈ (or

) Becomes high level and the row address signal RA ₇ becomes low level (

When the high level), the end gate output composed of the NAND gate 250 and the inverter 251 is high level, so that the separation clock Ø _ISO outputted to the line 301 changes to a low level.

In addition, since the lines 280 and 290 are all at the high level, the equalization circuit 206 and 207 are stopped. Thereafter, when the clock Ø _S becomes high level, first, the output of the NAND gate 260 goes low, and the output of the NAND gate 261 goes high, and the output of the NAND gate 262 goes low.

)은 로우레벨로 된다. 그 다음 지연회로(204)의 출력은 하이레벨로 되며 낸드게이트(230)의 출력은 로우레벨로 된다.Therefore, since the MOS transistor 264 having the high level gate is turned on, the second sensing clock (

) Becomes the low level. The output of the delay circuit 204 then goes high and the output of the NAND gate 230 goes low.

Therefore, the PMOS transistor 233 having the gate at the low level is turned on and the second reset clock LA ₁ is at the high level.

In addition, since the line 282 is at a low level, the output of the inverter 251 is at a low level, and the separation clock Ø _ISO is changed to a high level.

)은 로우레벨로 변한다. 그 다음 지연회로(285)의 출력은 하이레벨이 되고 낸드게이트(240)의 출력은 로우레벨이 된다.The low level of line 282 then causes the output of delay circuit 203 to go low, the output of NAND gate 271 to high level, and the output of NAND gate 272 to low level. Therefore, the NMOS transistor 274 having the high level gate is turned on and the first sensing clock (

) Changes to the low level. The output of the delay circuit 285 then goes high and the output of the NAND gate 240 goes low.

Therefore, the PMOS transistor 243 having the gate at the low level is turned on and the first reset clock LA ₂ is at the high level.

)가 로우레벨이 하이레벨로 변하고, 행어드레스신호(RA₇)가 하이레벨일 때 클럭(Ø_S)이 하이레벨로 되면 순차적으로 분리클럭(Ø_ISO)은 로우레벨로 되고 제1 센싱클럭(

)은 로우레벨로 된다. 또한 제1 리스토어클럭(LA₂)이 하이레벨일 때 분리클럭(Ø_ISO)은 하이레벨로 되고 2센싱클럭(

)은 로우레벨로, 그리고 제2 리스토어클럭(LA1)은 하이레벨로 된다.On the other hand, the row address signal RA ₈ (or

) When the low level changes to a high level and the clock Ø _S goes to a high level when the row address signal RA ₇ is at the high level, the separation clock Ø _ISO goes to the low level sequentially and the first sensing clock (

) Becomes the low level. In addition, when the first restore clock LA ₂ is at a high level, the separation clock Ø _ISO becomes a high level and a two sensing clock (

) Is at the low level, and the second restore clock LA1 is at the high level.

)가 하이레벨일 때 행어드레스신호(RA₈)(

) 및 (RA₇)(

)는 모두 로우레벨이며, 등화클럭(Ø_EQ)의 하이레벨에 의해 프리차아지 싸이클을 유지한다. 따라서 분리클럭(Ø_ISO)은 하이레벨로 되고 제2 등화회로(100)를 구성하는 엔 모스 트랜지스터(32)(33)(34)는 모두 온상태가 되며 제1 등화회로(180)를 구성하는 엔 모스 트랜지스터(90)도 온상태로 된다. 그러므로 제2비트라인쌍(BL₀,

)과 제1비트라인쌍(BL₁,

)은 모두 V_CC/2레벨로 프리차아지된다.4 is an output timing chart of FIG. 3, and before the time t ₁ , a row address strobe (

When the high level is), the row address signal RA ₈ (

) And (RA ₇ ) (

) Are all low level and maintain precharge cycle by high level of equalization clock (Ø _EQ ). Therefore, the separation clock Ø _ISO becomes a high level, and the transistors 32, 33 and 34 constituting the second equalization circuit 100 are all turned on and the first equalization circuit 180 is constituted. The MOS transistor 90 is also turned on. Therefore, the second bit line pair BL ₀ ,

) And the first bit line pair BL ₁ ,

) Are all precharged to the V _CC / 2 level.

)가 로우레벨(액티브 싸이클)로 된후 어드레스가 입력되면, 시간(t₂)에서 행어드레스신호(RA₈)(또는

)가 하이레벨로 되고, 행어드레스신호(RA₇)가 로우레벨이 되었다면 어드레스의 입력시 도시하지 않은 클럭발생회로에서 발생되는 등화클럭(Ø_EQ)은 로우레벨로 된다.Strobe at time t ₁ (

) When the doenhu address is input to the low level (active cycle), the time (t _2), the row address signal (RA ₈₎ (or in

When () becomes high level and the row address signal RA ₇ becomes low level, the equalization clock (Ø _EQ ) generated in the clock generation circuit (not shown) at the input of the address becomes low level.

At this time, the separation clock Ø _ISO is also at a low level. Therefore, the first and second equalization circuits 180 and 100 are turned off and the isolation transistors 60 and 61 are turned off.

Thereafter, the word line selection clock Ø _WL01 for selecting the second half cell array 120 becomes V _CC + 2VT (V _T is the threshold voltage). If the storage capacitor of the memory cell 40 is charged with " 1 " (high level), the second bit line BL ₀ is referred to by charge sharing in the ON state of the transistor 160. As in 400, the voltage is increased by about 200mV at V _CC / 2.

)이 로우레벨(401)로 되고 시간(t₅)에서 제2 리스토어클럭(LA₁)이 하이레벨(402)로 된다. 그러므로 시간(t₄)와 (t₅)사이에서 제2 엔래치회로(130)가 동작을 하여 제2비트라인(

)은 로우레벨(405)로 방전된다.The clock Ø _S used herein is a signal that delays the word line selection signal. Clock at time (t ₃₎ a second sensing clock at time (t ₄₎ as described (Ø _S) is above the high level when the (

) Becomes the low level 401 and the second restore clock LA ₁ becomes the high level 402 at time t ₅ . Therefore, between the times t ₄ and t ₅ , the second latch circuit 130 operates to form the second bit line (

) Is discharged to the low level 405.

In addition, after the time t ₅ , the second stretch circuit 110 is operated to amplify the second bit line BL ₀ to the V _CC level 406 and restore the memory cell 40.

When the restore clock LA ₁ is at the high level, as described above, the separation clock Ø _ISO is at the high level and the isolation transistors 60 and 61 are all turned on at the time t ₆ .

)에 충전된 전하는 제1비트라인(BL₁)(

)으로 전달이 된다. (제5도의 (407)(408))시간(t₇)에서 제1센싱클럭(

)이 로우레벨(403)로 되고 시간(t₈)에서 제1 리스토어클럭(LA₂)이 하이레벨(404)로 되면 상기 전달된 전하는 제1 엔래치회로(130)와 제1 피래치회로(170)에 의해 제1비트라인쌍(BL₁,

)은 각각 V_CC와 V_SS로 되고 상기 메모리셀(40)을 리스토어하며, 열디코오더에서 출력하는 열선택신호(Ø_CD)에 의해 각각의 전달 트랜지스터(35)(96)를 통해 입출력라인(97),(98)으로 출력된다.Therefore, the second bit line BL ₀ (

The charge charged in the) is the first bit line BL ₁ (

) Is delivered. (407, 408 in FIG. ₅ ) the first sensing clock at time t ₇ (

) Becomes the low level 403 and the first restore clock LA ₂ becomes the high level 404 at time t ₈ . 170, the first bit line pair BL ₁ ,

) Are respectively V _CC and V _SS , and restore the memory cell 40, and input / output lines through the transfer transistors 35 and 96 by a column select signal Ø _CD output from a column decoder. 97) and (98).

)가 하이레벨이고 행어그레스신호(RA₇)가 하이레벨이 되면 등화클럭(Ø_EQ)은 로우레벨로 되고 분리클럭(Ø_ISO)도 로우레벨로 된다. 따라서 제1, 제2 등화회로(180)(100)와 분리트랜지스터(60)(61)는 오프상태로 되고 제1 하프 셀 어레이(160)중 어느하나의 메모리셀(70)을 선택하는 워드라인 선택클럭(Ø_WL11)이 V_CC+2VT로 된다. 메모리셀(70)의 스토리지 커패시터(76)에 ＂1＂(V_CC레벨)이 기억되어 있다면 상기 충전전하는 제1비트라인(BL₁)을 참조번호 400과 같이 충전한다.On the other hand, at time t ₂ , the row address signal RA ₈ (or

When () is high level and the hang address signal RA ₇ becomes high level, the equalization clock (Ø _EQ ) goes low and the separation clock (Ø _ISO ) goes low. Therefore, the first and second equalization circuits 180 and 100 and the isolation transistors 60 and 61 are turned off and the word lines for selecting one of the memory cells 70 of the first half cell array 160. The selection clock Ø _WL11 becomes V _CC + 2VT. If V1 (V _CC level) is stored in the storage capacitor 76 of the memory cell 70, the charging charge charges the first bit line BL _{1 as} shown by reference numeral 400.

)이 로우레벨로 되고(401) 제1 엔래치회로(150)가 동작 함으로써 제1비트라인(

)은 레벨로(405)방전이 된다.Then, as described above, when the clock Ø _S becomes high level, the first sensing clock (at time t ₄ )

) Becomes the low level (401) and the first latch circuit 150 is operated, so that the first bit line (

) Is discharged to level 405.

Thereafter, when the first restore clock LA ₂ reaches the high level 406 at time t ₅ , the first latch circuit 170 operates to move the first bit line BL ₁ to the V _CC level 406. The amplification is performed and the memory cell 70 is restored. The separation clock Ø _ISO is then at a high level at time t ₆ .

)에 VCC/2로 충전된 전하는 제1비트라인(

)으로 방전된다.Therefore, the charge of the first bit line BL1 is transferred to the second bit line BL ₀ and the second bit line

Charge charged to VCC / 2 on the first bit line (

Discharged).

)과 제2 리스토어클럭(LA₁)은 각각 로우레벨(403)과 하이레벨(404)로 되고 제1, 제2 엔래치회고(150)(130)와 제1, 제2 피래치회로(170)(110)가 모두 동작함으로써 상기 비트라인(BL₀)(BL₁) 및 비트라인(

)(

)을 각각 V_CC와 V_SS레벨로 증폭하고 상기 메모리셀(78)을 리스토어하게 된다.Then, at a time t ₇ and a time t ₈ , the second sensing clock (

) And the second restore clock LA ₁ are at the low level 403 and the high level 404, respectively, and the first and second envelop retrospectives 150 and 130 and the first and second latch circuits 170 are respectively. The bit line BL ₀ (BL ₁ ) and the bit line (

) (

) Is amplified to V _CC and V _SS levels, respectively, and the memory cell 78 is restored.

Thereafter, as described above, the output signal is output to the input / output lines 97 and 98 through the transfer transistors 95 and 96.

) 및 행어드레스신호(RA₇)(그리고

)는 모두 로우레벨로 되며 등화클럭(Ø_EQ)은 하이레벨로 되어 프리차아지 싸이클로 된다.When the strobe RAS becomes high at the end of the active cycle t ₉ , the word line select clock Ø _WL01 Ø _WL01 goes low and the row address signal RA ₈ (and

) And hang address signal (RA ₇ ) (and

) Are all at low level and the equalization clock (Ø _EQ ) is at high level to become precharge cycle.

)(

)은 모두 V_CC/2로 되고 비트라인쌍들도 모두 V_CC/2로 프리차아지된다.Therefore, the first and second sensing clocks LA ₂ (LA ₁ ) and the first and second restore clocks (

) (

) Are all V _CC / 2 and the bit line pairs are all precharged to V _CC / 2.

According to the prior art as described above, since the cell array is divided into 1/2 and each of the divided cell arrays has a sensing circuit of enlatch and a restoring circuit of the latch, the bit line is divided so as to be sequentially sensed. It is possible to improve the operating voltage margin and speed by the capacitance between lines and minimize the peak current, so that it is possible to manufacture 1 mega DRAM.

However, the prior art as described above is useful only for the production of one magazine DRAM, and when applied to fabricate four mega DRAM or higher density DRAM, there is a problem that an operation or error occurs.

For example, in the read-modify-write cycle, the data modified in the input / output lines 97 and 98 is transferred to the bit lines 47 and 48 through the isolation transistors 95 and 96. When it is necessary to modify (77) (79) from the high level to the low level and from the low level to the high level, the enlatch circuit 150 and the latch circuit 170 are flipped and then passed through the transfer gate circuit 140. After flipping the latch circuit 110, the latch circuit 130 takes too much time and the operating voltage margin becomes very bad, so that the latch circuits cannot be flipped.

In particular, it is inevitable that the resistances of the bit lines 47, 48, 77, and 78 become high in a high-density memory of 4 mega DRAM or more, and data modification is impossible when the resistance value is 10 kΩ or more.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object of the present invention is to provide a CMOS DRAM having a divided bit line sense amplifier capable of fabricating a high density memory of 4 mega DRAM or more.

A feature of the present invention is that the core circuitry of the CMOS DRAM is configured such that the first latch circuit is disposed closest to the input / output line, and the second latch circuit is disposed closest to the transfer gate circuit. The circuit is disposed adjacent to the en-latch circuit, the second latch circuit is disposed farthest from the input / output line, and the device size of the first latch circuit is the device of the second latch circuit. The CMOS DRAM has a split bit line sense amplifier that is larger than the size of.

Hereinafter, the present invention will be described in detail with reference to an exemplary embodiment of the present invention.

)에 제공되게 연결되고, 분리클럭(Ø_ISO)으로 제어되는 전달 게이트회로(140)에 의해서는 상기 제1비트라인(BL₁)(

)의 데이터가 제2비트라인(BL₀)(

)에 전달되게 연결된다.As shown in FIG. 2, the data of the input and output lines 97 and 98 are first bit lines BL through the transfer transistors 95 and 96 respectively controlled by the column select signal Ø _CD . ₁ ) (

) Is provided to be connected to, is the first bit line (BL ₁₎ by a separate clock (Ø _ISO) transfer gate circuit 140 is controlled by (

Data of the second bit line BL ₀ (

Is connected to).

)에는 제1 엔래치회로(150)가 배치되고 이어서 제1 피래치회로(170)와 제1 하프셀 어레이(160)가 차례로 배치된다.The first bit line BL ₁ of the portion closest to the input / output lines 97 and 98.

), The first latch circuit 150 is disposed, followed by the first latch circuit 170 and the first half cell array 160.

)에는 제2엔래치회로(130)를 배치하고 이어서 제2 하프셀 어레이(120)와 제2 피래치회로(110)가 차례로 배치된다. 즉 상기 제2 피래치회로(110)는 입.출력라인(97)(98)으로부터 가장 멀리 떨어진 곳에 배치된다.In addition, the second bit line BL ₀ of the adjacent portion of the transfer gate circuit 140 (

), The second enlated circuit 130 is disposed, followed by the second half cell array 120 and the second stretched circuit 110. That is, the second stretch circuit 110 is disposed farthest from the input / output lines 97 and 98.

Meanwhile, the device of the first stretch circuit 170 is formed to have a larger size than the device of the second stretch circuit.

The present invention described above will be described with reference to the lead modify light cycle, which is one of the basic cycles of the DRAM. In the operation process of the present invention, the sensing and restoring clock generation circuit 12 of the conventional divided bit line sensing circuit for a 1 mega DRAM is used as it is, so the process of sensing and restoring data is performed in the same manner. Description thereof will be omitted.

)(BL₀)(

)의 데이터가 입.출력라인(97)(98)으로부터 들어오는 수정된 데이터로 바뀌게 된다. 즉 상기 제1,2비트라인(BL₁)(

)(BL₀)(

)의 데이터가 하이레벨에서 로우레벨로 또는 로우레벨에서 하이레벨로 수정이 된다.During the read modulation write cycle of the DRAM, the divided first and second bit lines BL ₁ (

) (BL ₀ ) (

) Is replaced with the modified data coming from the input and output lines 97 and 98. That is, the first and second bit lines BL ₁ (

) (BL ₀ ) (

) Data is modified from high level to low level or from low level to high level.

In this case, the current ratio between the drain and source of the MOS transistor and the MOS transistor of the _{N /} Latch circuit constituting the sensing circuit and the restore circuit is I _P <I _N.

Therefore, the voltage between the bit lines driving the enlatch circuit should be higher than that of the stretch circuit.

)에서의 저항에 의한 영향과 상기 제1비트라인(BL₁)(

)간의 커패시턴스에 의한 영향을 최소한으로 받게 되므로 빠르게 동작된다.Accordingly. The first latch circuit 150 disposed closest to the input / output lines 97 and 98 has a first bit line BL ₁ (

Influence of resistance on the first bit line BL ₁

It is operated quickly because it is minimally affected by the capacitance between.

In addition, the restore operation by the first latch circuit 170 connected to the next stage of the first envelop circuit 150 may include drain-source current I _P of the PMOS transistor constituting the stretch circuit. Since the _N -th transistor transistor-to-source current I _N is smaller than that of the en-latch circuit, the first latch circuit 170 may be flipped quickly without difficulty.

)의 수정된 레벨로 제1 하프 셀 어레이(160)의 해당 셀의 데이터를 수정 한 다음, 전달 게이트회로(140)에 의해 분리되는 제2비트라인(BL₀)(

)의 데이터를 수정하게 된다.After the first bit line BL ₁ (

After modifying the data of the corresponding cell of the first half cell array 160 to the modified level of), the second bit line BL ₀ (separated by the transfer gate circuit 140)

) Will be modified.

In this case, as described above, since the second latch circuit 130 is closest to the transfer gate circuit 140, data sensing does not have a difficulty in the rapid operation of the second latch circuit 130.

On the other hand, the second stretch circuit 110 for restoring data is farthest from the input and output lines 97 and 98, but there is no problem in the rapid flip operation as described above.

In particular, since the size of the transistor constituting the second stretch circuit 110 becomes relatively smaller than the size of the transistor of the first stretch circuit 170, the modified data of the input / output lines 97 and 98 are changed. You can easily write it.

As described above, the present invention improves the sensing speed of the data and the voltage margin between the bit lines, and in particular, the high-speed memory of 4 mega DRAM or more because stable and rapid transfer and restoration of modified data during the read modilite cycle is achieved. It is possible to make a unique effect.

Claims (1)

Separating means for separating the first bit line and the corresponding second bit line by the separating clock; and selecting one memory cell by a word line selection clock having a plurality of memory cells connected to the first bit line. A transfer means for connecting a first cell array, the first bit line and an input / output line, and selecting a first bit line by a column select signal, and a first bit line between the transfer means and the first cell array. And a sensing means of a first N latch circuit for sensing data of the first bit line by a first sensing clock and a first bit line between the first cell array and the sensing means of the first N latch circuit. Restore means of a first P latch circuit for restoring data of the first bit line to a selected memory cell by a first restore clock; and a first bit connected to an end of the first bit line and connected by an equalization clock. First equalizing means for equalizing phosphorus to half of the power supply voltage, second equalizing means connected to an end of the second bit line and equalizing the second bit line to half of the power supply voltage by an equalization clock; A second cell array having a plurality of memory cells connected to a bit line and selecting one memory cell by a word line selection clock, and connected between a second bit line between the second cell array and the separating means; A sensing means of a second N latch circuit for sensing data of a second bit line by a two sensing clock and a second bit line between the second cell array and the second equalizing means and connected by a second restore clock. A partition bit for restoring data of the second bit line to a selected memory cell and having a restore means of a second P latch circuit having a device size smaller than that of the device of the restore means of the first P latch circuit; CMOS DRAM with a sense amplifier.

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