JP3495458B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
For details, see Static Random Access Memory (SRA
M: Static Random Access Memory).

[0002]

2. Description of the Related Art Generally, a high resistance load type memory cell or a CMOS type memory is used for an SRAM. FIG.
As shown in FIG. 3, the high resistance load type memory cell 150 includes N-channel MOS transistors (hereinafter, referred to as NMOS transistors) 151 and 152, a transfer gate 15
3, 154 and high resistances 155, 156. The drain terminals of the NMOS transistors 151 and 152 are connected to the high potential side power source Vcc through the high resistances 155 and 156, respectively, and the source terminals are connected to the low potential side power source Vss.
It is connected to the. NMOS transistors 151 and 15
The gate terminals of 2 are the other NMOS transistor 1
Cross-coupled connection is made to the drain terminals of 51 and 152. The node N21 between the high resistance 155 and the NMOS transistor 151, the high resistance 156 and the NMOS
The node N22 between the transistors 152 is connected to the bit line pair BL and bar BL via transfer gates 153 and 154, respectively. Transfer gate 153,1
The gate terminal of 54 is connected to the word line WL.

In the case of storing data, when the high resistance load type memory cell 150 is selected, first, the word line WL is set to L.
Rise from level to H level. Then, the transfer gates 153 and 154 are turned on, and the node N21,
N22 is connected to the bit line pair BL and bar BL, respectively.
Data to be written is transferred to the bit line pair BL, bar BL,
Data is written in the memory cell 150 via the transfer gates 153 and 154.

For example, bit lines corresponding to data to be written
When BL is at H level and the inverted bit line bar BL is at L level, the node N21 becomes H level and the node N22 becomes L level. Then, the NMOS transistor 151 is turned off and the NMOS transistor 152 is turned on. As a result, the potential of the node N21 changes to the NMOS transistor 1
The potential is settled to the potential determined by the off resistance of 51 and the voltage dividing resistance of the high resistance 155. On the other hand, the potential of the node N22 is
ON resistance of NMOS transistor 152 and high resistance 156
Settles down to the potential determined by the partial pressure resistance of and.

The ON resistance value of the NMOS transistor 152 is R _ON , and the OFF resistance value of the NMOS transistor 151 is R _ON .
_OFF , high resistance 155, 156 resistance value is R _R ,
R _ON <R _R <R _OFF . As a result, the potential of the node N21 becomes higher than the threshold value of the NMOS transistor 152, and the potential of the node N22 becomes higher than that of the NMOS transistor 1.
It becomes lower than the threshold value of 51. Therefore, the word line WL
Even if the L level goes to the standby state, the NMO
S transistor 151 is off, NMOS transistor 1
52 is held on and the data is stored.

On the contrary, depending on the data to be written, the bit line BL
Is at L level and the inverted bit line bar BL is at H level,
Since the node N21 becomes L level and the node N22 becomes H level, the NMOS transistor 151 is turned on and the NMOS
The transistor 152 is turned off. As a result, node N
The potential of 21 is determined by the on resistance of the NMOS transistor 151 and the high resistance 155, and the potential of the node N22 is determined by the off resistance of the NMOS transistor 152 and the high resistance 156. Settle down to the potential. Then, the NMOS transistor 151 is kept on and the NMOS transistor 152 is kept off to store the data.

When reading data, as in the case of writing data, the memory cell 150 is selected, the word line WL rises from the L level to the H level, the transfer gates 153 and 154 are turned on, and the node N2.
1 and N22 are connected to the bit line pair BL and bar BL, respectively. The potential of the bit line pair BL, bar BL is node N2.
According to the potentials of 1 and N22, data is read out by being changed to L level or H level complementarily.

For example, the NM corresponding to the stored data
When the OS transistor 151 is held off and the NMOS transistor 152 is held on, the potential of the node N21 is higher than the potential of the node N22. Therefore, the connected bit line BL is driven in the H level direction,
The inverted bit line bar BL is driven in the L level direction so that the data stored in the memory cell 150 concerned is transferred to the bit line pair BL,
It is transmitted to the bar BL and read.

On the contrary, the NMO corresponding to the stored data
S transistor 151 is on, NMOS transistor 1
When 52 is held off, the bit line BL is driven in the L level direction, the inverted bit line bar BL is driven in the H level direction, and the data stored in the memory cell 150 is bit line pair BL, It is transmitted to the bar BL and read.

When the reading is completed, the word line WL becomes L level and the transfer gates 153 and 154 are turned off. At this time, the nodes N21, N
The potentials of 22 are NMOS transistors 151 and 1, respectively.
It is held at a potential determined by the on or off resistance of 152.

As shown in FIG. 19, the CMOS memory cell 160 includes PMOS transistors 161, 162 and N transistors.
Two Cs consisting of MOS transistors 163 and 164.
It is composed of flip-flop circuits in which input terminals and output terminals of a MOS inverter circuit are connected to each other, and transfer gates 165 and 166. At the time of writing, the data transmitted to the bit line pair BL and bar BL is stored in the flip-flop circuit via the transfer gates 165 and 166 to store the data. On the contrary, at the time of reading, the data latched in the flip-flop circuit is transferred to the transfer gates 165 and 166.
The data is read by transmitting it to the bit line pair BL and bar BL via.

[0012]

The high resistances 155 and 156 of the high resistance load type memory cell 150 are formed of polysilicon or the like, and the areas thereof are NMOS transistors 151 and 152, transfer gates 153 and 15 respectively.
It becomes smaller than 4. Also, high resistance 155, 156
Can be formed above the NMOS transistors 151 and 152 and the transfer gates 153 and 154. Therefore, the memory cell area of the high resistance load type memory cell 150 is an area necessary to form the NMOS transistors 151 and 152 and the transfer gates 153 and 154. On the other hand, the CMOS type memory cell 160 includes PMOS transistors 161 and 162 in the same memory cell.
It is necessary to form the NMOS transistors 163 and 164 and the transfer gates 165 and 166, and the PMOS transistors 161 and 162 and the NMOS transistors 163 and 164 and the transfer gate 16
A separation region is required to separate the components 5 and 166. Therefore, the high resistance load type memory cell 150 can have a smaller memory cell area than the CMOS type memory cell 160. In addition, the high resistance load type memory cell 150
Can be formed in a smaller number of steps as compared with the CMOS type memory cell 160, so that the manufacturing cost is correspondingly reduced.

However, the high resistance load type memory cell 150
Is a data holding current (the NM turned on from the high resistances 155 and 156 in order to store data during standby).
Current flowing through the OS transistors 151 and 152)
is necessary. On the other hand, the CMOS type memory cell 160 is
Since the data is stored by the flip-flop circuit composed of two CMOS inverter circuits, the data holding current becomes extremely small. Therefore, the high resistance load type memory cell 150 consumes more current during standby than the CMOS type memory cell 160.

That is, the high resistance load type memory cells 150 and C
When compared with the MOS type memory cell 160, the high resistance load type memory cell 150 has a problem that the current consumption is large, and the CMOS memory cell 160 has a problem that the memory cell area is large and the manufacturing cost is high.

In recent years, in order to save area, CMO
The PMOS transistor 161, of the S-type memory cell 160,
It is proposed that 162 is formed of a TFT (Thin Film Transistor). The PMOS transistors 161, 162 formed by the TFT are NMOS transistors 16
3, 164, transfer gates 165, 166 can be formed, so that the memory cell area can be reduced. Further, since the data is stored by the flip-flop circuit including the CMOS inverter circuit, it is possible to reduce the current consumption. However, TF
CMO with a general number of process steps for forming T
Since the number of S-type memory cells 160 is larger than that of the S-type memory cells 160, there is a problem that the manufacturing cost increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing a chip area and suppressing an increase in current consumption. .

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

According to a first aspect of the present invention, there are provided two cross-coupled transistors,
A memory cell array including a memory cell including a transfer gate connected to a word line WL and connecting each of the transistors to a bit line pair, and a memory cell array connected to the bit line pair to precharge the bit line pair during standby. It is connected to a precharge circuit and a word line, and when active, selects one word line based on a row address specified from the outside, and when in standby, the transfer gate operates as a load resistance for all word lines. It is a gist that a row decoder for supplying a standby voltage and a standby voltage generation circuit for generating a standby voltage to be supplied to the transfer gate are provided.

[0024] According to a second aspect of the invention, the semiconductor memory device according to claim 1, the standby voltage generator is substantially H-level or L-level of the memory cells
A monitor cell that generates a potential substantially the same as the potential of the node of, and the standby voltage is controlled so that the voltage supplied to the transistor constituting the monitor cell becomes a predetermined voltage. Is the gist.

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

SUMMARY OF] According to the invention described in claim 1, the memory cell array is composed of two transistors connected cross-coupled, a transfer gate for connecting each of both transistors connected to the word line WL to the bit line pairs Memory cells are provided. A precharge circuit is connected to the bit line pair, and the bit line pair is precharged during standby. The word line is connected to the row decoder, and when active, one word line is selected based on the externally specified row address, and during standby, the transfer gate operates as a load resistance for all word lines. Supplied. Then, the standby voltage generation circuit generates the standby voltage supplied to the transfer gate.

According to the second aspect of the present invention, the standby voltage generation circuit has substantially the H level of the memory cell.
The potential that is substantially the same as that of the node at the L or L level.
A monitor cell for generation is provided, and the standby voltage is controlled and output so that the voltage supplied to the transistor forming the monitor cell becomes a predetermined voltage.

[0033]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 3, the SRAM 1 is provided with a memory cell array (memory cell matrix) 2. The memory cell array 2 is composed of memory cells 3 arranged two-dimensionally (row direction and column direction). In the memory cell array 2, the memory cells 3 arranged in the row direction (horizontal direction in FIG. 3) are connected to the word lines WL, and the memory cells 3 arranged in the column direction (vertical direction in FIG. 3) are the bit lines BL. And the inverted bit line bar BL. The bit line BL and the inverted bit line bar BL form one bit line pair BL,
It composes the bar BL.

Each word line WL is connected to a row decoder 4. A row address buffer 5 is connected to the row decoder 4. The chip enable signal bar CE is input to the row decoder 4. The chip enable signal bar CE is a signal for switching the state of the SRAM 1. When the chip enable signal bar CE is at the L level, the SRAM 1 is in a state (active) in which the write operation of the input data Din and the read operation of the output data Dout are possible, and the data is retained when the chip enable signal bar CE is at the H level. It becomes a standby state (standby).

External row address when active
When RA is designated, the row address RA is given from the row address buffer 5 to the row decoder 4. The row decoder 4 receives the row address RA given when it is active.
One word line WL corresponding to is selected.

The row decoder 4 is supplied with the boosted voltage V _PP and the standby voltage V _ST . Boost voltage V _PP
Is a voltage higher than the high potential side power supply Vcc, and the booster circuit 6
Are produced and supplied by. The standby voltage V _ST is a predetermined voltage between the high-potential-side power supply Vcc and the low-potential-side power supply Vss, and is controlled and supplied to a predetermined voltage by the standby voltage generation circuit 7. The row decoder 4 supplies the boosted voltage V _PP input to the selected word line WL when active. On the other hand, in the standby mode, the row decoder 4 supplies the standby voltage V _ST to all word lines WL.

Each bit line pair BL, bar BL is connected to the data bus line pair DB, bar DB via each column switch 8. Each column switch 8 is composed of a pair of NMOS transistors. The gate terminals of the pair of NMOS transistors are connected to each other and to the column decoder 9. When the column address CA is designated from the outside, the column address CA is given from the column address buffer 10 to the column decoder 9. The column address by the column decoder 9
H level activation signal to the column switch 8 corresponding to CA
Send YS. Then, the column switch 8 is turned on by the activation signal YS. Bit line pair BL, bar BL and data bus line pair D via the column switch 8 which is turned on.
B and bar DB are connected, and a pair of bit line pair BL and bar BL corresponding to the column address CA is selected.

Further, each bit line pair BL, bar BL is connected to the high potential side power source Vcc via each precharge circuit 11. Each precharge circuit 11 is composed of a pair of NMOS transistors. The pair of NMOS
The gate terminals of the transistors are connected to each other and the chip enable signal bar CE is input. Therefore, when active, each precharge circuit 11 is turned off and each bit line pair BL, BL is set to the high potential side power source Vcc.
In the standby mode, each precharge circuit 11 is turned on and each bit line pair BL and bar BL is connected to the high potential side power source Vcc. As a result, when the SRAM 1 goes into standby, each bit line pair BL and bar BL is precharged to H level.

The data bus line pair DB and bar DB are input / output circuits 1
Connected to 2. The input / output circuit 12 receives the write enable signal bar WE and the chip enable signal bar CE. The write enable signal bar WE is a signal for switching a data read operation and a data write operation when active. The SRAM 1 has input data Din input when the write enable signal bar WE is at L level.
And a read operation for outputting output data Dout when the write enable signal bar WE is at H level.

Input data Din from the outside is input / output circuit 1
Entered in 2. The input / output circuit 12 is active and changes the levels of the data bus line pair DB and bar DB complementarily in accordance with the input data Din during the write operation. The change in the level of the data bus line pair DB, bar DB is transmitted to the selected bit line pair BL, bar BL via the column switch 8. As a result, the input data Din is written in the memory cell 3 at the intersection of the selected word line WL and the bit line pair BL, BL whose level has changed.

On the other hand, the levels of the bit line pair BL and bar BL are
It changes complementarily by the data stored in a predetermined memory cell 3. The level change of the bit line pair BL and bar BL is changed by the column switch 8 turned on by the activation signal YS.
Is transmitted to the data bus line pair DB and the bar DB via. Then, the input / output circuit 12 outputs the output data Dout corresponding to the change in the level of the data bus line pair DB and bar DB to the outside during the read operation.

As shown in FIG. 1, the memory cell 3 has an NM
OS transistors 21 and 22 and transfer gate 2
3, 24. The gate terminals of the NMOS transistors 21 and 22 are cross-coupled with each other and are connected to the drain terminals of the other NMOS transistors 21 and 22. NMOS transistor 21,
The source terminal of 22 is connected to the low-potential-side power supply Vss. The drain terminals of the NMOS transistors 21 and 22 are connected to the bit line pair BL and bar BL via transfer gates 23 and 24, respectively. The gate terminals of the transfer gates 23 and 24 are connected to the word line WL.

When the chip enable signal CE is at L level and active, the boosted voltage V _PP is supplied to the selected word line WL via the row decoder 4. The boosted voltage V _PP is input to the gate terminals of the transfer gates 23 and 24, and the transfer gates 23 and 24 are turned on. The bit line pair BL and bar BL are complementarily changed to a level corresponding to the input data Din during the write operation. For example, if the bit line BL is at L level and the inverted bit line bar BL is at H level according to the input data Din, the node N1 is at L level and the node N2 is at H level. Then, the NMOS transistor 21 has its gate terminal at H level and is turned on, and the NMOS transistor 22 has its gate terminal at L level and is turned off. As a result, the input data Din is written in the memory cell 3.

Next, the chip enable signal bar CE goes high.
When it becomes a bell and becomes standby, all word lines WL
Is the standby voltage V_STIs supplied. Its standby power
Pressure V _STIs the gate terminal of the transfer gate 23, 24
Is entered. Standby voltage V_STIs the high potential side power supply Vcc
It is controlled to a predetermined voltage between the low potential power supply Vss. Servant
Therefore, the transfer gates 23 and 24 have standby power.
Pressure V_STThe on-resistance will be according to. As a result, the transfer
The gates 23 and 24, as shown in FIG.
Then, the high resistances 25 and 26 are operated.

At this time, the bit line pair BL and bar BL are set to H level (high potential side power supply Vcc) by the precharge circuit 11.
Is precharged to. Therefore, the nodes N1 and N2
Is a high-potential-side power source V via high resistances 25 and 26
Equivalent to connecting to cc. The memory cell 3 shown in FIG. 2 has the same configuration and connection as those of the conventional high resistance load type memory cell 150 when the transfer gates 153 and 154 are off, that is, in the standby state.

By the way, during standby, the nodes N21 and N2 of the conventional high resistance load type memory cell 150 described above are used.
2 is high resistance 155, 156 and NMOS transistor 1
The potentials are settled at the potentials determined by the on-resistances (off-resistances) of 51 and 152 and the voltage dividing resistance. The node N
NMOS transistor 15 depending on the potentials of 21 and N22
1, 152 are held on or off and memory cell 1
The data written in 50 is retained.

Therefore, also in the memory cell 3 of this embodiment, similarly, the potentials of the nodes N1 and N2 are the high resistances 25 and 26 formed by the transfer gates 23 and 24, and the NMOS.
The respective potentials settle down to the potentials determined by the on-resistance (off-resistance) of the transistors 21 and 22 and the voltage dividing resistance. Then, the NMOS transistors 21 and 22 are held on or off by the potentials of the nodes N1 and N2, and the data written in the memory cell 3 is held.

When reading data by becoming active, the boosted voltage V _PP is supplied to the selected word line WL via the row decoder 4 and the transfer gates 23 and 24 are turned on, as in the case of writing data. Become. Nodes N1 and N2 are turned on to transfer gate 23,
The bit line pair BL and the bar BL are connected via 24 respectively. The potential of the bit line pair BL and bar BL is the node N
Data is read out by changing complementarily according to the potentials of 1 and N2.

Next, the supply method and generation of the boosted voltage V _PP and the standby voltage V _ST supplied to the memory cell 3 will be described in detail. First, the supply of the respective voltages V _PP and V _ST will be described in detail. FIG. 5 is a partial circuit diagram of the row decoder 4.
Word line decoder 4a for selecting the word line WL of the book
Is. That is, the word line decoder 4a is provided corresponding to each word line WL.

The word line decoder 4a includes a NAND circuit 3
1, inverter circuit 32, NOR circuit 33, and NMOS
It is composed of transistors 34 to 37. The NAND circuit 31 has a plurality of input terminals, and the row address RA is input to each input terminal. The output terminal of the NAND circuit 31 is connected to the input terminal of the inverter circuit 32. The output terminal of the inverter circuit 32 is connected to the source terminal of the NMOS transistor 34, and the drain terminal of the NMOS transistor 34 is connected to the NMOS transistor 35.
Is connected to the gate terminal of. The gate terminal of the NMOS transistor 34 is connected to the high potential power supply Vcc. The source terminal of the NMOS transistor 35 is connected to the wiring for the boosted voltage V _PP , and the drain terminal is connected to the word line WL.

The output terminal of the inverter circuit 32 is
The NOR circuit 3 is connected to one input terminal of the NOR circuit 33.
The chip enable signal bar CE is input to the other input terminal of 3. The output terminal of the NOR circuit 33 is connected to the gate terminal of the NMOS transistor 36. NMO
The source terminal of the S transistor 36 is connected to the low-potential-side power supply Vss, and the drain terminal is connected to the word line WL.

The chip enable signal bar CE is NM.
It is input to the gate terminal of the OS transistor 37.
The source terminal of the NMOS transistor 37 is connected to the wiring of the standby voltage V _ST , and the drain terminal is the word line WL.
It is connected to the.

The word line decoder 4a has a row address RA
And NMOS based on chip enable signal bar CE
Control one of transistors 35-37 to turn on. The word line WL has an NMO controlled to be turned on.
The boosted voltage V _PP , the low-potential-side power supply Vss, or the standby voltage V _ST is supplied via the S transistors 35 to 37.

Since the row address RA is all at the L level by the row address buffer 5 during standby,
The NAND circuit 31 outputs an H level signal. The H level signal is input to the gate terminal of the NMOS transistor 35 via the inverter circuit 32 and the NMOS transistor 34. Therefore, the NMOS transistor 35 is turned off during standby.

Further, the row address RA becomes an address at which the word line WL is selected when active or an address at which the word line WL is not selected (a word line WL of another word line decoder 4a is selected). Below, the word line WL
The address that is selected is called the selected address, and the word line
Addresses for which WL is not selected are called non-selected addresses. The NAND circuit 31 outputs an L level signal when the row address RA is a selected address, and outputs an H level signal when the row address RA is a non-selected address. The signal output from the NAND circuit 31 is input to the gate terminal of the NMOS transistor 35 via the inverter circuit 32 and the NMOS transistor 34. Therefore, the NMOS transistor 35 is turned on when the row address RA is the selected address and turned off when the row address RA is the non-selected address. And
The boosted voltage V _PP is supplied to the word line WL through the turned-on NMOS transistor 35.

The output of the NAND circuit 31 is input to the NOR circuit 33 via the inverter circuit 32. The chip enable signal bar CE is input to the NOR circuit 33. Therefore, the NOR circuit 33 operates as a chip enable signal bar.
When CE is at H level (standby), L level signal is output, and when chip enable signal CE is at L level, a signal obtained by inverting the output of NAND circuit 31 input through inverter circuit 32 is output.

As described above, the NAND circuit 31 outputs an H level signal when the row address RA is a selected address and an L level signal when the row address RA is a non-selected address. Therefore, during standby, the NOR circuit 33 always outputs an L level signal. On the other hand, when active, the NOR circuit 33 outputs an L level signal when the row address RA is a selected address, and outputs an H level signal when the row address RA is a non-selected address.

The NMOS transistor 36 inputs the signal from the NOR circuit 33 to its gate terminal, and turns on when the signal is at the H level and turns off when the signal is at the L level. Therefore, the NMOS transistor 36 is turned on only when the row address RA is an unselected address and the word line WL is connected to the low-potential-side power supply Vss and becomes L level.

The chip enable signal bar CE is NM.
It is directly input to the gate terminal of the OS transistor 37.
Therefore, the NMOS transistor 37 is turned off when it is active and is turned on when it is on standby.

That is, when active, the boosted voltage V _PP is supplied to the word line WL when the row address RA is the selected address, and the low potential side power supply Vss (L level) is supplied when the row address RA is the non-selected address. Become. On the other hand, in the standby mode, the standby voltage V _ST is supplied to the word line WL.

Next, the booster circuit 6 for generating the boosted voltage V _PP will be described. The booster circuit 6 is a circuit for generating a voltage higher in the positive direction than the high-potential-side power supply Vcc, and is composed of, for example, a bootstrap circuit. The booster circuit 6 is provided to prevent a voltage drop due to the threshold voltage of the transfer gates 23 and 24 forming the memory cell 3 and a reduction in speed of a read operation or the like.

Next, the standby voltage generating circuit 7 for generating the standby voltage V _ST will be described in detail. As shown in FIG. 4, the standby voltage generation circuit 7 includes a monitor voltage generation unit 43 including a monitor cell control circuit 41 and a monitor cell 42, a reference voltage generation unit 44, and a differential amplifier 4.
5, a PMOS transistor 46, and a resistor 47.

The chip control signal CE and the standby voltage V _ST are input to the monitor control circuit 41. The monitor control circuit 41 includes a pseudo bit line pair MBL, a bar.
The monitor cell 42 is connected via the MBL, the pseudo bit line pair MBL, and the bar MBL. The monitor control circuit 41 drives and controls the monitor cell 42 during standby, and
2 generates and outputs a monitor voltage V _mon based on the drive control. That is, the monitor voltage generator 43 generates the monitor voltage V _mon based on the chip enable signal bar CE and the standby voltage V _ST . The monitor voltage V _mon is output to the differential amplifier 45.

The reference voltage generator 44 generates a reference voltage Vref set in advance, and outputs it to the differential amplifier 4
It is designed to output to 5. The differential amplifier 45 inputs the monitor voltage V _mon and the reference voltage Vref. Then, the differential amplifier 45 outputs the two voltages V _mon and Vref.
Are compared and a signal based on the comparison result is output. PMOS transistor 46 and resistor 47
Are connected in series between the high potential side power source Vcc and the low potential side power source Vss, and the gate terminal of the PMOS transistor 46 is connected to the output terminal of the differential amplifier 45. PMOS
The transistor 46 is turned on / off based on the signal output from the differential amplifier 45, that is, the result of comparison between the monitor voltage V _mon and the reference voltage Vref. And PMO
The standby voltage V _ST is output from the node N5 which is a connection point between the S transistor 46 and the resistor 47. The monitor cell control circuit 41 has a standby voltage V _ST.
Is input to drive and control the monitor cell 42 based on the standby voltage V _ST to generate the monitor voltage V _mon . Therefore, the standby voltage V _ST is equal to the monitor cell control circuit 4
1, feedback control is performed by the monitor cell 42, the differential amplifier 45, and the PMOS transistor 46.

As shown in FIG. 7, the monitor cell control circuit 4
1 is an inverter circuit 51-53, the first delay circuit 5
4, second delay circuit 55, and NMOS transistor 5
6, 57. The chip enable signal bar CE is input to the input terminal of the inverter circuit 51,
The output terminal is connected to the pseudo word line MWL via the NMOS transistor 56. Further, the first and second delay circuits 54 and 55 are connected to the output terminal of the inverter 51. The first delay circuit 54 is composed of two inverter circuits 58 and 59 connected in series. First
The chip enable signal bar CE is input to the delay circuit 54 via the inverter circuit 51. The first delay circuit 54 converts the input signal into two inverter circuits 58,
The output is delayed by the delay time determined by 59. The delay time determined by the inverter circuits 58 and 59 is called the first delay time. And
The first delay circuit 54 inputs the chip enable signal bar CE via the inverter circuit 51. Therefore, when the chip enable signal CE rises from the L level to the H level, the first delay circuit 54 outputs the L level signal to the gate terminal of the NMOS transistor 56 with a delay of the first delay time. Conversely, the chip enable signal bar CE
When H level falls from H level to L level, the first delay circuit 54 outputs an H level signal to the gate terminal of the NMOS transistor 56 with a delay of the first delay time.

The NMOS transistor 56 turns on when an H level signal is input to its gate terminal, and turns off when an L level signal is input. Then, the inverter circuit 5 is turned on via the turned-on NMOS transistor 56.
The chip enable signal bar CE inverted by 1 is transmitted to the pseudo word line MWL.

The second delay circuit 55 is composed of four inverter circuits 60 to 63 and a NOR circuit 64 which are connected in series. The chip enable signal bar CE inverted by the inverter circuit 51 is input to one input terminal of the NOR circuit 64 through the inverter circuits 60 to 63, and the chip enable signal inverted by the inverter circuit 51 is input to the other input terminal. The bar CE is directly input.
The output terminal of the NOR circuit 64 is the NMOS transistor 57.
Is connected to the gate terminal of. The drain terminal of the NMOS transistor 57 is connected to the pseudo word line MWL, and the source terminal thereof is supplied with the standby voltage V _ST .

The input signal of the second delay circuit 55 is L
As soon as the level rises from the H level to the H level, the L level signal is output, and when the input signal falls from the H level to the L level, the signal rises from the L level to the H level with a delay time determined by the inverter circuits 60 to 63. Output a signal. The delay time determined by the inverter circuits 60 to 63 is called the second delay time. Then, the second delay circuit 55 inputs the chip enable signal bar CE via the inverter circuit 51. Therefore, in the second delay circuit 55, the chip enable signal bar CE is L
When rising from the level to the H level, the H level signal is output to the gate terminal of the NMOS transistor 57 with a delay of the second delay time. Conversely, the chip enable signal bar
When CE falls from H level to L level, the second delay circuit 55 immediately outputs an L level signal to the gate terminal of the NMOS transistor 57.

The NMOS transistor 57 turns on when an H level signal is input to its gate terminal and turns off when an L level signal is input. Then, the standby voltage V is passed through the turned-on NMOS transistor 57.
_ST is transmitted to the pseudo word line MWL.

The first delay circuit 54 ensures that the first delay time is at the H level after the chip enable signal CE has become the H level and the pseudo word line MWL is surely at the L level. It is set. Second delay circuit 55
Is set so that its second delay time is longer than the first delay time of the first delay circuit 54. That is,
After the chip enable signal bar CE rises to H level and the NMOS transistor 56 is turned off, the NMOS
The transistor 57 is set to be turned on.
Therefore, the chip enable signal bar CE changes from L level to H level.
When you get to the level and enter the standby state, NMO
The S transistor 56 is turned off after the pseudo word line MWL is surely brought to the L level. Next, the NMOS transistor 57 is turned on, and the standby voltage V _ST is supplied to the pseudo word line MWL. When the chip enable signal CE falls from the H level to the L level, the NMOS transistor 57 is immediately turned off and the supply of the standby voltage V _ST to the pseudo word line MWL is stopped.

Inverter circuit 5 is connected to the pseudo bit line MBL.
The chip enable signal bar CE is supplied via 2, 53, and the pseudo bit line bar MBL is connected to the high potential side power source Vcc. Therefore, when the chip enable signal bar CE rises from the L level to the H level to enter the standby state, the pseudo bit line bar MBL becomes the H level. And
When the chip enable signal bar CE falls from H level to L level and becomes active, the pseudo bit line bar MBL becomes L level. The pseudo bit line MBL is always at H level.

As shown in FIG. 6, the monitor cell 42, like the memory cell 3, has NMOS transistors 71 and 72.
And transfer gates 73 and 74. The NMOS transistors 71 and 72 are used for the memory cell 3
Are formed in the same shape as the NMOS transistors 21 and 22 constituting the above. Therefore, the NMOS transistors 21, 22, 71, 72 forming the both cells 3, 42 have the same electrical characteristics.

The transfer gates 73 and 74 are formed in the same shape as the transfer gates 23 and 24 forming the memory cell 3. Therefore, the transfer gates 23, 24, 73, 74 forming the both cells 3, 42 have the same electrical characteristics.

The gate terminals of the NMOS transistors 71 and 72 forming the monitor cell 42 are different from each other.
It is connected to the drain terminals of the transistors 71 and 72. The drain terminals of the NMOS transistors 71 and 72 are connected to the pseudo bit line pair MBL and bar MBL via transfer gates 73 and 74, respectively. NM
The source terminals of the OS transistors 71 and 72 are connected to the low potential power source Vss. Transfer gate 73, 7
The gate terminal of 4 is connected to the pseudo word line MWL.
Then, the monitor voltage Vmon is generated and output from the node N4 between the transfer gate 74 and the NMOS transistor 72.

As shown in FIG. 8, the reference voltage generator 44 comprises a resistor 75 and an NMOS transistor 76. The NMOS transistor 76 is formed so as to have the same electrical characteristics as the NMOS transistors 71 and 72 forming the monitor cell 42, such as the threshold voltage. In addition, the NMOS transistors 71 and 72 forming the monitor cell 42 are the NMO forming the memory cell 3.
It is formed in the same shape as the S transistors 21 and 22 and has the same electrical characteristics. Therefore, the NMOS transistor 76 of the reference voltage generation unit 44 has the same electrical characteristics as the NMOS transistors 21 and 22 that form the memory cell 3. These NMOS transistors 21,
The threshold voltage of 22, 71, 72 and 76 is Vth.

The drain terminal and the gate terminal of the NMOS transistor 76 are connected to each other. Also, NMOS
The drain terminal of the transistor 76 is connected to the high potential side power source Vcc via the resistor 75, and the source terminal is connected to the low potential side power source Vss. Therefore, the NMOS transistor 76 is turned on when the high potential side power supply Vcc is supplied,
The voltage of the gate terminal of the NMOS transistor 76, that is, the voltage of the drain terminal becomes the same voltage as the threshold voltage Vth when the resistance value of the resistor 75 is sufficiently large. Therefore, by adjusting the resistance value of the resistor 75, the NMOS
The voltage of the drain terminal of the transistor 76 can be set to Vth + α. This α is set as a voltage sufficient to keep the NMOS transistors 21 and 22 forming the memory cell 3 on during standby, and is a slight voltage in this embodiment. Therefore, the potential of the source terminal of the NMOS transistor 76 is equal to the threshold voltage Vth.
The voltage is slightly higher. Then, the potential (= Vth + α) of the drain terminal of the NMOS transistor 76 is output as the reference voltage Vref.

As shown in FIG. 4, the differential amplifier 45 receives the reference voltage Vref output from the reference voltage generator 44 at its positive input terminal and the monitor voltage output from the monitor cell 42 at its negative input terminal. V
Input mon, monitor voltage Vmon and reference voltage V
Compare with ref. Then, the differential amplifier 45 outputs H when the monitor voltage Vmon is higher than the reference voltage Vref.
When the monitor voltage Vmon is lower than the reference voltage Vref, an L level signal is output to the gate terminal of the PMOS transistor 46.

The PMOS transistor 46 is turned on when an L level signal is input to its gate terminal, and the PMOS transistor 46 is turned on.
Standby voltage V _ST is output from node N5 between S transistor 46 and resistor 47. This standby voltage V _ST is supplied to the monitor cell control circuit 41. Then, the standby voltage V _ST is input by the monitor cell control circuit 41 to the gate terminals of the transfer gates 73 and 74 configuring the monitor cell 42 via the pseudo word line MWL during standby.

For example, when the monitor voltage Vmon becomes higher than the reference voltage Vref, the differential amplifier 45 outputs an H level signal and the HMO level signal causes the PMO.
The S transistor 46 is turned off. As a result, the standby voltage V _ST drops. On the contrary, when the monitor voltage Vmon becomes lower than the reference voltage Vref, the differential amplifier 45
Outputs an L level signal, and the L level signal turns on the PMOS transistor 46. as a result,
The standby voltage V _ST rises.

As described above, the standby voltage V _ST is
In the standby mode, the monitor cell control circuit 41 supplies the gate terminals of the transfer gates 73 and 74 forming the monitor cell 42 through the pseudo word line MWL. The transfer gates 73 and 74 have on-resistance according to the supplied standby voltage V _ST . Then, the potential of the node N4 between the transfer gate 74 and the NMOS transistor 72 is output as the monitor voltage Vmon. Therefore, the standby voltage V _ST is controlled so that the monitor voltage Vmon becomes the same voltage as the reference voltage Vref generated by the reference voltage generator 44.

By the way, when active, the pseudo bit line MBL is supplied with the chip enable signal CE (L level), and the pseudo bit line MBL is supplied with the high potential side power source Vcc.
Is being supplied. Therefore, the node N3 is at L level and the node N4 is at H level. Then, the NMOS transistor 71 is turned on and the NMOS transistor 72 is turned off.

Next, in the standby mode, the transfer gates 73 and 74 have ON resistances corresponding to the supplied standby voltage V _ST . Therefore, the potential of the node N3 settles to a potential determined by the voltage dividing resistance of the on resistance of the transfer gate 73 and the on resistance of the NMOS transistor 71, and the potential of the node N4 is set to the on resistance of the transfer gate 74 and the NMOS. The potential of the transistor 72 settles down to a potential determined by the voltage dividing resistance of the transistor 72. At this time, the potential of the node N4 becomes slightly higher than the threshold voltage of the NMOS transistors 71 and 72. The NMOS transistor 71 is connected to the node N4
Is kept on by the potential of the node N3, the node N3 is kept at the L level, and the NMOS transistor 72 is kept off by the potential of the node N3. Then, the monitor voltage generator 4
3 outputs the potential of the node N4 as the monitor voltage Vmon.

The potential of the node N4 of the monitor cell 42 becomes the same as that of the node N2 when the bit line pair BL and BL are at the L level and the H level, respectively, in accordance with the input data Din, and conversely the bit line pair BL and the bar. When BL is H level and L level, respectively, it is the same as the node N1. That is, the monitor cell 42 is in the same state as when the data was written in the memory cell 3. Then, when it goes into standby, the transfer gate 2 that constitutes the memory cell 3
Similar to 3, 24, the transfer gates 73, 74 forming the monitor cell 42 have on-resistance according to the standby voltage V _ST . Therefore, the monitor voltage Vmon output from the node N4 becomes the same as the potential of the node N2 of the memory cell 3. That is, the potentials of the nodes N1 and N2 of the memory cell 3 are detected by the potential of the node N4 of the monitor cell.

The standby voltage V _ST is controlled so that the potential of the node N2 of the memory cell 3 becomes the same potential as the reference voltage Vref generated by the reference voltage generator 44. Then, the reference voltage Vref
Is the threshold voltage Vth + of the NMOS transistor 76.
That is, α, that is, the threshold voltage Vth + α of the NMOS transistors 23 and 24 forming the memory cell 3. Therefore, the reference voltage Vref becomes a voltage slightly higher than the threshold voltage Vth of the NMOS transistors 21 and 22 forming the memory cell 3. Then, the nodes N1 and N2
The potentials of the NMOS transistors 21 and 22 are turned on.
Since the voltage is slightly higher than the threshold voltage Vth of
The current flowing through the turned-on NMOS transistors 21 and 22 becomes the minimum. That is, the data holding current flowing through the memory cell 3 during standby is minimized.

Next, the SRAM 1 configured as described above
The action of will be explained. When writing data, as shown in FIG. 10, a row address RA externally designated is selected to the row decoder 4 via the row address buffer 5, and a column address CA is selected to the column decoder 9 via the column address buffer 10. Given as an address.
When the chip enable signal bar CE falls to L level, the word line decoder 4a corresponding to the selected address is activated, the boosted voltage V _PP is supplied to the word line WL, and the level of the word line WL rises.

Next, when the write enable signal bar WE falls, the input / output circuit 12 externally receives the input data Din.
Enter. Then, the input / output circuit 12 complementarily changes the data bus line pair DB, bar DB to a level corresponding to the input data Din. The change in the level of the data bus line pair DB, bar DB is transmitted to the bit line pair BL, bar BL selected via the column switch 8 which is turned on by the activation signal YS output according to the column address CA. Transmitted. The input data Din is written to the memory cell 3 connected to the intersection of the bit line pair BL, bar BL and the word line WL to which the boosted voltage V _PP is supplied.

Next, in the standby state, since the chip enable signal bar CE is at the H level for each bit line pair BL and bar BL, the precharge circuit 11 supplies the high potential side power source Vcc to the H level. Become. A standby voltage V _ST is supplied from the row decoder 4 to each word line WL, and each word line WL is connected to the gate terminals of the transfer gates 23 and 24 which form the memory cell 3. Therefore, the transfer gates 23 and 24 have ON resistances corresponding to the standby voltage V _ST supplied to the gate terminals. Then transfer gate 2
As shown in FIG. 2, 3 and 24 operate as high resistances 25 and 26 connected between the drain terminals of the NMOS transistors 21 and 22 and the bit line pair BL and bar BL.

At this time, the high potential side power source Vcc is supplied to each bit line pair BL and bar BL. Therefore, the potential of the node N1 is obtained by dividing the potential between the high-potential-side power supply Vcc and the low-potential-side power supply Vss by the voltage dividing resistor including the ON resistance (or OFF resistance) of the NMOS transistor 21 and the high resistance 25. Settle down to the potential. On the other hand, the potential of the node N2 is NMOS
The potential divided by the voltage dividing resistor including the off resistance (or on resistance) of the transistor 22 and the high resistance 26 settles down. That is, the transfer gates 23 and 24 operate as high resistances 25 and 26 similar to the high resistances 155 and 156 that form the conventional high resistance load type memory cell 150 in the standby state, and the high resistances 25 and 26 and the NMOS transistor 21. The data is held by the ON resistances (or OFF resistances) of 22 and 22.

Therefore, the conventional CMOS type memory cell 16
As in 0, it is not necessary to provide the PMOS transistors 161, 162, and the data can be held only by the NMOS transistors 21, 22 and the transfer gates 23, 24. As a result, the memory cell area of the memory cell 3 can be made smaller than that of the conventional CMOS memory cell 160.

At this time, the standby voltage V _ST is feedback-controlled so that the monitor voltage Vmon and the reference voltage Vref are the same voltage. The NMOS transistors 71 and 72 that form the monitor cell 42 are the NMOS transistors 21 and 22 that form the memory cell 3.
Are formed in the same shape as, and their electrical characteristics are the same. The NMOS transistor 76 that constitutes the reference voltage generator 44 is formed to have the same electrical characteristics as the NMOS transistors 21 and 22 that constitute the memory cell 3. That is, the NMOS transistors 21, 22, 71, 72 and 76 have the same threshold voltage Vth.

The standby voltage V _ST is controlled so that the monitor voltage Vmon matches the reference voltage Vref. Therefore, the high resistances 25 and 26, that is, the on resistances of the transfer gates 23 and 24 are
The potential of N2 is the reference voltage Vref (monitor voltage Vmo
n)). Then, the nodes N1 and N
Since the potential of 2 is a voltage slightly higher than the threshold voltage Vth of the NMOS transistors 21 and 22, the data holding current flowing through the turned-on NMOS transistors 21 and 22 becomes the minimum.

By the way, the resistance values of the high resistances 155 and 156 forming the conventional high resistance load type memory cell 150 are set such that data is held even if a necessary data holding current changes due to process variations and temperature changes. Is set as a resistance value with a certain margin. On the other hand, in the SRAM 1 of the present embodiment, the standby voltage V _ST is controlled so that the drain voltage of the NMOS transistors 21 and 22 forming the memory cell 3 is slightly higher than the threshold voltage Vth of the transistors 21 and 22.
Causes the transfer gates 23 and 24 to have high resistance 25,
It was made to operate as 26. Therefore, the data holding current flowing through the transfer gates 23 and 24 and the turned-on NMOS transistors 21 and 22 is smaller than the data holding current required for the conventional high resistance load type memory cell 150. As a result, the current consumption of the SRAM 1 is the SRA of the conventional high resistance load type memory cell 150.
Less than M.

When reading data, as shown in FIG. 9, as in the case of writing, when the chip enable signal bar CE falls to the L level, the word line WL selected based on the row address RA externally specified is selected. Boosted voltage V _PP
Is supplied to raise the level of the word line WL. Then, each bit line pair BL, BL changes to a level according to the data stored in the memory cell 3 connected to the word line WL to which the boosted voltage V _PP is supplied.

At this time, the bit line pair BL, bar BL and the data bus line pair DB, bar DB selected by the activation signal YS output by the column address CA due to the fall of the chip enable signal bar CE are changed to the column. Switch 8
Connected via. Then, the change in the level of the selected bit line pair BL, bar BL changes with the data bus line pair DB, bar.
It is transmitted to DB. The input / output circuit 12 outputs the output data Dout according to the level change of the data bus line pair DB and bar DB.
Is output to the outside.

As described above, according to this embodiment,
During standby, the standby voltage V _ST is applied to the gate terminals of the transfer gates 23 and 24, and the high potential side power source V
The bit line pair BL precharged to cc and the high resistances 25 and 26 connected to the bar BL are operated. As a result, the memory cell 3 is replaced with the NMOS transistors 21 and 2.
2 and the transfer gates 23 and 24, the conventional CMOS memory cell 160
The area of the memory cell can be made smaller than that of. Further, when compared with the conventional high resistance load type memory cell 150, the high resistances 155 and 156 and the high potential side power supply Vcc, NMO.
The memory cell area of the memory cell 3 of this embodiment can be reduced by the area for forming contact holes for connecting to the S transistors 151 and 152. Furthermore, since the high resistances 155 and 156 of the conventional high resistance load type memory cell 150 can be omitted, the number of process steps can be reduced accordingly.

In the standby mode, the standby voltage V _ST applied to the gate terminals of the transfer gates 23 and 24 is controlled to set the potentials of the nodes N1 and N2 to the reference voltage Vref, that is, the threshold values of the NMOS transistors 21 and 22. The voltage is set to be slightly higher than the voltage Vth. As a result, since the data holding current flowing in the memory cell 3 can be minimized, the current consumption can be reduced as compared with the conventional high resistance load type memory cell 150. (Second Embodiment) A second embodiment of the present invention will be described below with reference to FIGS.

In the present embodiment, the same components as those in the first embodiment are designated by the same reference numerals, detailed description thereof will be omitted, and only the points different from the first embodiment will be described in detail.
The present embodiment differs from the first embodiment in that a memory cell 90 shown in FIG. 12 is provided instead of the memory cell 3. With the change of the memory cell 90, a monitor cell control circuit 110 shown in FIG. 16 is provided in place of the monitor cell control circuit 41, and a monitor cell 42 is shown in FIG.
The monitor cell 120 shown in FIG. A reference voltage generation unit 130 shown in FIG. 15 is provided instead of the reference voltage generation unit 44. And FIG.
The standby voltage generation circuit 7 shown in FIG.
It is designed to generate and output _ST 1. The standby voltage V _ST 1 is supplied to each memory cell 90 via the row decoder 4 and each word line WL during standby.

First, the memory cell 90 will be described.
As shown in FIG. 12, the memory cell 90 is composed of a PMOS transistor 91, an NMOS transistor 92, and transfer gates 93 and 94. PMO
The source terminal of the S transistor 91 is connected to the high-potential-side power supply Vcc, and the drain terminal is connected to the gate terminal of the NMOS transistor 92. NMOS transistor 9
The source terminal of 2 is connected to the low-potential-side power supply Vss, and the drain terminal is connected to the gate terminal of the PMOS transistor 91. A node N6 between the drain terminal of the PMOS transistor 91 and the gate terminal of the NMOS transistor 92 is connected via the transfer gate 93 to the bit line BL.
It is connected to the. A node N7 between the gate terminal of the PMOS transistor 91 and the drain terminal of the NMOS transistor 92 is connected to the inverted bit line bar BL via the transfer gate 94. The transfer gates 93 and 94 are NMOS transistors, and the gate terminals of both transfer gates 93 and 94 are connected to the word line WL.

A precharge circuit 100 is connected to the bit line pair BL, bar BL. The precharge circuit 100 is composed of a pair of NMOS transistors and is
The gate terminals of the S transistors are connected to each other and the chip enable signal CE is input. When the H-level chip enable signal CE is input in the standby state, both NMOS transistors are turned on. Then, the bit line BL is connected to the low potential side power source Vss, and the inverted bit line bar BL is connected to the high potential side power source Vcc. As a result, the bit line BL is precharged to L level and the inverted bit line bar BL is precharged to H level.

With respect to the memory cell 90 configured as described above, when it is active as in the first embodiment, the boosted voltage V _{PP is} applied to the selected word line WL via the row decoder 4.
Is being supplied. The boosted voltage V _PP is input to the gate terminals of the transfer gates 93 and 94, and the transfer gates 93 and 94 are turned on. Then, the bit line pair BL, bar BL receives the input data Din during the write operation.
The level changes in a complementary manner. For example, if the bit line BL is at H level and the inverted bit line bar BL is at L level according to the input data Din, the node N6 becomes H level and the node N7 becomes L level. Then the PMOS
The transistor 91 has its source terminal at L level and is turned on, and the NMOS transistor 92 has its gate terminal at H level and is turned on. As a result, the input data Din is written in the memory cell 90.

Next, in the standby mode, the standby voltage V _ST 1 is supplied to all the word lines WL, and the transfer gates 93 and 94 have ON resistances corresponding to the standby voltage V _ST 1. As a result, as shown in FIG. 13, the transfer gates 93 and 94 have high resistances 95 and 95, respectively.
The memory cell 90 operates as a PM.
It is composed of an OS transistor 91, an NMOS transistor 92, and high resistances 95 and 96.

At this time, the bit line pair BL and bar BL are precharged by the precharge circuit 100 to L level (low potential side power supply Vss) and H level (high potential side power supply Vcc), respectively. Therefore, the node N6 is equivalent to being connected to the low potential side power source Vss via the high resistance 95, and the node N7 being connected to the high potential side power source Vcc via the high resistance 96. Since both MOS transistors 91 and 92 are on, the nodes N6 and N7 are held at H level and L level, respectively, and the data written in the memory cell 90 is held.

On the other hand, according to the input data Din, the bit line BL
Is at the L level and the inverted bit line bar BL is at the H level, the node N6 is at the L level and the node N7 is at the H level. Then, the PMOS transistor 91 has its gate terminal at H level and turns off, and the NMOS transistor 92 has its gate terminal at L level and turns off. When in standby, the transfer gates 93 and 94 operate as high resistances 95 and 96 having resistance values corresponding to the standby voltage V _ST 1, respectively. The bit line pair BL and bar BL are precharged to the L level and the H level, respectively, by the precharge circuit 100, the node N6 is connected to the low potential side power source Vss through the high resistance 95, and the node N7 has the high resistance. High potential side power source Vcc via 96
Is equivalent to being connected to. Then, the potential of the node N6 settles to a potential determined by the voltage dividing resistance of the off resistance of the PMOS transistor 91 and the high resistance 95 of the transfer gate 93, and the potential of the node N7 is high resistance 96 of the transfer gate 94. And the off resistance of the NMOS transistor 92 settles down to the potential determined by the voltage dividing resistance.

At this time, assuming that the threshold voltage of the PMOS transistor 91 is Vtp, the threshold voltage of the NMOS transistor 92 is Vtn, and the potentials of the nodes N6 and N7 are VN6 and VN7, respectively, VN6 <Vtn, Vcc- | Vtp | <V
It will be N7. As a result, both MOS transistors 91, 92
Is held off and the data written in the memory cell 90 is held.

Since the operation of reading the data held in the memory cell 90 by becoming active is the same as that of the first embodiment, the description thereof will be omitted. Next, the supply and generation of the standby voltage V _ST 1 will be described in detail.

As shown in FIG. 16, in the monitor cell control circuit 110, the inverter circuits 52 and 53 are omitted as compared with the monitor cell control circuit 41 of the first embodiment, and the pseudo bit line MBL is connected to the low potential side power source Vss. It is connected. Therefore, the pseudo bit line MBL is always at the L level and the pseudo bit line bar MBL is always at the H level. Then, as in the first embodiment, the pseudo word line MWL is at H level when active, and the standby voltage V _ST 1 is supplied during standby.

As shown in FIG. 14, the monitor cell 120
Is similar to the memory cell 90, the PMOS transistor 1
21, an NMOS transistor 122, and transfer gates 123 and 124. In addition, each of the transistors 121 and 12 that form the monitor cell 120
2. The transfer gates 123 and 124 are formed in the same shape as the transistors 91 and 92 and the transfer gates 93 and 94, respectively, which form the memory cell 90. Therefore, the monitor cell 120 has the same electrical characteristics as the memory cell 90. Then, the monitor cell 120
Is the gate terminal of the PMOS transistor 121 and the NMO
Node N between the drain terminal of the S transistor 122
The monitor voltage Vmon1 is output from 9.

As shown in FIG. 15, the reference voltage generator 130 is composed of resistors 131 and 132, and the resistors 131 and 132 are connected in series between the high potential side power source Vcc and the low potential side power source Vss. ing. The reference voltage generator 130 includes a node N10 between the resistors 131 and 132.
Therefore, the voltage between the high potential side power source Vcc and the low potential side power source Vss is output as the reference voltage Vref1 by the voltage dividing resistor of the resistors 131 and 132.

The values of the resistors 131 and 132 are set to the potential of the node N10 by the resistance division, that is, the reference voltage Vref1.
However, the threshold voltage of the PMOS transistor 121 is Vtp
Then, Vref1> Vcc- | Vtp | is set. In this embodiment, the reference voltage Vref1
Is set to slightly exceed Vcc- | Vtp |.

Similar to the first embodiment, the differential amplifier 45 shown in FIG. 4 compares the monitor voltage Vmon1 output from the monitor cell 120 with the reference voltage Vref1 output from the reference voltage generator 130, and The PMOS transistor 46 is on / off controlled based on the comparison result. Then, the standby voltage V _ST 1 is output from the node N5 between the PMOS transistor 46 and the resistor 47. The standby voltage V _ST 1 is supplied to the word line WL and the pseudo word line MWL by the row decoder 110 during standby,
Monitor voltage Vmon1 on the basis of the standby voltage V _ST 1
Is generated.

That is, the standby voltage V _ST 1 is controlled so that the PMOS transistor 121 to which the monitor voltage V mon1 is applied is slightly turned off, and the row decoder 110 is controlled.
Is supplied to each word line WL in the standby state via. The transfer gates 93 and 94 which form each memory cell 90 have resistors 95 and 96 as shown in FIG. 13 due to the standby voltage V _ST 1 supplied to the word line WL.
To work as. Therefore, the node N7 of the memory cell 90
Is equal to the potential of the node N9 of the monitor cell 120, that is, the monitor voltage Vmon1. As a result, as in the first embodiment, the data written in the memory cell 90 is retained even during standby.

At this time, the PM forming the memory cell 90
Since the OS transistor 91 is formed in the same shape as the PMOS transistor 121 forming the monitor cell 120, their threshold voltages are the same. The threshold voltage of these PMOS transistors 91 and 121 is set to the threshold voltage Vtp. Then, the potential of the node N7 of the memory cell 90 becomes a potential slightly higher than Vcc- | Vtp | due to the potential equal to the monitor voltage Vmon1, that is, the high potential side power supply Vcc and the threshold voltage Vtp of the PMOS transistor 121. . Then, P constituting the monitor cell 120
The MOS transistor 121 and the PMOS transistor 91 forming the memory cell 90 have the same characteristics. Therefore, the current flowing through the high resistance 95 composed of the turned-on PMOS transistor 91 and the transfer gate 93, that is, the data holding current is minimized. Therefore, the current consumption during standby can be suppressed.

As described above, also in this embodiment, the memory cell 90 can be constituted by the PMOS transistor 91, the NMOS transistor 92, and the transfer gates 93 and 94, as in the first embodiment. As a result, as compared with the NMOS transistor 21 of the first embodiment, P
Since the area occupied by the element is larger in the MOS transistor 91, the memory cell area is larger, but the conventional CM
The memory cell area can be made smaller than that of the OS type memory cell 160. In addition, since the data holding current for holding the data in the standby state can be minimized by controlling the standby voltage V _ST 1 applied to the gate terminals of the transfer gates 123 and 124, the conventional high resistance load can be achieved. Current consumption can be reduced as compared with the memory cell 150 of the type. (Third Embodiment) A third embodiment of the present invention will be described below with reference to FIG.

In the present embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 17, the source terminals of the NMOS transistors 21 and 22 constituting each memory cell 3 of the first embodiment are commonly connected and the capacitor 141 is also provided.
Of the capacitor 141, and the other end of the capacitor 141 is connected to the low potential side power source Vss. The capacitor 141 is formed to have a relatively large capacity, and is about 1 nF in this embodiment. An NMOS is connected in parallel to the capacitor 141.
The transistors 142 and 143 are connected. That is,
The drain terminals of the NMOS transistors 142 and 143 are connected to the node N11 between the source terminals of the NMOS transistors 142 and 143 and the capacitor 141,
The source terminals of the NMOS transistors 142 and 143 are connected to the low potential power source Vss. The chip enable signal CE is input to the gate terminal of the NMOS transistor 142 via the inverter circuit 144. NM
The gate terminal and the drain terminal of the OS transistor 143 are connected to each other.

When in standby, the NMOS transistor 142 is turned off because the chip enable signal bar CE inverted by the inverter circuit 144 is input to the gate terminal of the NMOS transistor 142.

For example, the NMOS transistor 21 is turned on and the NMOS transistor 22 is turned off according to the written input data Din. At this time, the standby voltage V _ST is applied to the gate terminals of the transfer gates 23 and 24, respectively, and the high resistance 2 shown in FIG. 2 of the first embodiment is shown.
5 and 26. Then, the potential of the node N1 becomes a potential determined by the voltage dividing resistance of the high resistance 25 and the ON resistance of the NMOS transistor 21,
The potential of 2 is a potential determined by the voltage dividing resistance of the high resistance 26 and the off resistance of the NMOS transistor 23.

At this time, the data holding current flowing from the bit line BL through the high resistance 25 (transfer gate 23) and the turned-on NMOS transistor 21 flows into the electrode of the capacitor 141 and is stored in the capacitor 141. It does not consume current. Therefore, the current consumption can be further reduced as compared with the first embodiment.

By the way, the standby voltage V _ST may fluctuate due to the margin of the process for manufacturing the SRAM and the data holding current flowing through the memory cell 3 may increase. Also in this case, similarly, the data holding current flowing from the bit line BL through the high resistance 25 and the turned-on NMOS transistor 21 flows into the electrode of the capacitor 141 and is stored in the capacitor 141. I won't.

The NMOS transistor 143 is provided to set the upper limit (limit) of the potential that rises due to the electric charge stored in the capacitor 141. And N
The threshold voltage of the MOS transistor 143 is set and formed so as to be lower than the threshold voltage of the NMOS transistors 21 and 22 which form the memory cell 3. Therefore, when the potential of the node N11 rises due to the data holding current flowing from the bit line BL (bar BL),
The NMOS transistor 143 is turned on before the NMOS transistors 21 and 22.

When the potential of the node N11 becomes higher than the threshold voltage of the NMOS transistors 21 and 22, NMO
The S transistors 21 and 22 are turned on. Then, the potentials of the nodes N1 and N2 are lowered, and the data written in the memory cell 3 is destroyed. NMOS transistor 1
When 43 is turned on, a current flows from the capacitor 141 through the NMOS transistor 143 to limit the rise of the potential of the node N11. As a result, the potential of the node N11 does not rise until the NMOS transistors 21 and 22 are turned on, so that the data written in the memory cell 3 is retained without being destroyed. Next, when activated, the gate terminal of the NMOS transistor 142 receives the chip enable signal CE inverted by the inverter circuit 144, that is, the H level signal.
The MOS transistor 142 is turned on. Then, the node N11 is connected to the low-potential-side power supply Vss via the NMOS transistor 142, and the electric charge stored in the capacitor 141 is discharged. As a result, the low-potential-side power supply Vss is applied to the source terminals of the NMOS transistors 21 and 22 forming the memory cell 3. Then, as in the first embodiment, the input data Din is written in the memory cell 3 by the change in the level of the bit line pair BL and bar BL.

As described above, according to this embodiment,
In addition to the effects of the first embodiment, even if the standby voltage V _ST changes due to process variations or the like, an increase in current consumption can be suppressed.

The present invention is not limited to the above embodiments, but may be carried out as follows. 1) In each of the above embodiments, the memory cell array 2 is divided into a plurality of blocks, and the standby voltage generation circuit 7 is provided for each of these blocks. Then, the standby voltage V _ST supplied to the memory cells included in the block is generated by each standby voltage generation circuit 7. According to this configuration, although the chip area increases, the data holding current of the memory cells 3 and 90 can be controlled for each block at the time of standby, so that it is possible to suppress an increase in current consumption due to variations in the chip.

2) In the third embodiment, the NMOS transistor 143 serving as a limiter is composed of a plurality of MOS transistors connected in series. Then, it becomes possible to finely set the limit for increasing the potential of the node N11.

3) In the third embodiment, the memory cell array 2 is divided into a plurality of blocks and the capacitors 141 corresponding to the respective blocks are formed. Then, the capacitors 141 corresponding to the memory cells 3 included in the block are respectively provided.
Connect to and carry out.

4) In the first embodiment, the transfer gates 23 and 24 are formed so as to be turned off based on the standby voltage V _ST during standby. Similarly, in the second embodiment, the transfer gate 93 on the basis of the standby voltage V _ST 1 during standby,
It is formed so that 94 is turned off.

5) In each of the above embodiments, the precharge circuits 11 and 100 are composed of a pair of PMOS transistors, and the inverted chip enable signal CE is supplied to the gate terminals of both PMOS transistors.

6) In each of the above embodiments, the present invention is applied to SRAM using bipolar transistors. In addition, in this specification, a member according to the configuration of the invention is defined as follows.

Transistors include field effect transistors (FETs) and bipolar transistors. FET
Are not only MOS transistors, but also field effect transistors (FETs) with MIS structure, insulated gate FETs.
Not only (IGFET) but also JFET is included. Bipolar transistors include NPN type transistors and PNP type transistors.

[0130]

As described in detail above, according to the present invention, a semiconductor memory device capable of reducing the chip area and suppressing the increase in current consumption can be provided. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory cell of a first embodiment embodying the present invention.

FIG. 2 is an equivalent circuit diagram of the memory cell of the first embodiment.

FIG. 3 is a block circuit diagram of SRAM.

FIG. 4 is a block circuit diagram of a standby voltage generation circuit.

FIG. 5 is a partial circuit diagram of a row decoder.

FIG. 6 is a circuit diagram of a monitor cell of the first embodiment.

FIG. 7 is a circuit diagram of a monitor cell control circuit according to the first embodiment.

FIG. 8 is a circuit diagram of a reference voltage generation circuit according to the first embodiment.

FIG. 9 is a waveform diagram for explaining an operation at the time of reading.

FIG. 10 is a waveform diagram for explaining an operation during writing.

FIG. 11 is a waveform diagram for explaining the operation of the standby voltage generation circuit.

FIG. 12 is a circuit diagram of a memory cell according to a second embodiment.

FIG. 13 is an equivalent circuit diagram of the memory cell of the second embodiment.

FIG. 14 is a circuit diagram of a monitor cell according to a second embodiment.

FIG. 15 is a circuit diagram of a reference voltage generation circuit according to a second embodiment.

FIG. 16 is a circuit diagram of a monitor cell control circuit according to a second embodiment.

FIG. 17 is a circuit diagram of a memory cell of a third embodiment.

FIG. 18 is a circuit diagram of a high resistance load type memory cell.

FIG. 19 is a circuit diagram of a CMOS memory cell.

[Explanation of symbols]

2 memory cell array 3 memory cell 4 row decoder 21, 22 NMOS transistor 23, 24 transfer gate 25, 26 high resistance as load resistance 40 standby voltage generation circuit 41, 110 monitor cell control circuit 42, 120 monitor cell 43 monitor voltage generation section 44, Reference voltage generator 45 Differential amplifier 46 PMOS transistor 47 Resistance 91 PMOS transistor 92 NMOS transistors 93, 94 Transfer gates 95, 96 High resistance 141 as load resistance 142 Capacitor 142 NMOS transistor 143 NMOS transistor BL, bar BL as limit transistor bit line pair Vmon, Vmon1 monitor voltage Vref, Vref1 reference voltage V _ST, V _ST 1 standby voltage WL the word line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-59-172194 (JP, A) JP-A-62-3485 (JP, A) JP-A-61-255592 (JP, A) JP-A-2- 183495 (JP, A) JP-A-5-342880 (JP, A) JP-A-62-76097 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/41-11 / 419

Claims (2)

(57) [Claims] 1. A memory cell array including a memory cell including two transistors that are cross-coupled and a transfer gate that is connected to a word line WL and respectively connects the transistors to a bit line pair, and a bit line. A precharge circuit connected to the pair, which precharges the bit line pair during standby, and a word line, which is connected to the word line and selects one word line based on a row address externally specified when active,
In a standby mode, a row decoder that supplies a standby voltage to which the transfer gate operates as a load resistance for all word lines, and a substantially H level or L level node of the memory cell.
A semiconductor memory device comprising: a standby voltage generation circuit that generates a standby voltage to be supplied to a transfer gate based on a potential that is substantially the same as the potential of the battery. 2. The semiconductor memory device according to claim 1, wherein the standby voltage generation circuit is substantially the same as the memory cell.
Substantially the same potential as the H level or L level node
A semiconductor memory device comprising a monitor cell for generating, and controlling a standby voltage so that a voltage supplied to a transistor constituting the monitor cell becomes a predetermined voltage.