JP5666883B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to an active matrix liquid crystal display device.

  In an active matrix liquid crystal display device, liquid crystal is sandwiched between a common electrode and a plurality of pixel electrodes. Each pixel electrode is provided with an active element such as a TFT (Thin Film Transistor), and it is possible to control whether or not to set the voltage of the source wiring to the pixel electrode using the active element.

  The common electrode is set to a predetermined potential, and each pixel electrode is set to a potential corresponding to each pixel value of the display image. Here, a state in which the potential of the pixel electrode is higher than the potential of the common electrode is referred to as positive polarity. A state in which the potential of the pixel electrode is lower than the potential of the common electrode is referred to as negative polarity.

FIG. 35 is an explanatory diagram showing an example of the potential of the common electrode and the potential for setting the pixel to white or black with each polarity. Here, the case of normally white will be described as an example. The potential of the common electrode referred to as _{V COM. V} pb shown in FIG. _{35, V pw, V COM,} V nw, V nb each represent a _potential, and a _{V nb <V nw <V COM} <V pw <V pb. When the pixel is displayed in black with positive polarity, the potential of the source line connected to the pixel is set to V _pb , and when the pixel is displayed in white with positive polarity, the source line connected to the pixel What is necessary is _just to set an electric potential to _Vpw . In addition, when a pixel is set to be halftone display with positive polarity, the potential of the source line connected to the pixel may be set higher than V _{pw and} lower than V _pb . When the pixel is displayed in black with negative polarity, the potential of the source line connected to the pixel is set to V _nb , and when the pixel is displayed in white with negative polarity, the source connected to the pixel The line potential may be set to V _nw . Further, in the case where a pixel is set to a halftone display with a negative polarity, the potential of the source line connected to the pixel may be set to a potential lower than V _{nw and} higher than V _nb .

  In an active matrix liquid crystal display device, in order to prevent crosstalk, it is preferable to drive so that pixels having the same polarity are less likely to be continuously arranged. FIG. 36 is an explanatory diagram showing a general liquid crystal display device. As shown in FIG. 36, the pixel electrodes 50 are arranged in a matrix, and each pixel electrode is provided with a TFT 51. In FIG. 36, “R” is written for the red display pixel, “G” is written for the green display pixel, and “B” is written for the blue display pixel.

As shown in FIG. 36, the source driver 60 to set the potential of each source line _S 1 to S _n are provided, the output terminal _D 1 to D _n of the source driver 60, the source lines are connected. In the example shown in FIG. 36, each TFT 51 is provided on the left side of the pixel electrode 50 and connected to a source line existing on the left side of the pixel electrode 50. Further, gate lines G ₁ , G ₂ , G ₃ ,... Are provided for each row of pixels, and each gate line is connected to the TFT 51 of each pixel electrode in that row. The gate lines are sequentially selected, and the TFT 51 in the selected row brings the pixel electrode 50 and the source line into a conductive state. As a result, the pixel electrode 50 in the selected row is controlled to be equipotential with the source line existing on the left side of the pixel electrode. Further, the TFT 51 in the non-selected row brings the pixel electrode 50 and the source line into a non-conductive state. The gate lines are sequentially selected, and the source driver 60 sets the potential of each source line to a potential corresponding to the pixel value of each pixel in the selected row, so that an image corresponding to the image data is displayed.

In the general liquid crystal display device shown in FIG. 36, the source driver 60 controls the adjacent pixels to have different polarities as follows, for example. When a gate line in an odd-numbered row is selected in a certain frame, the source driver 60 applies the potentials of the source lines S ₁ , S ₃ , S ₅ ,. ) is set to a potential higher than the potential _{V COM} of the even-numbered column source line _{S 2, and} S _{4, S} 6, the potential of ... is set _to a potential lower than _{V COM.} Further, the source driver 60 sets the potentials of the source lines S ₁ , S ₃ , S ₅ ,... In the odd-numbered columns to potentials lower than V _COM when the gate lines in the even-numbered rows are selected. The potentials of the source lines S ₂ , S ₄ , S ₆ ,... In the even-numbered columns are set higher than V _COM . As a result, as shown in FIG. 36, the adjacent pixels are controlled to be alternately positive and negative. In FIG. 36, “+” represents positive polarity, and “−” represents negative polarity.

Further, the source driver 60 switches the potential of the source line so as to invert the polarity of each pixel every time the frame is switched. That is, in the next frame of the frame, the source driver 60, during odd-numbered selection gate lines of rows, while an odd-numbered source line of the potential of the column to a potential lower than V _COM, the even-numbered The potential of the source line of the column is set to a potential higher than _VCOM . The source driver 60, during even-numbered selection gate lines of rows, while an odd-numbered source line potential of the column to a potential higher than V _COM, V _COM source line of the potential of the even-numbered column A lower potential is set. As a result, the polarity of each pixel is opposite to the polarity of each pixel shown in FIG.

In this driving method, each selected row is switched, changes the potential of each source line or changing to a lower potential than V _COM from the potentials higher than V _COM or a potential higher than V _COM from potentials lower than V _COM I will let you. As a result, power consumption increases. In particular, since the power consumption of the liquid crystal display panel is proportional to the square of the potential difference of the source line when the selected row is switched, the power consumption increases due to the large number of potential switching of the source line.

A liquid crystal display device that can be controlled so that the polarities of adjacent pixels are different while suppressing power consumption has been proposed (see Patent Document 1). In the liquid crystal display device described in Patent Document 1, TFTs connected to odd-numbered gate lines are formed on the left side of the source lines, and TFTs connected to even-numbered gate lines are formed on the right side of the source lines. . With this configuration, each selection period, or changes from a high potential of the source line is higher than V _COM potential lower than V _COM potential, it prevents the changes towards potentials higher than V _COM from potentials lower than V _COM Yes.

  Patent Document 2 describes a liquid crystal display device that suppresses the amount of heat generated by a source driver by supplying a signal potential (potential set to a pixel) to a source line after supplying a preliminary potential. . A period during which the preliminary potential is supplied is called a precharge period. In the case of the positive polarity, the liquid crystal display device described in Patent Document 2 supplies the first preliminary potential to the source line during the precharge period. The first preliminary potential is, for example, a substantially average value of the positive signal potential corresponding to the lowest gradation and the positive signal potential corresponding to the highest gradation. In the case of negative polarity, the second preliminary potential is supplied to the source line in the precharge period. The second preliminary potential is, for example, a substantially average value of the negative signal potential corresponding to the lowest gradation and the negative signal potential corresponding to the highest gradation.

JP 2009-181100 A (paragraphs 0008-0018, FIG. 1-6) JP 2010-15057 A (paragraph 0020)

  As a configuration of the liquid crystal display panel, a configuration in which the number of source lines is increased by one more than the number of pixel electrode columns, and pixel electrode columns are arranged between the source lines can be considered. In this configuration, for example, each pixel electrode in the odd-numbered row is connected to the left source line via the TFT. Each pixel electrode in the even-numbered row is connected to the right source line through the TFT. The number of source lines in this configuration is n + 1. In the selection period of the odd-numbered row, the potential corresponding to each pixel value of the selected row is set from the leftmost source line to the n-th source line. From the second source line to the (n + 1) th source line, by setting a potential corresponding to each pixel value of the selected row, all the pixel electrodes in each row can be set to a potential corresponding to the pixel value. it can.

In such a configuration, for example, the second output terminal from the left in the source driver is connected to the second source line from the left. The output terminal sets a potential corresponding to the pixel value of the second pixel from the left in the selection period of the odd-numbered row, and the pixel value of the leftmost pixel in the selection period of the even-numbered row. What is necessary is just to set the electric potential according to. At this time, the output continues to output the potentials lower than V _COM in a frame, it continues to output the potentials higher than V _COM in the next frame. Thus, in the second output terminals from the left in the source driver switches between the output of the potentials lower than V _COM and the output of the potentials higher than V _COM for each frame. In other output terminal of the source driver, and it outputs the potentials higher than V _COM, or outputs a low potential, may be switched for each frame. The other source lines are similarly controlled. By doing in this way, the polarity of adjacent pixels can be made into a reverse polarity, suppressing power consumption.

  However, in the configuration as described above, there is one source line that is not used for setting the potential of the pixel electrode in the selection period of each row. For example, since the (n + 1) th source line from the left is not connected to the pixel electrode of the odd-numbered row, it is not used for setting the potential of the pixel electrode of the odd-numbered row in the selection period of the odd-numbered row. Similarly, since the leftmost source line is not connected to the pixel electrode of the even-numbered row, it is not used for setting the potential of the pixel electrode of the even-numbered row in the selection period of the even-numbered row.

  As described above, the source lines at both ends may not be used for setting the potential of the pixel electrode in the selected row. At this time, the output terminal of the source driver connected to the source line that is not used for setting the potential of the pixel electrode may be in a high impedance state. For example, the output terminal of the source driver connected to the (n + 1) th source line from the left can be set to a high impedance state when an odd-numbered row is selected. Also regarding the output terminal of the source driver connected to the leftmost source line, when the even-numbered row is selected, it can be considered to set it to the high impedance state.

  However, when the output terminal of the source driver is set to the high impedance state in this way, the potential of the source line connected to the output terminal becomes unstable. For example, when the output terminal of the source driver enters a high impedance state, the potential of the source line connected to the output terminal becomes unstable due to the influence of the gate line or the like.

  Accordingly, an object of the present invention is to provide a liquid crystal display device capable of stabilizing the source line potential while suppressing power consumption.

The liquid crystal display device according to the present invention includes an active matrix liquid crystal display panel (for example, the liquid crystal display panel 20) and a driving device (for example, the driving device 1) for driving the liquid crystal display panel. An electrode, a plurality of pixel electrodes arranged in a matrix, and a number of source lines that is one more than the number of columns of pixel electrodes, each column of pixel electrodes being arranged between adjacent source lines, When the electrode row is made into one group for each row or for every plurality of consecutive rows, the pixel electrodes in each row of the odd-numbered group have a predetermined number of source lines existing on both sides of the pixel electrode. Connected to the source line on the side (for example, the left side when viewed from the viewing side), and the pixel electrodes in each row of the even-numbered group are connected to a predetermined side of the source lines existing on both sides of the pixel electrode. Connected to the source line on the opposite side (for example, the right side when viewed from the viewing side), the driving device has a potential output terminal for each source line that outputs a potential corresponding to the pixel value included in the image data to the source line. The positive polarity potential that is higher than the potential of the common electrode is output from the odd-numbered potential output end from the predetermined side, and the negative polarity is lower than the potential of the common electrode from the even-numbered potential output end from the predetermined side. A first potential output mode for outputting a potential; and a second potential for outputting a negative potential from an odd-numbered potential output terminal from a predetermined side and outputting a positive potential from an even-numbered potential output terminal from a predetermined side A potential output means (for example, potential setting unit 2) that switches the potential output mode alternately for each frame, and a potential that is set to the source line before the positive potential corresponding to the pixel value is output to the source line. so First preliminary potential (e.g., V _p) that the first preliminary voltage output means for outputting (e.g., V _p setting section 3) and, before the negative polarity potential corresponding to the pixel value is output to the source line, the Second preliminary potential output means (for example, V _n setting section 4) that outputs a second preliminary potential (for example, V _n ) that is a potential set to the source line, and the potential output means determines the number of source lines. Assuming n + 1 lines, in the period in which each row of the odd-numbered group is selected in each frame, the pixel values correspond to the first to nth potential output terminals from the predetermined side after the preliminary potential setting period, respectively. In the period when all the rows in the even-numbered group are selected, the potential corresponding to the pixel value is output from the second to n + 1th potential output terminals from the predetermined side after the preliminary potential setting period. And driving equipment The first source connects the first source line from the predetermined side to the first preliminary potential output means, the second preliminary potential output means, or the first potential output terminal from the predetermined side in the potential output means. The line switching means (for example, the switch 11) and the (n + 1) th source line from the predetermined side are connected to the n + 1th source line from the predetermined side in the first preliminary potential output means, the second preliminary potential output means, or the potential output means. The last source line switching means (for example, the switch 12) to be connected to the potential output terminal, and even-numbered source lines of the source lines other than the first and n + 1th from the predetermined side are connected to the first preliminary potential output means, The second preliminary potential output means or the even-numbered source line switching means (for example, the scan line connecting means connected to the even-numbered potential output terminal from the predetermined side of the potential output means). 14) and an odd-numbered source line among the source lines other than the first and n + 1th from the predetermined side is a predetermined line in the first preliminary potential output means, the second preliminary potential output means, or the potential output means. Odd-numbered source line switching means (for example, switch 15) connected to the odd-numbered potential output terminal from the side of the first source line switching means within the frame (for example, the first potential output mode) , In the frame in which POL ₁ is at a high level), the first source line from the predetermined side is used as the first preliminary potential output means during the preliminary potential setting period during the period when all the rows of the odd-numbered group are selected. After the preliminary potential setting period elapses, the source line is connected to the first potential output terminal from a predetermined side, and during the period when all the rows of the even-numbered group are selected, The source line is connected to the first preliminary voltage output unit, in a frame as a second potential output mode (for example, the frame POL ₁ is at low level), each row of the odd-numbered group is selected all During the preliminary potential setting period, the first source line from the predetermined side is connected to the second preliminary potential output means, and after the preliminary potential setting period, the source is connected to the first potential output terminal from the predetermined side. A frame in which the lines are connected and the source lines are connected to the second preliminary potential output means during the period when all the rows of the even-numbered group are selected, and the final source line switching means is in the first potential output mode. The n + 1th source line from the predetermined side is connected to the first preliminary potential output means or the second preliminary potential output means during a period in which all the rows of the odd-numbered group are selected. During the period when all the rows of the even-numbered group are selected, the source line is connected to the first preliminary potential output means or the second preliminary potential output means during the preliminary potential setting period. The source line is connected to the (n + 1) th potential output terminal from the side of the first side, and during the period when all the rows of the odd-numbered group are selected in the frame that is the second potential output mode, the (n + 1) th potential output terminal is selected. The source line is connected to one of the first preliminary potential output means and the second preliminary potential output means, which is different from the frame serving as the first potential output mode, and all the rows of the even-numbered groups are selected. In the preliminary potential setting period, the source line is connected to one of the first preliminary potential output means and the second preliminary potential output means that is different from the first potential output mode frame. After the unit setting period, the source line is connected to the (n + 1) th potential output terminal from the predetermined side, and the even-numbered source line switching means is in the preliminary potential setting period within the frame in the first potential output mode. The even-numbered source line from the predetermined side is connected to the second preliminary potential output means, and after the preliminary potential setting period has elapsed, the source line is connected to the even-numbered potential output terminal from the predetermined side. In the frame that is the potential output mode, even-numbered source lines from the predetermined side are connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the even-numbered source lines are even-numbered from the predetermined side. The odd-numbered source line switching means connects the odd-numbered source from the predetermined side in the preliminary potential setting period within the frame that is in the first potential output mode. The line is connected to the first preliminary potential output means, and after the preliminary potential setting period, the source line is connected to the odd-numbered potential output terminal from the predetermined side, and in the frame that becomes the second potential output mode, An odd-numbered source line from the predetermined side is connected to the second preliminary potential output means during the preliminary potential setting period, and the source line is connected from the predetermined side to the odd-numbered potential output terminal after the preliminary potential setting period has elapsed. It is characterized by making it.

The liquid crystal display device according to the present invention includes an active matrix type liquid crystal display panel (for example, the liquid crystal display panel 20 _b ) and a plurality of driving devices (for example, the first driving device) that are arranged side by side to drive the liquid crystal display panel. 1 _a and the second driving device 1 _b ), the liquid crystal display panel includes a common electrode, a plurality of pixel electrodes arranged in a matrix, and a number of source lines that is one more than the number of columns of pixel electrodes, Each column of pixel electrodes is arranged between adjacent source lines, and when the row of pixel electrodes is one group for each row or for every plurality of consecutive rows, an odd-numbered group The pixel electrodes in each row are connected to the source lines on a predetermined side (for example, the left side when viewed from the viewing side) among the source lines existing on both sides of the pixel electrode, and The electrode is connected to the source line on the opposite side (for example, the right side when viewed from the viewing side) of the source lines existing on both sides of the pixel electrode, and a plurality of driving devices respectively convert the image data to the image data. A plurality of potential output terminals that output potentials corresponding to the included pixel values to the source line, and output a positive potential that is higher than the potential of the common electrode from an odd-numbered potential output terminal from a predetermined side; A first potential output mode that outputs a negative potential that is lower than the potential of the common electrode from the even-numbered potential output terminal from the predetermined side, and a negative potential output from the odd-numbered potential output terminal from the predetermined side And a potential output means (for example, potential setting unit 2) for alternately switching the second potential output mode for outputting the positive potential from the even-numbered potential output terminal from the predetermined side for each frame, and the pixel value According to the positive electrode First preliminary potential output means (for example, V _p setting unit 3) for outputting a first preliminary potential (for example, V _p ) that is a potential set to the source line before the potential is output to the source line; Before the negative potential corresponding to the pixel value is output to the source line, second preliminary potential output means (for example, V _n ) that outputs a second preliminary potential (for example, V _n ) that is a potential set to the source line and a V _n setting unit 4), when the number of potential output terminals of the potential output means provided in each drive unit and (n + 1), n + 1 is an odd number, the number of the plurality of drives and u, v 1 Assuming that the integer is less than u, the v · n + 1 source line from the predetermined side has the first branch portion and the second branch portion, and the first branch portion of the v · n + 1 source line from the predetermined side. In the v-th drive device from the predetermined side The second branching portion of the source line is connected to the first potential output terminal from the predetermined side in the (v + 1) th driving device from the predetermined side, and is connected to the first potential output terminal from the predetermined side. In each frame, the potential output means included in each of the odd-numbered groups in each frame is selected from the first to nth potential output terminals from the predetermined side after the preliminary potential setting period. In the period in which the potential corresponding to the pixel value is output and all the rows of the even-numbered groups are all selected, the pixel value is set to the pixel value from the second to the (n + 1) th potential output terminal after the preliminary potential setting period. The first driving device (for example, the first driving device 1 _a ) that outputs the corresponding potential and is the first driving device arranged from the predetermined side among the plurality of driving devices is the driving device itself. The first switching means for connecting the source line corresponding to the first potential output terminal from the predetermined side of the potential output means to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal ( For example, the switch 11) and the first branch portion of the source line corresponding to the (n + 1) th potential output terminal from the predetermined side in the potential output means of the drive device itself are connected to the first reserve potential output means and the second reserve potential output. Or a second switching means (for example, a switch 91) that is connected to the potential output terminal or is not connected to any of them, and a position farthest from a predetermined side among the plurality of driving devices. the second driving device is arranged driven apparatus (e.g., the second driving device 1 _b), the first potential output terminal from the predetermined side in the potential output means of the drive device itself Third switching means for connecting the second branch portion of the corresponding source line to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal thereof, or to connect them to none of them. For example, the switch 92) and the source line corresponding to the (n + 1) th potential output terminal from the predetermined side in the potential output means of the driving device itself are connected to the first preliminary potential output means, the second preliminary potential output means, or the A fourth switching unit (for example, switch 12) connected to the potential output terminal, and each of the plurality of driving devices has a source line corresponding to an even-numbered potential output terminal from a predetermined side in the potential output unit, In the first preliminary potential output means, the second preliminary potential output means, or the fifth switching means (for example, the switch 14) connected to the potential output terminal, and the potential output means Sixth switching means (for example, switch 15) for connecting the source line corresponding to the odd-numbered potential output terminal from the predetermined side to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal. The first switching means is in a period in which each row of the odd-numbered group is selected in a frame (for example, in a frame in which POL ₁ is at a high level) in the first potential output mode. The source line corresponding to the first potential output terminal from the predetermined side in the potential output means of the driving device provided with the first switching means is connected to the first preliminary potential output means during the preliminary potential setting period, and the preliminary potential setting period After that, the source line is connected to the potential output terminal, the source line is connected to the first preliminary potential output means during the period when all the rows of the even-numbered group are selected, In the frame in which the potential output mode is 2 (for example, in the frame in which POL ₁ is at a low level), during the period in which all the rows of the odd-numbered group are all selected, Connected to the preliminary potential output means, and after the preliminary potential setting period, the source line is connected to the potential output terminal, and the source line is connected to the second preliminary potential during the period when all the rows of the even-numbered group are selected. The potential of the driving device provided with the second switching means is connected to the output means and the second switching means is selected during the period when all the rows of the odd-numbered group are selected in the frame in the first potential output mode. The first branch portion of the source line corresponding to the (n + 1) th potential output terminal from the predetermined side in the output means is set to the high impedance state, and all the rows in the even-numbered group are selected. The first branch portion of the source line is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the first branch portion of the source line is connected to the potential output terminal. In the frame in which the second potential output mode is selected, the first branch portion of the source line is set to the high impedance state during the period in which all the rows of the odd-numbered group are selected, and each row of the even-numbered group is During the period in which all of the source lines are selected, the first branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period has elapsed, A drive device that is connected to the potential output terminal and in which the third switching unit is provided during a period in which each row of the odd-numbered group is selected in the frame that is in the first potential output mode. The second branch portion of the source line corresponding to the first potential output terminal from the predetermined side in the potential output means is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period has elapsed, The second branch portion of the source line is connected to the potential output terminal, and the second branch portion of the source line is set to a high impedance state during the period when all the rows of the even-numbered group are selected. In the frame in which all the rows of the odd-numbered group are selected, the second branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period, After the elapse of time, the second branch portion of the source line is connected to the potential output terminal, and the second branch portion of the source line is connected to the high impedance during a period when all the rows of the even-numbered group are selected. The potential output means of the drive device in which the fourth switching means is provided during a period in which each row of the odd-numbered group is selected in the frame in which the fourth switching means is in the first potential output mode. The source line corresponding to the (n + 1) th potential output terminal from the predetermined side is connected to the first spare potential output means, and the source line is set to the spare potential during the period when all the rows of the even-numbered group are selected. Connected to the first preliminary potential output means in the period, and after the preliminary potential setting period, the source line is connected to the potential output terminal, and each row of the odd-numbered group in the frame in the second potential output mode The source line is connected to the second preliminary potential output means during the period in which all of the lines are selected, and the source line is connected to the standby power during the period in which all the rows of the even-numbered groups are selected. In the frame setting period, the second preliminary potential output means is connected, and after the preliminary potential setting period has elapsed, the source line is connected to the potential output terminal, and the fifth switching means is in the frame in the first potential output mode. Then, the source line corresponding to the even-numbered potential output terminal from the predetermined side in the potential output means is connected to the second preliminary potential output means in the preliminary potential setting period, and after the preliminary potential setting period, the potential output terminal And the source line is connected to the first preliminary potential output means during the preliminary potential setting period and connected to the potential output terminal after the preliminary potential setting period elapses in the frame that becomes the second potential output mode. And the sixth switching means causes the source line corresponding to the odd-numbered potential output terminal from the predetermined side of the potential output means within the first potential output mode to be in the first spare potential setting period. Connected to the potential output means, connected to the potential output terminal after the preliminary potential setting period has elapsed, and the source line is output to the second preliminary potential output during the preliminary potential setting period within the frame that becomes the second potential output mode. And a potential output terminal after the preliminary potential setting period has elapsed.

  Among the plurality of driving devices, each driving device (for example, the third driving device) other than the first driving device and the second driving device has a configuration including a second switching unit and a third switching unit. May be.

  Further, the potential output means provided in each driving device has a first or n + 1th potential output terminal from a predetermined side after a preliminary potential setting period in which the source line is set to the first preliminary potential or the second preliminary potential. In a high-impedance state, the potential corresponding to the pixel value is output from each of the other potential output terminals, and in a period in which each row of the odd-numbered group is selected in each frame, a predetermined potential is set after the preliminary potential setting period. In a period in which potentials corresponding to the pixel values are output from the first to nth potential output terminals from the side of, and the n + 1th potential output terminal is set to a high impedance state and all the rows of the even-numbered groups are selected. After the preliminary potential setting period, the potential corresponding to the pixel value is output from the second to n + 1th potential output terminals from the predetermined side, and the first potential output In the high-impedance state, and the second switching means is in the first potential output mode in the frame in which each row of the odd-numbered group is all selected, the potential of the driving device provided with the second switching means. The first branch portion of the source line corresponding to the (n + 1) th potential output terminal from the predetermined side in the output means is connected to the potential output terminal, and during the period when all the rows of the even-numbered group are selected, The first branch portion is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the first branch portion of the source line is connected to the potential output terminal, and the second potential is set. During the period when all the rows of the odd-numbered group are selected in the output mode frame, the first branch portion of the source line is connected to the potential output terminal, and each row of the even-numbered group is The first branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the first branch portion of the source line is connected to the first branch portion of the source line. The third switching unit is connected to the potential output terminal, and the third switching unit is provided with the third switching unit during a period in which each row of the odd-numbered group is selected in the frame in the first potential output mode. The second branch portion of the source line corresponding to the first potential output terminal from the predetermined side in the potential output means is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period has elapsed, The second branch portion of the source line is connected to the potential output terminal, and the second branch portion of the source line is connected to the potential output terminal during the period in which each row of the even-numbered group is all selected. Potential output mode In the frame in which all the rows of the odd-numbered group are selected, the second branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period, After the elapse of time, the second branch portion of the source line is connected to the potential output end, and the second branch portion of the source line is connected to the potential output end during a period in which each row of the even-numbered group is selected. It may be a configuration.

For example, when the negative potential (for example, V ₁₇ ) corresponding to the maximum gradation is V _b and the positive potential (for example, V ₀ ) corresponding to the maximum gradation is V _a , the first preliminary potential is V _b + (3/4) × (V _a −V _b ), and the second preliminary potential may be V _b + (1/4) × (V _a −V _b ).

  According to the liquid crystal display device of the present invention, the source line potential can be stabilized while suppressing power consumption.

Explanatory drawing which shows the drive device with which the liquid crystal display device of this invention is provided, a control part, and a power supply part. Explanatory drawing which shows the example of the liquid crystal display panel 20 with which the liquid crystal display device of this invention is provided. The timing chart which shows the example of the timing which takes in the data for 1 line in order. Explanatory drawing which shows the change of STB. Explanatory view showing an example of a change of POL _1, POL _2. Explanatory drawing which shows the example of a connection with a pixel electrode, a source line, and a gate line. Explanatory drawing which shows the example of STV and CPV. Diagram showing the timing setting of POL ₂ during a frame start. FIG. 6 is an explanatory diagram showing a source line connection destination switching operation by the switch 11; FIG. 6 is an explanatory diagram showing a source line connection destination switching operation by the switch 12; FIG. 5 is an explanatory diagram illustrating a source line connection destination switching operation by a switch; FIG. 6 is an explanatory diagram illustrating a source line connection destination switching operation by a switch 15; _STB, a POL 1, POL _2, illustrates the relationship between the potential of each source line. Explanatory drawing which shows an example of the polar state of each pixel. _STB, a POL 1, POL _2, illustrates the relationship between the potential of each source line. Explanatory drawing which shows an example of the polar state of each pixel. FIG. 3 is an explanatory diagram illustrating a configuration example of a potential setting unit 2. FIG. 6 is an explanatory diagram illustrating a configuration example of an output switching unit 65. Explanatory view showing a mode in which the potential setting section 2 generates POL _2. Explanatory view showing an example of a liquid crystal display panel 20 _a included in the liquid crystal display device of the second embodiment of the present invention. Explanatory drawing which shows the connection destination switching operation | movement of the source line by the switch 11 in 2nd Embodiment. Explanatory drawing which shows the connection destination switching operation | movement of the source line by the switch 12 in 2nd Embodiment. Diagram showing _STB, an example of POL 1, POL ₂ in frame POL ₁ is at high level in the second embodiment. Explanatory drawing which shows an example of the polar state of each pixel. Diagram showing _STB, an example of POL 1, POL ₂ in frame POL ₁ is at low level in the second embodiment. Explanatory drawing which shows an example of the polar state of each pixel. Explanatory drawing which shows the example of the liquid crystal display device of the 3rd Embodiment of this invention. Explanatory drawing which shows the structural example of the 1st drive device _1a . FIG. 5 is an explanatory diagram showing a source line connection destination switching operation by a switch 91; Explanatory drawing which shows the structural example of the 2nd drive device _1b . FIG. 9 is an explanatory diagram showing a source line connection destination switching operation by a switch 92; Explanatory drawing which shows the structural example of the 3rd drive device _1c . Explanatory drawing which shows operation | movement of the switch 91 in the case of applying 2nd Embodiment to 3rd Embodiment. Explanatory drawing which shows operation | movement of the switch 92 in the case of applying 2nd Embodiment to 3rd Embodiment. Explanatory drawing which shows the example of the electric potential which sets a pixel to white and black by the electric potential of a common electrode, and each polarity. Explanatory drawing which shows a general liquid crystal display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
FIG. 1 is an explanatory diagram showing a driving device, a control unit, and a power supply unit included in the liquid crystal display device of the present invention. FIG. 2 is an explanatory diagram showing an example of the liquid crystal display panel 20 provided in the liquid crystal display device of the present invention.

The power supply unit 9 (see FIG. 1) supplies voltages V _{0 to} V ₈ and V _{9 to} V ₁₇ to the driving device 1 (specifically, a potential setting unit 2 described later). V ₀ ~V ₈ is a voltage higher than the potential _{V COM} of the common electrode (not shown in FIG. _{2), V} 9 _{~V 17} is a voltage lower than _{V COM. Here,} as the _{V 17 <V 16 <··· <} V 9 <V COM <V 8 <V 7 <··· <V 0. In _addition, a _{V COM -V 17 = V 0 -V} COM. A voltage of V ₀ -V ₁₇ is denoted as V _DDA . In the present embodiment, for example, a case where a ground voltage (0 V) is used as V ₁₇ , which is the lowest voltage, is exemplified. However, V ₁₇ may be other than 0 V.

In this example, the case where the power supply unit 9 supplies V _{0 to} V ₈ as a voltage for positive polarity display will be described as an example. The potential setting unit 2 divides the voltage and displays, for example, 64 gradations in the positive polarity. Similarly, a case where the power supply unit 9 supplies V _{9 to} V ₁₇ as a voltage for negative polarity display will be described as an example. The potential setting unit 2 divides the voltage and displays, for example, 64 gradations in the negative polarity. However, the voltages supplied from the power supply unit 9 for the positive polarity display and the negative polarity display are not limited to nine types, respectively, and the number of gradations is not limited to 64 gradations.

The driving device 1 controls the potentials of the source lines S _{1 to} S _{n + 1} provided in the liquid crystal display panel 20 (see FIG. 2). Drive device 1 includes the potential setting section 2, a first precharge potential setting section 3 (hereinafter, referred to as V _p setting unit 3.) And, second precharge potential setting unit 4 (hereinafter, V _n setting unit 4 and referred to.), the first precharge potential setting line 5 (hereinafter, a V _p referred to as setting the wiring 5.), the second precharge potential setting line 6 (hereinafter, V _n set wire 6)).

A precharge potential (sometimes referred to as a reserve potential) is a potential set in a source line before setting the source line to a potential corresponding to a pixel value. First precharge potential is a precharge potential to be set for the source line to be set a higher potential than V _COM to a potential corresponding to the pixel value, hereinafter referred to as V _p. Second precharge potential is a precharge potential to be set for the source line to be set lower potential than V _COM to a potential corresponding to the pixel value, hereinafter referred to as V _n.

In first pre-charge potential _{V p,} for _example, it may be used a potential becomes _{V p = V 17 + 3V DDA} / 4. Further, as the second precharge potential V _n , a potential that satisfies V _n = V ₁₇ + V _DDA / 4 may be used. In this example, it is assumed that V ₁₇ = 0, and V _p = 3V _DDA / 4 and V _n = V _DDA / 4.

However, other potentials may be used as V _p and V _n . For example, an average potential (that is, (V ₀ + V ₈ ) / 2) of the potential corresponding to the maximum gradation in the positive polarity and the potential corresponding to the lowest gradation in the positive polarity may be used as V _p . Similarly, the average potential (that is, (V ₁₇ + V ₉ ) / 2) of the potential corresponding to the maximum gradation in the negative polarity and the potential corresponding to the lowest gradation in the negative polarity may be used as V _n .

V _p setting unit 3, V the potential of the _p sets wiring 5 by setting V _p, sets the potential of the source lines connected to V _p setting wire 5 to V _p. V _n setting unit 4, by setting the potential for V _n set wirings 6 to V _n, it sets the potential of the source connected line V _n setting wire 6 to V _n.

The potential setting unit 2 takes in the image data under the control of the control unit 8 and outputs a potential corresponding to the pixel value indicated by the image data. The number of potential output terminals of the potential setting unit 2 is _{n + 1,} which are represented by D _{1 to} D _{n + 1} , respectively. The potential output terminals D _{1 to} D _{n + 1} correspond to the source lines S _{1 to} S _{n + 1} , respectively.

The source line is set to the potential V _p when connected to the V _p setting wiring 5, is set to the potential V _n when connected to the V _n setting wiring 6, and is connected to the potential output terminal of the potential setting unit 2. Then, the output potential from the potential output terminal is set.

For each source line, a switch for switching the connection to _{V p} set wiring 5, _{V n} set wiring 6 and the potential output terminals of the potential setting section 2 (one of the switches 11, 12, 14, 15) are provided. The operation of the switch provided in the source line differs depending on the position of the source line. The operation of each switch 11, 12, 14, 15 will be described later.

Note that, among the potential output terminals D _{1 to} D _{n +} 1 in FIG. 1, D ₁ is the leftmost potential output terminal when viewed from the image viewing side (viewing side) of the liquid crystal display device, and D _{n + 1} is the left The case of the (n + 1) th potential output terminal from the start will be described as an example. The source lines S _{1 to} S _{n + 1} are sequentially connected to the potential output terminals D _{1 to} D _{n + 1} . Thus, in this embodiment, as viewed from the viewing side, S _{n + 1} S ₁ is the source lines of the leftmost is (n + 1) th source lines from the left. In this example, n + 1 is an odd number, S _{n + 1} is an odd-numbered source line from the left, and D _{n + 1} is an odd-numbered potential output terminal from the left.

Further, as shown in FIG. 2, in each row of the liquid crystal display panel 20, each pixel is repeatedly arranged in the order of R (red), G (green), and B (blue), and corresponds to one row of pixels. The image data is input to the potential setting unit 2 in order from data (pixel value) corresponding to the pixel at one end of the pixels for one row. In the following description, a case where pixel values are sequentially input from the left pixel as viewed from the viewing side will be described as an example. FIG. 3 is a timing chart showing an example of timing at which the potential setting unit 2 sequentially fetches data for one row. In accordance with the control signal SCLK input from the control unit 8, the potential setting unit 2 sequentially captures data for one row of the image from the data of the left pixel. SCLK is a clock signal for capturing an image to the potential setting unit 2. The potential setting unit 2 captures image data for one pixel at the rising edge of SCLK. That is, as shown in FIG. 3, first, the leftmost pixel value R ₁ in the image data for one row is captured at the rising edge of SCLK, and thereafter, the pixel values G ₁ and B _{1 at} every rising edge of SCLK. , R ₂ ,... Here, a case where pixel values are captured serially is illustrated, but R, G, and B pixel values may be captured in parallel for each rising edge of SCLK. Note that the number of pixels for one row is n, which is 1 less than the number of source lines.

The potential setting unit 2 takes in the data for one row within the selection period for one row in accordance with the control of the control unit 8. Then, the potential setting unit 2 outputs a potential corresponding to each data for one row from the potential output terminals D _{1 to} D _n or the potential output terminals D _{2 to} D _{n + 1} in the next selection period. The potential setting unit 2 outputs a potential according to the control signal STB input from the control unit 8. STB is a control signal that specifies the selection period of each row. FIG. 4 is an explanatory diagram showing changes in STB. The period from the falling edge of STB to the rising edge is a selection period of one row in the liquid crystal display panel 20 (see FIG. 2). The control unit 8 outputs SCLK (see FIG. 3) instructing to capture data for one row of the image within this selection period, and the potential setting unit 2 captures and stores the data for one row. The potential setting unit 2 outputs, from the potential output terminals D _{1 to} D _n or D _{2 to} D _{n + 1} , the potential corresponding to the pixel value of each pixel stored for one row at the falling edge of STB. The potential setting unit 2 sets the outputs of the potential output terminals D _{1 to} D _{n + 1} to, for example, a high impedance state during the period when the STB is at a high level.

Further, the potential setting section 2, in accordance with the control signal POL ₁ input from the control unit 8, the potential output from each of the potential output terminal is switched to either potentials higher than V _COM or lower than V _COM potential. The potentials higher than V _{COM, specifically,} and V 0 ~V _8, a potential obtained by partial pressure based on V 0 ~V _8, hereinafter referred to as the positive polarity potential. _Further, the potentials lower than _{V COM, specifically,} and V 9 _{~V 17,} a potential obtained by partial pressure based on V 9 _{~V 17,} hereinafter referred to as negative polarity potential. POL ₁ is a control signal that controls whether the potential at each potential output terminal of the potential setting unit 2 is set to a positive potential or a negative potential. The control unit 8 alternately switches the level of POL ₁ between a high level and a low level for each frame. One frame is a period required for line sequential selection (line sequential scanning) from the first row to the last row.

When POL ₁ is at a high level, the potential setting unit 2 sets the output potential of each odd-numbered potential output terminal from the left as a positive potential when viewed from the viewing side, and sets the output potential of each even-numbered potential output terminal from the left. A negative potential is assumed. In addition, when POL ₁ is at a low level, the potential setting unit 2 sets the output potential of each odd-numbered potential output terminal from the left as a negative potential when viewed from the viewing side, and outputs the even-numbered potential output terminals from the left. The potential is a positive potential. What value of potential is output as the positive potential is determined by the pixel value. Similarly, what potential is output as the negative potential is determined by the pixel value.

Further, the potential setting unit 2 outputs pixels for one row from the potential output terminals D _{1 to} D _n according to the control signal POL ₂ input from the control unit 8, or the potential output terminals D ₂ to D _n. Determine whether to output from D _{n + 1} . Whether POL ₂ outputs each potential corresponding to each pixel (n pixels) for one row from potential output terminals D _{1 to} D _n , or outputs from potential output terminals D _{2 to} D _{n + 1} This is a control signal for instructing. The control unit 8 sets POL ₂ to the high level at the start of the frame. Then, the POL ₂ level is alternately switched between a high level and a low level for each selection period within the frame. Specifically, for each cycle of STB (see FIG. 4), the level of POL ₂ is switched from high to low or from low to high within a period in which STB is at high level.

The potential setting unit 2 outputs potentials corresponding to n pixels corresponding to one row from the potential output terminals D _{1 to} D _n when POL ₂ is at a high level. Further, when POL ₂ is at a low level, each potential corresponding to n pixels corresponding to one row is output from the potential output terminals D _{2 to} D _{n + 1} .

FIG. 5 is an explanatory diagram showing an example of changes in POL ₁ and POL ₂ . The level of POL ₁ is switched alternately every frame. In addition, POL ₂ becomes high level at the start of the frame, and thereafter, is switched every cycle of the STB (in other words, every selection period of each row). Hereinafter, a period during which both POL ₁ and POL ₂ are at the high level is referred to as “A”. A period in which POL ₁ is at a high level and POL ₂ is at a low level is referred to as “B”. A period in which POL ₁ is at a low level and POL ₂ is at a high level is denoted as C. A period during which both POL ₁ and POL ₂ are at a low level is denoted as “D”.

In the period A, the potential setting unit 2 outputs each potential corresponding to n pixels corresponding to one row from D _{1 to} D _n . At this time, the potential output from the odd-numbered potential output terminal from the left is a positive potential, and the potential output from the even-numbered potential output terminal from the left is a negative potential. However, in the period A, the potential setting unit 2 sets D _{n + 1} to the high impedance state. In the period B, the potential setting unit 2 outputs each potential corresponding to n pixels corresponding to one row from D _{2 to} D _{n + 1} . At this time, the potential output from the odd-numbered potential output terminal from the left is a positive potential, and the potential output from the even-numbered potential output terminal from the left is a negative potential. However, in the period B, the potential setting section 2, a D ₁ to a high impedance state. In the frame in which POL ₁ is at the high level, the operation in the period A and the operation in the period B are repeated. Therefore, the potential output from each potential output terminal is in the frame, it does not change across the V _COM.

In the period C, the potential setting unit 2 outputs each potential corresponding to n pixels corresponding to one row from D _{1 to} D _n . At this time, the potential output from the odd-numbered potential output terminal from the left is a negative potential, and the potential output from the even-numbered potential output terminal from the left is the positive potential. However, in the period C, the potential setting unit 2 sets D _{n + 1} to the high impedance state. In the period D, the potential setting unit 2 outputs each potential corresponding to n pixels corresponding to one row from D _{2 to} D _{n + 1} . At this time, the potential output from the odd-numbered potential output terminal from the left is a negative potential, and the potential output from the even-numbered potential output terminal from the left is the positive potential. However, in the period D, the potential setting section 2, a D ₁ to a high impedance state. In the frame in which POL ₁ is at the low level, the operation in the period C and the operation in the period D are repeated. Therefore, the potential output from each potential output terminal is in the frame, it does not change across the V _COM.

Thus, the potential output from each potential output terminal, do not change across the V _COM in individual frames.

  A liquid crystal display panel 20 shown in FIG. 2 has a liquid crystal (not shown) sandwiched between a plurality of pixel electrodes 21 arranged in a matrix and a common electrode (not shown in FIG. 2). The state is changed according to the potential difference between 2 and the common electrode, and an image is displayed. The liquid crystal display panel 20 includes a pair of substrates (not shown), has a plurality of pixel electrodes 21 arranged in a matrix on one substrate, and has a common electrode on the other substrate. Then, two substrates are arranged so that the group of pixel electrodes 21 and the common electrode face each other, and liquid crystal is injected between the substrates.

  As already described, in each row of the liquid crystal display panel 20, each pixel is repeatedly arranged in the order of R, G, and B. In FIG. 2, the red display pixel is indicated by “R”, the green display pixel is indicated by “G”, and the blue display pixel is indicated by “B”.

In addition, the liquid crystal display panel 20 includes source lines S _{1 to} S _{n + 1} and includes pixel electrodes for one column between adjacent source lines. Therefore, in the pixel electrode group arranged in a matrix, the number of pixel electrode columns is n columns, which is one less than the number of source lines. In other words, the liquid crystal display panel 20 includes a source line on the left side of each column of pixel electrodes, and also includes a source line on the right side of the rightmost pixel column.

  Each pixel electrode 21 is provided with an active element 22. In the following description, a case where the active element is a TFT (Thin Film Transistor) will be described as an example. However, an active element other than a TFT may be provided in each pixel electrode 21.

  In the present embodiment, in each pixel electrode 21 in an odd-numbered row, a TFT 22 is provided on the left side of the pixel electrode 21 when viewed from the viewing side, and the pixel electrode 21 is connected to the left source line. . Then, in each pixel electrode 21 in the even-numbered row, a TFT 22 is provided on the right side of the pixel electrode 21 when viewed from the viewing side, and the pixel electrode 21 and the source line on the right side thereof are connected as an example (FIG. 2). reference).

  However, here, for the sake of convenience, the case where the pixel of the odd-numbered TFT is provided on the left side of the pixel electrode and the TFT of the even-numbered row is provided on the right side of the pixel electrode is illustrated. As long as it is connected to the source line and the pixel electrode in the even-numbered row is connected to the source line on the right side, the position of the TFT itself may be arbitrary.

  Each TFT 22 has, for example, a source connected to the source line and a drain connected to the pixel electrode 21.

In addition, the liquid crystal display panel 20 includes gate lines G ₁ , G ₂ , G ₃ ,... For each row of pixel electrodes arranged in a matrix. In FIG. 2, illustration of gate lines in the fourth and subsequent rows is omitted. The gate line is connected to the gate of the TFT 22 provided in each pixel electrode 21 in the corresponding row. For example, gate line G ₁ shown in FIG. 2 is connected to the gate of TFT22 of the first row pixel electrodes.

FIG. 6 is an explanatory diagram illustrating an example of connection between the pixel electrode, the source line, and the gate line. In FIG. 6, the pixel electrode 21 is connected to the i-th gate line Gi and is connected to the source line Sk existing on the left side of the pixel electrode 21 as an example. Gate 22 _a of the TFT22 is connected to the gate line Gi. In the TFT 22, the source 22 _c is connected to the source line Sk, and the drain 22 _b is connected to the pixel electrode 21. FIG. 6 illustrates the case where the pixel electrode 21 is connected to the left source line. However, when the pixel electrode 21 is connected to the right source line, for example, the TFT 22 is disposed on the right side of the pixel electrode 21. Then, the connection may be made in the same manner as shown in FIG.

  The image display device includes a gate driver (not shown) that sets the potential of each gate line. The gate driver sequentially selects the gate lines one by one, sets the selected gate lines to the selected potential, and sets the unselected gate lines to the unselected potential. Accordingly, each row is selected one by one. The drive device 1 may have a function as a gate driver.

  The control unit 8 is a control signal (hereinafter referred to as STV) for instructing the start of one frame, and a control signal (gate clock; hereinafter referred to as CPV) for instructing switching of a selected row. To the gate driver. FIG. 7 is an explanatory diagram showing examples of STV and CPV. The period from the rising edge of the CPV to the next rising edge of the CPV is the period of the CPV, and is a period for setting the potential at the time of selection for one gate line. Further, the control unit 8 sets the STV to the high level at the start of one frame, and sets the STV to the low level in the other periods. That is, the control unit 8 notifies the start of the frame by setting STV to a high level. When the gate driver detects the rising edge of CPV when STV is at the high level, the gate line of the first row is set to the potential when selected, and the gate line of the other row is set to the potential when not selected. To do. Thereafter, every time the rising edge of the CPV is detected, the gate driver sequentially switches the rows to be set to the selection potential.

  Each TFT 22 makes the drain and source conductive when the gate potential is set to the selected potential, and makes the drain and source nonconductive when the gate potential is set to the non-selected potential. . Accordingly, each pixel electrode in the selected row is in an equipotential state with the source line connected via the TFT. In addition, each pixel electrode that is not selected becomes non-conductive with the source line.

In the example shown in FIG. 6, the select gate lines Gi is, if the gate 22 _a is set to the selection period potential, and the drain 22 _b and the source 22 _c is turned equipotential pixel electrode 21 and the source line Sk become. Then, according to the potential difference between the potential V _COM of the common electrode 30 and the potential of the pixel electrode 21, the liquid crystal state between the pixel electrode 21 and the common electrode 30 is defined, and the display state in this pixel is determined.

The control unit 8 controls the driving device 1 by inputting the above-described POL ₁ , POL ₂ , SCLK, STB and the like to the driving device 1. The control unit 8 defines the selection period with the STB. In the present embodiment, a case where a control signal STV for instructing the start of one frame is also input to the driving apparatus 1 will be described as an example. The control signal input by the control unit 8 is not limited to POL ₁ , POL ₂ , SCLK, STB, and STV, and other control signals may be used.

Since the first row, which is an odd-numbered row, is selected at the start of the frame, the control unit 8 needs to set the level of POL ₂ to the high level at the start of the frame. The control unit 8 may set the level of POL ₂ to the high level based on the rising edge of STB and the falling edge of STB during the period in which STV (see FIG. 7) is at the high level. FIG. 8 is an explanatory diagram showing the timing setting of POL ₂ at the start of a frame. In FIG. 8, the part shown with the broken line is the same as that of FIG. As will be described later, the control unit 8 sets the outputs of the potential output terminals D _{1 to} D _{n + 1} of the potential setting unit 2 to a high impedance state during the period in which the STB is at the high level. In FIG. 8, this period is shown in black. However, in the present invention, each source line is connected to the V _p setting wiring 5 or the V _n setting wiring 6 while the STB is at the high level, and therefore connected to the potential output terminal in the high impedance state. Never happen. The control unit 8 may switch the level of POL ₂ from the low level to the high level during the period when the STV is set to the high level (see FIG. 8). Thereafter, the control unit 8 may switch the level of POL ₂ alternately every time STB becomes high level.

Next, a description will be given switches 11, 12, 14, 15 provided on the source line _{S 1 ~S n +} 1. When viewed from the viewing side, the 1st source line S ₁ on the left side, first end switch 11 (hereinafter, simply referred to as switch 11.) Are connected. When viewed from the viewing side, to the (n + 1) th source line S _{n + 1} from the left, the second end switch 12 (hereinafter, simply referred to as switch 12.) Are connected. Further, of the source line _S 2 to S _n other than both ends, the even-numbered source lines from the left as viewed from the viewing side _{S 2, S} 4, the., Switch 14 (hereinafter for even-numbered source lines, Simply referred to as switch 14). Further, of the source line _S 2 to S _n other than both ends, the odd-numbered source lines _S 3 from the left as viewed from the viewing _{side, S} 5, the., Switch 15 (hereinafter for odd-numbered source lines, Simply referred to as switch 15).

When the switches 11 and 12 detect the rising edge of the STB during the period when the STV (see FIGS. 7 and 8) is at the high level, the switches 11 and 12 thereafter, for each period corresponding to two STB cycles in the frame. Repeat the action specified for. The operation within the period of two STB cycles is different between the switches 11 and 12. Even for the same switch, the operation differs depending on whether POL ₁ is high or low in the frame.

In addition, when the switches 14 and 15 detect the rising edge of the STB during the period when the STV is at the high level, the switches 14 and 15 subsequently perform the operation defined for each switch within the frame for each period of one STB period. repeat. The operation in the period corresponding to two STB cycles is different between the switches 14 and 15. Even for the same switch, the operation differs depending on whether POL ₁ is high or low in the frame.

FIG. 9 is an explanatory diagram showing the operation of switching the connection destination of the source line by the switch 11. FIG. 9A shows the case where POL ₁ is at a high level, and FIG. 9B shows the case where POL ₁ is at a low level. The operation of is shown.

With reference to FIG. 9A, the operation of the switch 11 when POL ₁ is at a high level will be described. When the switch 11 detects the first rising edge in the period corresponding to two STB cycles, the switch 11 connects the source line S ₁ to the V _p setting wiring 5 while the STB is at the high level. As a result, the potential of the source line _{S 1} becomes _{V p.} Next, the switch 11 detects a falling edge of STB, while the STB is at the low level, connecting the source lines S ₁ to the potential output terminal D _1. Since POL ₁ is at a high level, the output potential of the potential output terminal D ₁ is a positive potential. Therefore, the potential of the source line S ₁ from V _p, changes to a positive polarity potential corresponding to the pixel value. That is, the source line S ₁ from being set to the precharge voltage V _p, will be set to a positive polarity potential corresponding to the pixel value. Next, when the second rising edge of the STB in the period corresponding to two STB periods is detected, the switch 11 connects the source line S ₁ to the V _p setting wiring 5 for the period corresponding to one STB period from the rising edge. Accordingly, in the period STB1 period of the second half in a period of STB2 period, the potential of the source line _{S 1} becomes _{V p.} The switch 11 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at the high level, the source line S ₁ is kept at the positive potential. Further, even when the potential output terminals D ₁ is set to the high impedance state, the source line S ₁ is maintained at a positive polarity potential.

With reference to FIG. 9B, the operation of the switch 11 when POL ₁ is at a low level will be described. When the switch 11 detects the first rising edge in the period corresponding to two STB cycles, the switch 11 connects the source line S ₁ to the V _n setting wiring 6 while the STB is at the high level. As a result, the potential of the source line _{S 1} becomes _{V n.} Next, the switch 11 detects a falling edge of STB, while the STB is at the low level, connecting the source lines S ₁ to the potential output terminal D _1. Since POL ₁ is at a low level, the output potential of the potential output terminal D ₁ is a negative potential. Therefore, the potential of the source line S ₁ from V _n, changes to a negative polarity potential corresponding to the pixel value. That is, the source line S ₁ from being set to the precharge voltage V _n, will be set to a negative polarity potential corresponding to the pixel value. Then, upon detecting the second rising edge of STB in the period STB2 cycles, switch 11 for a period of STB1 cycles from the rising edge to connect the source lines _{S 1} to _{V n} setting wire 6. Accordingly, in the period STB1 period of the second half in a period of STB2 period, the potential of the source line _{S 1} becomes _{V n.} The switch 11 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at the low level, the source line S ₁ is kept at the negative potential. Further, even when the potential output terminals D ₁ is set to the high impedance state, the source line S ₁ is kept to a negative polarity voltage.

FIG. 10 is an explanatory diagram showing the switching operation of the source line connection destination by the switch 12. FIG. 9A shows a case where POL ₁ is at a high level, and FIG. 9B shows a case where POL ₁ is at a low level. Shows the operation.

With reference to FIG. 10A, the operation of the switch 12 when POL ₁ is at a high level will be described. When the switch 12 detects the first rising edge in the period corresponding to the STB2 period, the switch 12 connects the source line Sn _{+ 1} to the V _p setting wiring 5 for the period corresponding to the STB1 period from the rising edge. Accordingly, in the period STB1 period of the first half in a period of STB2 period, the potential of the source line _{S n + 1} becomes _{V p.} Next, when the second rising edge of the STB is detected in the period corresponding to two STB cycles, the switch 12 continues to connect the source line _{Sn + 1} to the V _p setting wiring 5 while the STB is at the high level. As a result, the potential of the source line _{S n + 1} remains at _{V p.} Next, when detecting the falling edge of STB, the switch 12 connects the source line S _{n + 1} to the potential output terminal D _{n + 1} while the STB is at the low level. The switch 12 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at the high level, the source line _{Sn + 1} is kept at the positive potential. Further, even when the potential output terminal D _{n + 1} is in a high impedance state, the source line S _{n + 1} is kept at the positive potential.

With reference to FIG. 10B, the operation of the switch 12 when POL ₁ is at a low level will be described. Switch 12 detects the first rising edge in the period of STB2 cycles, periods of STB1 cycles from the rising edge to connect the source line _{S n + 1} to _{V n} setting wire 6. Accordingly, in the period STB1 period of the first half in a period of STB2 period, the potential of the source line _{S n + 1} becomes _{V n.} Then, upon detecting the second rising edge of STB in the period STB2 period, the switch 12 continues, while the STB is at high level to connect the source line _{S n + 1} to _{V n} setting wire 6. As a result, the potential of the source line _{S n + 1} remains at _{V p.} Next, when detecting the falling edge of STB, the switch 12 connects the source line S _{n + 1} to the potential output terminal D _{n + 1} while the STB is at the low level. The switch 12 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at the low level, the source line _{Sn + 1} is kept at the negative potential. Even when the potential output terminal D _{n + 1} is in a high impedance state, the source line S _{n + 1} is kept at the negative potential.

Here, the case where S _{n + 1} is an odd-numbered source line from the left and D _{n + 1} is an odd-numbered potential output terminal from the left has been described as an example. When S _{n + 1} is an even-numbered source line from the left and D _{n + 1} is an even-numbered potential output terminal from the left, the switch 12 operates when POL ₁ is at the high level and when it is at the low level. The operation is reversed. That is, if POL ₁ is at the high level, the switch 12 may perform the operation when POL ₁ is at the low level (see FIG. 10B). If POL ₁ is at a low level, the switch 12 may perform the operation when POL ₁ is at a high level (see FIG. 10A).

11A and 11B are explanatory diagrams showing the operation of switching the connection destination of the source line by the switch 14, FIG. 11A shows a case where POL ₁ is at a high level, and FIG. 11B shows a case where POL ₁ is at a low level. The operation of is shown. The switch 14 repeats the same operation every STB cycle. Further, here, the switch 14 corresponding to the source line S _2, and potential output terminals D ₂ (the second switch from the left) is described as an example, but the operation of the switches 14 is the same both.

With reference to FIG. 11A, the operation of the switch 14 when POL ₁ is at a high level will be described. Switch 14 detects the rising edge of STB, while the STB is at high level to connect the source line _{S 2} to _{V n} setting wire 6. As a result, the potential of the source line _{S 2} becomes _{V n.} Next, the switch 14 detects a falling edge of STB, STB is while a low level, connecting the source line S ₂ to the potential output terminal D _2. Since POL ₁ is at a high level, the output potentials of even-numbered potential output terminals D ₂ , D ₄ ,... From the left are negative potentials. Therefore, the potential of the source line S ₂ from V _n, changes to a negative polarity potential corresponding to the pixel value. That is, the source line S ₂ is comprised of is set to the precharge voltage V _n, to be set to a negative polarity potential corresponding to the pixel value. The switch 14 repeats the above operation within the frame. Accordingly, each even-numbered source line from the left is kept at a negative potential in a frame in which POL ₁ is at a high level.

With reference to FIG. 11B, the operation of the switch 14 when POL ₁ is at a low level will be described. When the switch 14 detects the rising edge of the STB, the switch 14 connects the source line S ₂ to the V _p setting wiring 5 while the STB is at the high level. As a result, the potential of the source line _{S 2} becomes _{V p.} Next, the switch 14 detects a falling edge of STB, STB is while a low level, connecting the source line S ₂ to the potential output terminal D _2. Since POL ₁ is at a low level, the output potentials of even-numbered potential output terminals D ₂ , D ₄ ,... From the left are positive potentials. Therefore, the potential of the source line S ₂ from V _p, changes to a positive polarity potential corresponding to the pixel value. That is, the source line S ₂ is comprised of is set to the precharge voltage V _p, to be set to a positive polarity potential corresponding to the pixel value. The switch 14 repeats the above operation within the frame. Therefore, each even-numbered source line from the left is kept at a positive potential in a frame in which POL ₁ is at a low level.

12A and 12B are explanatory diagrams showing the operation of switching the connection destination of the source line by the switch 15. FIG. 12A shows a case where POL ₁ is at a high level, and FIG. 12B shows a case where POL ₁ is at a low level. Shows the operation. The switch 15 repeats the same operation every STB cycle. Further, here, the switch 15 corresponding to the source lines S ₃ and the potential output terminals D ₃ (the third switch from the left) will be described as an example, but also the operation of the switches 15.

With reference to FIG. 12A, the operation of the switch 15 when POL ₁ is at a high level will be described. When the switch 15 detects the rising edge of the STB, the switch 15 connects the source line S ₃ to the V _p setting wiring 5 while the STB is at the high level. As a result, the potential of the source line _{S 3} becomes _{V p.} Next, the switch 15 detects a falling edge of STB, while the STB is at the low level, connecting the source lines S ₃ to the potential output terminals D _3. Since POL ₁ is at a high level, the output potentials of odd-numbered potential output terminals D ₃ , D ₅ ,... From the left are positive potentials. Therefore, the potential of the source line S ₃ from V _p, changes to a positive polarity potential corresponding to the pixel value. That is, the source lines S ₃ consists is set to the precharge voltage V _p, to be set to a positive polarity potential corresponding to the pixel value. The switch 15 repeats the above operation within the frame. Therefore, each odd-numbered source line from the left is kept at a positive potential in a frame in which POL ₁ is at a high level.

With reference to FIG. 12B, the operation of the switch 15 when POL ₁ is at a low level will be described. Switch 15 detects the rising edge of STB, while the STB is at high level to connect the source lines _{S 3} to _{V n} setting wire 6. As a result, the potential of the source line _{S 3} becomes _{V n.} Next, the switch 15 detects a falling edge of STB, while the STB is at the low level, connecting the source lines S ₃ to the potential output terminals D _3. Since POL ₁ is at a low level, the output potentials of odd-numbered potential output terminals D ₃ , D ₅ ,... From the left are negative potentials. Therefore, the potential of the source line S ₃ from V _n, changes to a negative polarity potential corresponding to the pixel value. That is, the source lines S ₃ consists is set to the precharge voltage V _n, to be set to a negative polarity potential corresponding to the pixel value. The switch 15 repeats the above operation within the frame. Therefore, each odd-numbered source line from the left is kept at a negative potential in a frame in which POL ₁ is at a low level.

FIG. 13 is an explanatory diagram showing the relationship between the control signals STB, POL ₁ and POL ₂ output from the control unit 8 and the potential of each source line. Here, a description will be given by taking as an example a frame in which POL ₁ is at a high level. Here, a case where n + 1 is an odd number will be described as an example.

The control unit 8 starts up the first STB in the frame. At this time, the control unit 8 switches POL ₁ to the high level at the rising edge of the first STB in the frame, and thereafter maintains POL ₁ at the high level in the frame. Further, the control unit 8 switches POL ₂ to high level during the period when STB first becomes high level in the frame, and thereafter switches the level of POL ₂ alternately for each STB cycle.

When the rising edge of the first STB in the frame is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows while the STB is at a high level. The switch 11 connects the source line S ₁ to the V _p setting wiring 5. The switch 12 connects the source line S _{n + 1} to the V _p setting wiring 5. Also, among the switches other than the switches 11 and 12, the switches 14 of the even-numbered from the left to connect the corresponding source line V _n setting wire 6. Among the switches other than the switches 11 and 12, each odd-numbered switch 15 from the left connects the corresponding source line to the V _p setting wiring 5. As a result, during the period in which STB becomes high level, the source line _{S 1,} S 3, · · _·, the potential of _{S n + 1} becomes _{V p.} In addition, the source line _{S 2, S 4, ···,} the potential of the _{S n} is the _{V n.} Accordingly, even when the output at each potential output terminal is in a high impedance state during the period when STB is at a high level, the potential of each source line is set to V _p or V _n and does not become unstable. .

Next, when the falling edge of the STB is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows while the STB is at the low level. Switch 11 to connect the source lines _{S 1} to the potential output terminal _{D 1.} Switch 12 will continue to be connected to _{V p} set wire 5 the source line _{S n + 1.} Each switch 14 connects the corresponding source line to the even-numbered potential output terminal from the left. Each switch 15 connects a corresponding source line to an odd-numbered potential output terminal from the left. At this time, since POL ₂ is at high level, the potential corresponding to the n pixel values for one row are output from the potential output terminals _D 1 to D _n, the potential of the source line _S 1 to S _n each The potential is set according to the pixel value. As a result, the n pixel electrodes in the first row have the same potential as that of the left source line as viewed from the viewing side. Since POL ₁ is at a high level, the odd-numbered potential output terminals D ₁ , D ₃ ,... From the left have positive polarity and the even-numbered potential output terminals D ₂ , D from the left. ₄ ,... Are negative potentials. Therefore, the polarity of each pixel in the first row changes from the left pixel to positive polarity, negative polarity, positive polarity, negative polarity,..., And adjacent pixels have different polarities.

At this time, the source line _{Sn + 1} is not used for pixel setting of the pixel electrode. However, since the potential of the source line S _{n + 1} is set to V _p, the output of the potential output terminals D _{n + 1} is a high-impedance state, is not the potential of the source line S _{n + 1} becomes unstable.

When the next rising edge of STB is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows during the period when STB is at a high level. The switch 11 connects the source line S ₁ to the V _p setting wiring 5. The switch 12 connects the source line S _{n + 1} to the V _p setting wiring 5. Each switch 14, to connect the corresponding source line V _n setting wire 6. Each switch 15 connects the corresponding source line to the V _p setting wiring 5. As a result, during the period in which STB becomes high level, the source line _{S 1,} S 3, · · _·, the potential of _{S n + 1} becomes _{V p.} In addition, the source line _{S 2, S 4, ···,} the potential of the _{S n} is the _{V n.} Therefore, the potential of each source line is set to V _p or V _n and does not become unstable.

During this time, POL ₂ is switched to the low level.

Next, when the falling edge of the STB is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows while the STB is at the low level. The switch 11 continues to connect the source line S ₁ to the V _p setting wiring 5. The switch 12 connects the source line S _{n + 1} to the potential output terminal D _{n + 1} . Each switch 14 connects the corresponding source line to the even-numbered potential output terminal from the left. Each switch 15 connects a corresponding source line to an odd-numbered potential output terminal from the left. At this time, since POL ₂ is at a low level, potentials corresponding to n pixel values for one row are output from the potential output terminals D _{2 to} D _{n + 1} , and the potentials of the source lines S _{2 to} S _{n + 1} are respectively The potential is set according to the pixel value. As a result, the n pixel electrodes in the second row have the same potential as that of the source line on the right side when viewed from the viewing side. Since POL ₁ is at a low level, the output potentials of the even-numbered potential output terminals D ₂ , D ₄ ,... From the left are negative potentials, and the odd-numbered potential output terminals D ₃ , D from the left. ₅ ,... Are positive potentials. Therefore, the polarity of each pixel in the second row changes from the left pixel to negative polarity, positive polarity, negative polarity, positive polarity,..., And adjacent pixels have different polarities.

At this time, the source line S ₁ is not used in the pixel set of the pixel electrode. However, the potential of the source line S ₁ is so set to V _p, even output high impedance state of the potential output terminals D _1, not the potential of the source line S ₁ is unstable.

  Thereafter, the driving device 1 repeats the above operation every period of two STB cycles. As a result, the polarities of the pixels in each row are as shown in FIG. That is, in the odd-numbered rows, the positive polarity, negative polarity, positive polarity, negative polarity, ... from the left, and in the even-numbered rows, the negative polarity, positive polarity, negative polarity, positive polarity, ... from the left. It becomes. In FIG. 14, “+” represents positive polarity, and “−” represents negative polarity. This also applies to FIGS. 16, 24, 26, and the like.

FIG. 15 is an explanatory diagram showing the relationship between the control signals STB, POL ₁ and POL ₂ and the potential of each source line. In FIG. 15, unlike FIG. 13, a frame in which POL ₁ is at a low level is described as an example. Here, n + 1 is an odd number.

The control unit 8 starts up the first STB in the frame. At this time, the control unit 8 switches POL ₁ to the low level in conjunction with the rising edge of the first STB in the frame, and thereafter maintains POL ₁ at the low level in this frame. Further, the control unit 8 switches POL ₂ to high level during the period when STB first becomes high level in the frame, and thereafter switches the level of POL ₂ alternately for each STB cycle.

When the rising edge of the first STB in the frame is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows while the STB is at a high level. The switch 11 connects the source line S ₁ to the V _n setting wiring 6. The switch 12 connects the source line S _{n + 1} to the V _n setting wiring 6. Each switch 14 connects the corresponding source line to the V _p setting wiring 5. Each switch 15, to connect the corresponding source line V _n setting wire 6. As a result, the potentials of the source lines S ₁ , S ₃ ,..., S _{n + 1} become V _n during the period when STB is at the high level. In addition, the source line _{S 2, S 4, ···,} the potential of the _{S n} is the _{V p.} Accordingly, even when the output at each potential output terminal is in a high impedance state during the period when STB is at a high level, the potential of each source line is set to V _p or V _n and does not become unstable. .

Next, when the falling edge of the STB is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows while the STB is at the low level. Switch 11 to connect the source lines _{S 1} to the potential output terminal _{D 1.} The switch 12 continues to connect the source line S _{n + 1} to the V _n setting wiring 6. Each switch 14 connects the corresponding source line to the even-numbered potential output terminal from the left. Each switch 15 connects a corresponding source line to an odd-numbered potential output terminal from the left. At this time, since POL ₂ is at high level, the potential corresponding to the n pixel values for one row are output from the potential output terminals _D 1 to D _n, the potential of the source line _S 1 to S _n each The potential is set according to the pixel value. As a result, the n pixel electrodes in the first row have the same potential as that of the left source line as viewed from the viewing side. Since POL ₁ is at a low level, the output potentials of odd-numbered potential output terminals D ₁ , D ₃ ,... From the left are negative potentials, and even-numbered potential output terminals D ₂ , D from the left. ₄ ,... Are positive potentials. Therefore, the polarity of each pixel in the first row changes from the left pixel to negative polarity, positive polarity, negative polarity, positive polarity,..., And adjacent pixels have different polarities.

At this time, the source line _{Sn + 1} is not used for pixel setting of the pixel electrode. However, since the potential of the source line _{Sn + 1} is set to Vn, even _{if the} output of the potential output terminal Dn _{+ 1} is in a high impedance state, the potential of the source line _{Sn + 1} does not become unstable.

When the next rising edge of STB is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows during the period when STB is at a high level. The switch 11 connects the source line S ₁ to the V _n setting wiring 6. The switch 12 continues to connect the source line S _{n + 1} to the V _n setting wiring 6. Each switch 14 connects the corresponding source line to the V _p setting wiring 5. Each switch 15, to connect the corresponding source line V _n setting wire 6. As a result, the potentials of the source lines S ₁ , S ₃ ,..., S _{n + 1} become V _n during the period when STB is at the high level. In addition, the source line _{S 2, S 4, ···,} the potential of the _{S n} is the _{V p.} Therefore, the potential of each source line is set to V _p or V _n and does not become unstable.

During this time, POL ₂ is switched to the low level.

Next, when the falling edge of the STB is detected, each of the switches 11, 12, 14, and 15 (see FIG. 1) operates as follows while the STB is at the low level. The switch 11 continues to connect the source line S ₁ to the V _n setting wiring 6. The switch 12 connects the source line S _{n + 1} to the potential output terminal D _{n + 1} . Each switch 14 connects the corresponding source line to the even-numbered potential output terminal from the left. Each switch 15 connects a corresponding source line to an odd-numbered potential output terminal from the left. Since POL ₂ is at a low level, potentials corresponding to n pixel values for one row are output from the potential output terminals D _{2 to} D _{n + 1} , and the potentials of the source lines S _{2 to} S _{n + 1} are set to the respective pixel values. The electric potential is set accordingly. As a result, the n pixel electrodes in the second row have the same potential as that of the source line on the right side when viewed from the viewing side. In addition, since POL ₁ is at a low level, the output potentials of even-numbered potential output terminals D ₂ , D ₄ ,... From the left are positive potentials, and odd-numbered potential output terminals D ₃ , D from the left. ₅ ,... Are negative potentials. Therefore, the polarity of each pixel in the second row changes from the left pixel to positive polarity, negative polarity, positive polarity, negative polarity,..., And the adjacent pixels have different polarities.

At this time, the source line S ₁ is not used in the pixel set of the pixel electrode. However, the potential of the source line S ₁ is so set to V _n, be an output is high impedance state of the potential output terminals D _1, not the potential of the source line S ₁ is unstable.

  Thereafter, the driving device 1 repeats the above operation every period of two STB cycles. As a result, the polarities of the pixels in each row are as shown in FIG. That is, the odd-numbered rows are negative, positive, negative, positive, and so on, and the even-numbered rows are positive, negative, positive, negative, and so on.

Since POL ₁ changes alternately every frame, the polarity of each pixel changes alternately between the state shown in FIG. 14 and the state shown in FIG. 16 for each frame.

Further, as described above, each source line, when not connected to the potential output terminal for outputting a potential corresponding to the pixel value is connected to V _p setting wiring 5 or V _n setting wire 6. Therefore, the potential of the source line does not become unstable. Also in the source line _{S 1, S n +} 1 is not used in the potential setting of the pixel electrode selection period, the source lines _{S 1, S n +} 1 is connected to _{V p} setting wiring 5 or _{V n} setting wire 6. Therefore, the potential does not become unstable with respect to the source lines S ₁ and _{Sn + 1} .

  Further, as shown in FIGS. 14 and 16, since the polarities of adjacent pixels are different from each other, crosstalk can be prevented.

Further, the potential of the individual source lines, maintained at positive potential or negative potential within one frame, does not change across the V _COM (see FIG. 13, FIG. 15). Therefore, power consumption can be suppressed.

Further, when a potential corresponding to the pixel value is set for each source line, if the potential is a positive potential, the driving device 1 sets the potential of the source line to V _p and then according to the pixel value. Set the potential. Further, when the potential corresponding to the pixel value is negative potential, the driving device 1, the potential of the source line from the V _n, sets the potential corresponding to the pixel value. Therefore, power consumption can be suppressed.

  Next, a configuration example of the potential setting unit 2 will be described. FIG. 17 is an explanatory diagram illustrating a configuration example of the potential setting unit 2. The potential setting unit 2 includes, for example, a shift register 61, a first latch unit 62, a second latch unit 63, a level shifter 64, an output switching unit 65, a DA converter 66, and a voltage follower 67. .

SCLK, STH, and STB are input to the shift register 61 from the control unit 8 (see FIG. 1). The shift register 61 includes n signal output terminals C _{1 to} C _n which are the same number as the number of pixels for one row. The shift register 61 outputs a data read instruction signal from one signal output terminal to the signal input terminal of the first latch unit 62 at every rising edge of SCLK. The shift register 61 outputs a data read instruction signal in the order of the signal output terminals C ₁ , C ₂ ,..., C _n . The control signal STH is a signal for instructing start of data acquisition for one line. For example, control unit 8 in the case of instructing the start of output from signal output terminal C _1, and the STH to high level, in other periods the STH to low level. Shift register 61, when STH is at high level, if it detects the rising edge of SCLK, and outputs the data reading instruction signal from the signal output terminal C _1, since, for each rising edge of SCLK, sequentially, the signal output Switch the edge.

The first latch unit 62 has signal input terminals L _{1 to} L _n corresponding to the signal output terminals C _{1 to} C _n . The first latch portion 62, when the data reading instruction signal from the signal input terminal L _i is input, reads data of the i-th pixel from the left in the one line (pixel values). In this example, the pixels for one line are arranged in the order of R, G, and B. Therefore, the first latch unit 62 includes the pixels in the order of R, G, B, R, G, B,. Read the value. The first latch unit 62 holds the read data in order.

In addition, SCLK is input to the shift register 61 from the control unit so that signal output from the signal output terminals C _{1 to} C _n is performed within one cycle of STB. Therefore, data for one line is held in the first latch unit 62 during one STB cycle. The data for one line is collectively read into the second latch unit 63.

The first latch unit 62 has n output terminals L ′ _{1 to} L ′ _n as terminals used to output n data for one line.

The second latch unit 63 includes data read terminals Q _{1 to} Q _n corresponding to the output terminals L ′ _{1 to} L ′ _n of the first latch unit 62. The timing at which the second latch unit 63 reads data from the first latch unit 32 and outputs the data is defined by the STB. The second latch unit 63 collectively reads data for one line for each falling edge of the STB, and outputs the data from the data output terminals Q ′ _{1 to} Q ′ _n . The control unit outputs the STB to the shift register 61, the second latch unit 63, and the DA converter 66.

The level shifter 64 has n data input terminals U _{1 to} U _n and n data output terminals U ′ _{1 to} U ′ _n . Each data input terminals _U 1 ~U _n is connected to the data output terminals Q _'1 ~Q' _n of the second latch section 63. The level shifter 64 performs a level shift relative to input to the data input terminals U ₁ ~U _n data, and outputs the data after the level shift from the data output terminals U _'1 ~U' _n. For example, when the output data of the second latch unit 63 is a low voltage system (for example, 3V system), the level shifter 64 level-shifts the data to a high voltage system (for example, 15V system), and the data output terminal Output.

Output switching unit 65 includes n input terminals _I 1 ~I _n is equal to the number of pixels of one row, and the n + 1 output terminals _O 1 _{~ O n + 1.} The number of output terminals of the output switching unit 65 is the same as the number of source lines. POL ₂ is input to the output switching unit 65. If each input terminal of the output switching unit 65 is I _k (where 1 ≦ k ≦ n), the output switching unit 65 converts the data input from the level shifter 64 to the input terminal I _k according to POL _2. Output from _one of the output terminals O _k and O _{k + 1} . When POL ₂ is at high level, the output switching unit 65 outputs the input to the input terminal I _k data from the output terminal O _k. Further, when POL ₂ is at a low level, the output switching unit 65 outputs data input to the input terminal I _k from the output terminal _{Ok + 1} . Therefore, when POL ₂ is at high level, a row of data input to the input terminal _I 1 ~I _n, from the output terminal _O 1 ~ O _n from first left as viewed from the viewing side to the n-th Output. On the other hand, when POL ₂ is at low level, a row of data input to the input terminal _I 1 ~I _n, from the output terminal _O 2 _{~ O n + 1} from the second from the left as viewed from the viewing side to the n + 1 th Output.

FIG. 18 is an explanatory diagram illustrating a configuration example of the output switching unit 65. Output switching unit 65 includes, for example, the first transistor 73 and second transistor 74 for each individual input _{I k.} Input I _k is connected to the first terminal of the first transistor 73, a second terminal of the first transistor 73 is connected to the output terminal O _k. Similarly, the input terminal I _k is connected to the first terminal of the second transistor 74, and the second terminal of the second transistor 74 is connected to the output terminal _{Ok + 1} . Each of the first transistor 73 and the second transistor 74 includes a third terminal in addition to the first terminal and the second terminal, and when a high level signal (voltage) is input to the third terminal, When a low level signal (voltage) is input to the third terminal, the first terminal and the second terminal are turned off.

The control signal POL ₂ is input from the control unit 8 to the third terminal of each first transistor 73. Further, the output switching unit 65 includes a signal inverting unit 75. POL ₂ is input from the control unit 8 to the signal inversion unit 75. Signal inverter 75, the POL ₂ input inverted to the low level if a high level, POL ₂ is input inverted to the high level if low. Then, the signal inverter 75 inputs the inverted POL ₂ to the third terminal of each second transistor 74.

Therefore, when POL ₂ is at high level, high level POL ₂ is input to the third terminal of each first transistor 73, and low level POL ₂ is input to the third terminal of each second transistor 74. The As a result, the input terminals I _k are brought into conduction and the output terminal O _k, becomes non-conductive state, the output terminal O _{k + 1.} Thus, input to the input terminal I _k data is output from the output terminal O _k.

On the other hand, when POL ₂ is at low level, low level POL ₂ is input to the third terminal of each first transistor 73, and high level POL ₂ is input to the third terminal of each second transistor 74. The As a result, the input terminals I _k becomes the output terminal O _k and a non-conducting state, becomes conductive and the output terminal O _{k + 1.} Therefore, the data input to the input terminal _Ik is output from the output terminal _{Ok + 1} .

In other words, POL ₂ can be said to be a control signal for controlling whether the input terminal I _k is connected to either the output terminal O _k or O _{k + 1} .

The DA converter 66 has n + 1 data input terminals T _{1 to} T _{n + 1} and n + 1 potential output terminals T ′ _{1 to} T ′ _{n + 1} . Each data input terminals _{T 1 ~T n +} 1 is connected to the output terminal _{O 1 ~O n +} 1 of the output switching unit 65. The DA converter 66 converts data input from the data input terminals T _{1 to} T _{n + 1} into an analog voltage and outputs the analog voltage from the potential output terminals T ′ _{1 to} T ′ _{n + 1} . Further, the D-A converter 66 receives the voltages V _{0 to} V ₈ and V _{9 to} V ₁₇ from the power supply unit 9 (see FIG. 1), and generates potentials corresponding to 64 gradations by voltage division. . Then, the potential corresponding to the data after the voltage division is output as the potential after analog conversion. That is, the DA converter 66 converts each row of data (level-shifted data) into any one of 64 gradation potentials according to the data and outputs the converted data. However, here, a case where the gradation of the image is 64 gradations will be described as an example, but the type of voltage input to the DA converter 66 is not limited to V _{0 to} V ₁₇ , and the image The gradation is not limited to 64 gradations

Further, POL ₁ is input from the control unit 8 to the DA converter 66. The DA converter 66 determines whether the output potentials of the potential output terminals T ′ _{1 to} T ′ _{n + 1} are set higher than V _COM or lower than V _COM depending on whether POL ₁ is high level or low level. Switch. Specifically, when the POL ₁ is at the high level, the DA converter 66 sets the odd-numbered potential output terminals T ′ ₁ , T ′ ₃ ,... From the left to the output potential higher than V _COM. and then, the even-numbered potential output terminals T from the left _'2, T' _4, the output potential of ... and potentials lower than _{V COM.} Conversely, when POL ₁ is at the low level, the DA converter 36 sets the output potentials of the odd-numbered potential output terminals T ′ ₁ , T ′ ₃ ,... From the left to potentials lower than V _COM . The output potentials of even-numbered potential output terminals T ′ ₂ , T ′ ₄ ,... From the left are set to potentials higher than V _COM .

That is, when POL ₁ is at a high level, any potential (positive potential) from V _{0 to} V ₈ is supplied from odd-numbered potential output terminals T ′ ₁ , T ′ ₃ ,. .., And any potential (negative potential) of V _{9 to} V ₁₇ is output from the even-numbered potential output terminals T ′ ₂ , T ′ ₄ ,. On the contrary, when POL ₁ is at the low level, any potential of V _{9 to} V ₁₇ is output from the odd-numbered potential output terminals T ′ ₁ , T ′ ₃ ,. A potential of any one of V _{0 to} V _{8 and the} like is output from the second potential output terminals T ′ ₂ , T ′ ₄ ,.

However, when POL ₂ is at high level, not input data to the input terminal T _{n + 1,} in this case, the output state of the potential output terminals T _{'n + 1,} for example, may be a high impedance state. Similarly, when POL ₂ is at low level, no data is input to the input terminal T _1, in this case, the output state of the potential output terminals T _'1, for example, may be set to impedance state.

In the present embodiment, the control unit 8 (see FIG. 1) switches POL ₁ alternately between a high level and a low level every frame. As a result, during one frame, the output potential from each potential output terminal in the DA converter 66 is maintained as a positive potential or a negative potential. However, when the STB is at a high level, the DA converter 66 sets the outputs of the potential output terminals T ′ _{1 to} T ′ _{n + 1} to a high impedance state.

Note that POL ₁ may be input to the second latch unit 63, but the operation of the second latch unit 63 is not affected by POL ₁ .

The voltage follower 67 has n + 1 potential input terminals W _{1 to} W _{n + 1} corresponding to the potential output terminals T ′ _{1 to} T ′ _{m + 1} of the DA converter 66. In addition, n + 1 potential output terminals D _{1 to} D _{n + 1} that output a potential equal to the potential input to each potential input terminal of the voltage follower 67 are provided. Potential output terminals _D 1 _{to D n + 1} of the voltage follower 67, corresponds to the potential output terminals _D 1 _{to D n + 1} of the potential setting section 2, for each potential output terminals _D 1 _{to D n + 1} of the voltage follower 67, shown in FIG. 1 A switch (one of switches 11, 12, 14, and 15) is provided.

With the configuration described above, the potential setting unit 2 outputs a potential corresponding to n pixel values for one row from the potential output terminals D _{1 to} D _n when POL ₂ is at a high level. Further, POL ₂ is at the low level, outputs a potential corresponding from the potential output terminals _D 2 _{to D n + 1} to n of the pixel values of one row.

The potential setting unit 2 outputs a positive potential from the odd-numbered potential output terminal from the left and outputs a negative potential from the even-numbered potential output terminal from the left in the frame in which POL ₁ is at the high level. In a frame in which POL ₁ is at a low level, a negative potential is output from the odd-numbered potential output terminal from the left, and a positive potential is output from the even-numbered potential output terminal from the left.

  However, the configuration illustrated in FIG. 17 is an example of the configuration of the potential setting unit 2, and the configuration of the potential setting unit 2 is not limited to the configuration illustrated in FIG. For example, the output switching unit 65 may be arranged not at a position between the level shifter 64 and the DA converter 66 but at another location. Further, here, the case where the potential setting unit 2 reads one row of data serially has been illustrated, but, for example, a configuration in which R, G, B data is read in parallel may be used. The data read by the potential setting unit 2 may be monochrome image data instead of R, G, and B data.

In the description of the first embodiment, the case where the control unit 8 inputs POL ₂ to the driving device 1 has been described. Instead of the controller 8 generating POL ₂ , the driving device 1 (for example, the potential setting unit 2 in the driving device 1) may generate POL ₂ and operate according to POL ₂ . FIG. 19 is an explanatory diagram showing a mode in which the potential setting unit 2 generates POL ₂ . In this case, the control unit 8 inputs the STV not only to the gate driver (not shown) but also to the potential setting unit 2. Thereby, the potential setting unit 2 can determine the start of the frame. The potential setting unit 2 inputs the generated POL ₂ to the output switching unit 65. If the STB input from the control unit 8 becomes high level during the period when the STV input from the control unit 8 is high level, the potential setting unit 2 becomes high level. During this period, the POL ₂ level may be switched from the low level to the high level (see FIG. 19). Note that during the period when the STB is at the high level, the outputs of the potential output terminals T ′ _{1 to} T ′ _n are in a high impedance state, for example. Thereafter, the potential setting unit 2 may switch the level of POL ₂ alternately every time STB becomes high level.

Further, in the above first embodiment, after the preliminary potential setting period (in the above example, left side) predetermined side from the first potential output terminals D ₁ or n + 1-numbered potential output terminals D _{n + 1} to a high impedance state The case of making was explained as an example. At this time, the first source line S ₁ or the (n + 1) th source line S _{n + 1} from the predetermined side is connected to the V _p setting unit 3 or the V _n setting unit 4. That is, the potential output terminals D ₁ or D _{n + 1} is in a state not connected to the source line (open state). Therefore, at this time, it may not be the first potential output terminals D ₁ and n + 1-numbered potential output terminals D _{n + 1} in a high impedance state.

[Embodiment 2]
In the first embodiment, the pixel electrodes in the odd-numbered rows are connected to the left source line, and the pixel electrodes in the even-numbered rows are connected to the right source line. In the second embodiment, a plurality of consecutive rows are grouped, and the pixel electrodes of each row in the odd-numbered group are connected to the left source line when viewed from the viewing side, and each row in the even-numbered group is connected. The pixel electrode is connected to the right source line.

FIG. 20 is an explanatory diagram illustrating an example of _a liquid crystal display panel 20a included in the liquid crystal display device according to the second embodiment of the present invention. Components similar to those of the liquid crystal display panel 20 in the first embodiment are denoted by the same reference numerals as those in FIG.

The liquid crystal display panel 20 _a includes a plurality of pixel electrodes 21 arranged in a matrix, for sandwiching a liquid crystal (not shown) between the common electrode (not shown in FIG. 20). In each row of the liquid crystal display panel 20 _a, each pixel, R (red), repeatedly arranged in the order of G (green), B (blue).

Also in this embodiment, it is assumed that the number of pixels for one row is n, and the number of pixel electrodes arranged in one row is n. The liquid crystal display panel 20 _a includes n + 1 source lines S _{1 to} S _{n + 1} which is one more than the number of pixels per row. As in the first embodiment, one column of pixel electrodes is provided between adjacent source lines. In other words, the liquid crystal display panel _20a includes a source line on the left side of each column of pixel electrodes, and also includes a source line on the right side of the rightmost pixel column.

  Each pixel electrode 21 is provided with an active element 22, and each pixel electrode 21 is connected to the source line via the active element 22. The above points are the same as those of the liquid crystal display panel 20 in the first embodiment. Here, as in the first embodiment, a case where the active element 22 is a TFT will be described as an example.

  In the second embodiment, each row of the pixel electrodes 21 is made into one group for each of a plurality of consecutive rows. FIG. 20 shows a case where two consecutive rows are grouped. However, the number of rows per group is not limited to two. For example, one group may be formed every three consecutive rows or every four rows. The number of rows in one group may be N / 2−1 or less, where N is the number of rows of the pixel electrodes 21.

  In the following description, a case where one group is set for every two consecutive rows is taken as an example. Therefore, the first row and the second row of the pixel electrode 21 are the first group, and the third row and the fourth row are the second group. Subsequent lines are similarly divided into groups.

  Each pixel electrode 21 in each row in the odd-numbered group is connected to the left source line through the TFT 22 as viewed from the viewing side. In the odd-numbered group, the TFT 22 is provided, for example, on the left side of the pixel electrode 21. However, the arrangement position of the TFT 22 is not limited to this position, and may be arbitrary.

  Each pixel electrode 21 in each row in the even-numbered group is connected to the source line on the right side as viewed from the viewing side via the TFT 22. In the even-numbered group, the TFT 22 is provided, for example, on the right side of the pixel electrode 21. However, like the above case, the arrangement position of the TFT is not limited to this position, and may be arbitrary.

The power supply unit 9 is the same as that in the first embodiment. The configuration of the driving device 1 is the same as that of the first embodiment (see FIG. 1). In the second embodiment, the case where the source line _{Sn + 1} is an odd-numbered source line from the left and the potential output terminal Dn _{+ 1} is an odd-numbered potential output terminal from the left will be described as an example.

In the present embodiment, the operations of the switches 11 and 12 corresponding to the respective source lines are different from those in the first embodiment. The operations of the switches 14 and 15 are the same as those in the first embodiment. Further, the output mode of POL ₂ of the control unit 8 is different from that of the first embodiment.

  The liquid crystal display device of the second embodiment also includes a gate driver (not shown) that sets the potential of each gate line, as in the first embodiment. The gate driver sequentially selects the gate lines one by one, sets the selected gate lines to the selected potential, and sets the unselected gate lines to the unselected potential. Accordingly, each row in each group is selected one by one. The drive device 1 may have a function as a gate driver.

The control unit 8 controls the driving apparatus 1 by outputting POL ₁ , POL ₂ , SCLK, and STB. The output modes of SCLK, STB and STV are the same as those in the first embodiment. That is, the control unit 8 defines a selection period by STB, and the potential setting unit 2 sequentially takes in data for one row using SCLK. Further, the control unit 8 sets the STV to the high level at the start of the frame, and sets the STV to the low level during the other periods. Each of the switches 11, 12, 14, and 15 starts operation within one frame when detecting the rising edge of the STB when the STV is at the high level.

Further, the control unit 8 alternately switches the level of POL ₁ between a high level and a low level for each frame. The output mode of this POL ₁ is the same as that of the first embodiment. However, in the present embodiment, the control unit 8 switches the POL ₂ level alternately between a high level and a low level for each group. Specifically, the control unit 8 sets POL ₂ to a high level within a period in which each row in the first group in the frame is selected regardless of the frame, and thereafter, every time the group is switched, POL ₂ The level of is alternately switched.

By switching POL ₂ for each group, the potential setting unit 2 outputs an electric potential corresponding to each pixel for one row from the potential output terminals D _{1 to} D _n, and the potential output terminals D _{2 to} D _{n + 1.} The operation of outputting a potential corresponding to each pixel for one row is switched for every period in which all the rows in the group are scanned.

Also in the present embodiment, if the control unit 8 sets the STB to the high level in accordance with the CPV when the STV (see FIG. 7) is set to the high level, the POL is output during the period in which the STB is set to the high level. The level ₂ may be switched from the low level to the high level. Thereafter, if the number of rows constituting the group is g, the control unit 8 may repeatedly switch the level of POL ₂ during the period when the STB after g times is at the high level.

Next, the switches 11 and 12 (see FIG. 1) in the present embodiment will be described. When the switches 11 and 12 detect the rising edge of the STB during the period when the STV is at the high level, the switch 11 and 12 thereafter multiply the number corresponding to two groups of rows within the frame by the period of the STB ( Hereinafter, it is referred to as a scanning period for two groups.) Every time the operation determined for each switch is repeated. The operation within this period is different between the switches 11 and 12. Even for the same switch, the operation differs depending on whether POL ₁ is high or low in the frame.

  The scanning period for two groups is divided into a first half period and a second half period. Both the first half and the second half are periods obtained by multiplying the STB cycle by the number corresponding to one group of rows. This period of time is hereinafter referred to as a scanning period for one group.

FIG. 21 is an explanatory diagram illustrating a source line connection destination switching operation by the switch 11 according to the second embodiment. FIG. 21A shows a case where POL ₁ is at a high level, and FIG. 21B shows an operation when POL ₁ is at a low level.

With reference to FIG. 21A, the operation of the switch 11 when POL ₁ is at a high level will be described. When the switch 11 detects the first rising edge in the scanning period for two groups, the source line is used while the STB is at a high level during the scanning period for one group in the first half in the scanning period for two groups. S ₁ is connected to the V _p setting wiring 5. Further, while the STB is at the low level, connecting the source lines S ₁ to the potential output terminal D _1. Therefore, in this first half period, a setting mode in which the positive potential according to the pixel value is set after the precharge potential V _p is set in the source line S ₁ is repeated. The number of repetitions is the number of rows in one group (2 rows in the example shown in FIG. 20). Thereafter, the switch 11 continues to connect the source line S ₁ to the V _p setting wiring 5 during the scanning period of one group in the latter half of the scanning period of two groups. Thus, during this second half of the period, the potential of the source line S ₁ becomes V _p. The switch 11 repeats the above operation within the frame. Accordingly, in the frame in which POL ₁ is at the high level, the source line S ₁ is kept at the positive potential. Further, even when the potential output terminals D ₁ is set to the high impedance state, the source line S ₁ is maintained at a positive polarity potential.

With reference to FIG. 21B, the operation of the switch 11 when POL ₁ is at a low level will be described. When the switch 11 detects the first rising edge in the scanning period for two groups, the source line is used while the STB is at a high level during the scanning period for one group in the first half in the scanning period for two groups. to connect the S ₁ to _{V n} setting wire 6. Further, while the STB is at the low level, connecting the source lines S ₁ to the potential output terminal D _1. Therefore, in the period of this first half, the source line S _1, since the set precharge voltage V _n, setting an embodiment that a negative polarity potential corresponding to the pixel value is set is repeated. The number of repetitions is the number of rows in one group. Thereafter, the switch 11 continues to connect the source line S ₁ to the V _n setting wiring 6 during the scanning period of one group in the latter half of the scanning period of two groups. Thus, during this second half of the period, the potential of the source line S ₁ becomes V _n. The switch 11 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at a low level, the source line S ₁ is kept negative. Further, even when the potential output terminals D ₁ is set to the high impedance state, the source line S ₁ is kept to a negative polarity voltage.

FIG. 22 is an explanatory diagram illustrating a source line connection destination switching operation by the switch 12 according to the second embodiment. 22A shows a case where POL ₁ is at a high level, and FIG. 22B shows an operation when POL ₁ is at a low level.

With reference to FIG. 22A, the operation of the switch 12 when POL ₁ is at a high level will be described. When the switch 12 detects the first rising edge in the scanning period for two groups, the switch 12 connects the source line _{Sn + 1} to the V _p setting wiring 5 during the scanning period for the first half of the scanning period for two groups. Continue to let. Therefore, in the period of this first half, the potential of the source line _{S n + 1} becomes _{V p.} Thereafter, during the scanning period for one group in the latter half of the scanning period for two groups, the switch 12 connects the source line _{Sn + 1} to the V _p setting wiring 5 while the STB is at the high level. Further, while the STB is at the low level, the source line S _{n + 1} is connected to the potential output terminal D _{n + 1} . Therefore, in this second half period, the setting mode in which the positive potential according to the pixel value is set after the precharge potential V _p is set in the source line _{Sn + 1} is repeated. The number of repetitions is the number of rows in one group (2 rows in the example shown in FIG. 20). The switch 12 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at the high level, the source line _{Sn + 1} is kept at the positive potential. Further, even when the potential output terminal D _{n + 1} is in a high impedance state, the source line S _{n + 1} is kept at the positive potential.

With reference to FIG. 22B, the operation of the switch 12 when POL ₁ is at a low level will be described. Switch 12 detects the first rising edge in the scanning period of the second group component, during the scanning period of one group of the first half in the scanning period of 2 groups content, connects the source line S _{n + 1} to V _n setting wiring 6 Continue to let. Therefore, in the period of this first half, the potential of the source line _{S n + 1} becomes _{V n.} Thereafter, during the scanning period for one group in the latter half of the scanning period for two groups, the switch 12 connects the source line S _{n + 1} to the V _n setting wiring 6 while the STB is at the high level. Further, while the STB is at the low level, the source line S _{n + 1} is connected to the potential output terminal D _{n + 1} . Therefore, in this second half period, the setting mode in which the negative potential according to the pixel value is set after the precharge potential V _n is set in the source line S _{n + 1} is repeated. The number of repetitions is the number of rows in one group. The switch 12 repeats the above operation within the frame. Therefore, in the frame in which POL ₁ is at the low level, the source line _{Sn + 1} is kept at the negative potential. Even when the potential output terminal D _{n + 1} is in a high impedance state, the source line S _{n + 1} is kept at the negative potential.

Here, the case where S _{n + 1} is an odd-numbered source line from the left and D _{n + 1} is an odd-numbered potential output terminal from the left has been described as an example. When S _{n + 1} is an even-numbered source line from the left and D _{n + 1} is an even-numbered potential output terminal from the left, the switch 12 operates when POL ₁ is at the high level and when it is at the low level. The operation is reversed. That is, if POL ₁ is at a high level, the switch 12 may perform the operation when POL ₁ is at a low level (see FIG. 22B). If POL ₁ is at a low level, the switch 12 may perform the above-described operation when POL ₁ is at a high level (see FIG. 22A). However, in the following description, the case where n + 1 is an odd number is taken as an example.

  The operation of the switch 14 in this embodiment is the same as that in the first embodiment (see FIG. 11). The operation of the switch 15 in this embodiment is the same as that in the first embodiment (see FIG. 12).

FIG. 23 is an explanatory diagram illustrating an example of STB, POL ₁ , and POL _{2 in} a frame in which POL ₁ is at a high level in the second embodiment. When the controller 8 starts up the first STB in this frame, it switches POL ₁ to the high level in conjunction with the rising edge of the STB, and thereafter maintains POL ₁ at the high level in this frame. To do. Further, the control unit 8 switches POL ₂ to the high level during the period in which the STB is initially at the high level in the frame, and thereafter, assuming that the number of rows constituting the group is g, The switching of the level of POL ₂ is repeated during the period when the level becomes high. In other words, the POL ₂ level is alternately switched every scanning period for one group.

Operation of each of the switches 11, 12, 14, 15 (see FIG. 1) during a period in which each row of the first group is selected one row after the rising edge of the first STB in the frame in which POL ₁ becomes high level Will be explained. During a period in which each row of the first group is selected one by one, POL ₂ is at a high level, so that the potentials corresponding to n pixel values for one row are potential output terminals D _{1 to} D _n. Is output from. In this frame, since POL ₁ is at a high level, odd-numbered potential output terminals from the left output positive potentials, and even-numbered potential output terminals from the left output negative potentials.

When the switch 11 detects the rising edge of the first STB in the frame, the switch 11 sets the source line S ₁ to V _p when the STB goes high during the period of selecting each row of the first group one by one. It is connected to the wiring 5, when the STB is at the low level, thereby connecting the source lines _{S 1} to the potential output terminal _{D 1} (see FIG. 21 (a)). Accordingly, in this period, the source lines S _1, since the set precharge voltage V _p, setting an embodiment that the positive polarity potential corresponding to the pixel value is set is repeated.

When the switch 12 detects the rising edge of the first STB in the frame, the switch 12 continues to connect the source line _{Sn + 1} to the V _p setting wiring 5 within a period in which each row of the first group is selected one by one (see FIG. 22 (a)). Within this period, the source line S _{n + 1} is not used for the potential setting of the pixel electrode, the potential of the source line S _{n + 1} is maintained at V _p.

Each switch 14 even-numbered from the left, when the the STB is at a high level, to connect the corresponding source line V _n setting wires 6, when the STB is at the low level, the corresponding source lines Are connected to the even-numbered potential output terminals from the left (see FIG. 11A). Therefore, within the period for selecting line by line each row of the first group, in the even-numbered each source line from the left, since the set precharge voltage V _n, is set to a negative polarity potential corresponding to the pixel value The setting mode is repeated.

Each of the odd-numbered switches 15 from the left connects the corresponding source line to the _Vp setting wiring 5 when the STB is at a high level, and connects the corresponding source line to the _Vp setting wiring 5 when the STB is at a low level. These are respectively connected to odd-numbered potential output terminals from the left (see FIG. 12A). Therefore, within the period in which each row of the first group is selected one by one, the precharge potential V _p is set in each odd-numbered source line from the left, and then the positive potential corresponding to the pixel value is set. The setting mode is repeated.

Next, the operation of each of the switches 11, 12, 14, and 15 during a period in which each row of the second group is selected one by one will be described. During this period, since POL ₂ becomes low level, the potential corresponding to the n pixel values for one row are output from the potential output terminals D ₂ to D n + _1. Since POL ₁ remains at the high level, even-numbered potential output terminals D ₂ , D ₄ ,... From the left output negative potentials, and odd-numbered potential output terminals D ₃ , D from the left. ₅ ,... Output a positive potential.

When the switch 11 detects the rising edge of the STB corresponding to the first row of the second group, the switch 11 connects the source line S ₁ to the V _p setting wiring 5 during a period of selecting each row of the second group one by one. (See FIG. 21A). Within this period, the source line S ₁ is not used for the potential setting of the pixel electrode, the potential of the source line S ₁ is maintained at V _p.

When the switch 12 detects the rising edge of the STB corresponding to the first row of the second group, the source line S _{n + 1} when the STB becomes high level within a period of selecting each row of the second group one by _one. was connected to _{V p} setting wiring 5, when the STB is at the low level, thereby connecting the source line _{S n + 1} to the potential output terminal _{D n + 1.} Therefore, in this period, the setting mode in which the positive potential according to the pixel value is set after the precharge potential V _p is set in the source line _{Sn + 1} is repeated.

Even-numbered switches 14 from the left repeat the same operation as in the period in which each row in the first group is selected one by one in the period in which each row in the second group is selected one by one. Accordingly, even in a period for selecting line by line the row of the second group, the even-numbered each source line from the left, since the set precharge voltage V _n, is set to a negative polarity potential corresponding to the pixel value The setting mode is repeated.

The odd-numbered switches 15 from the left repeat the same operation as in the period in which each row in the first group is selected one by one in the period in which each row in the second group is selected one by one. Accordingly, even in a period in which each row of the second group is selected one by one, in each odd-numbered source line from the left, after the precharge potential V _p is set, the positive potential according to the pixel value is set. The setting mode is repeated.

  Thereafter, each of the switches 11, 12, 14, and 15 repeats the operation of the scanning period for the two groups within this frame. As a result, the polarities of the pixels in each row are as shown in FIG. That is, in the period in which each row of the odd-numbered group is selected one by one, from the left, the positive polarity, the negative polarity, the positive polarity, the negative polarity,... Are selected, and the period in which each row in the even-numbered group is selected one by one. Then, from the left, they are negative polarity, positive polarity, negative polarity, positive polarity, and so on.

FIG. 25 is an explanatory diagram illustrating an example of STB, POL ₁ , and POL _{2 in} a frame in which POL ₁ is at a low level in the second embodiment. When the first STB rises in this frame, the control unit 8 switches POL ₁ to the low level in conjunction with the rising edge of the STB, and thereafter maintains POL ₁ at the low level in this frame. To do. The control of POL ₂ by the control unit 8 is the same as the frame in which POL ₁ becomes high level.

Operation of each switch 11, 12, 14, 15 (see FIG. 1) during a period in which each row of the first group is selected one row after the rising edge of the first STB in the frame in which POL ₁ becomes low level Will be explained. During a period in which each row of the first group is selected one by one, POL ₂ is at a high level, so that the potentials corresponding to n pixel values for one row are potential output terminals D _{1 to} D _n. Is output from. In this frame, since POL ₁ is at a low level, odd-numbered potential output terminals from the left output negative potentials, and even-numbered potential output terminals from the left output positive potentials.

When the switch 11 detects the rising edge of the first STB in the frame, the switch 11 sets the source line S ₁ to V _n when the STB becomes high level within a period of selecting each row of the first group one by one. It is connected to the wiring 6, when the STB is at the low level, thereby connecting the source lines _{S 1} to the potential output terminal _{D 1} (see FIG. 21 (b)). Accordingly, in this period, the source lines S _1, since the set precharge voltage V _n, setting an embodiment that a negative polarity potential corresponding to the pixel value is set is repeated.

When the switch 12 detects the rising edge of the first STB in the frame, the switch 12 continues to connect the source line S _{n + 1} to the V _n setting wiring 6 within a period in which each row of the first group is selected one by one (see FIG. 22 (b)). Within this period, the source line S _{n + 1} is not used for the potential setting of the pixel electrode, the potential of the source line S _{n + 1} is maintained at V _n.

The even-numbered switches 14 from the left connect the corresponding source line to the V _p setting wiring 5 when the STB is at a high level, and switch the corresponding source line when the STB is at a low level. Are connected to the even-numbered potential output terminals from the left (see FIG. 11B). Accordingly, within the period in which each row of the first group is selected one by one, the precharge potential V _p is set in each even-numbered source line from the left, and then the positive potential corresponding to the pixel value is set. The setting mode is repeated.

Odd-numbered each switch 15 from the left, when the the STB is at a high level, to connect the corresponding source line V _n setting wires 6, when the STB is at the low level, the corresponding source lines These are respectively connected to odd-numbered potential output terminals from the left (see FIG. 12B). Therefore, within the period for selecting line by line each row of the first group, the odd-numbered each source line from the left, since the set precharge voltage V _n, is set to a negative polarity potential corresponding to the pixel value The setting mode is repeated.

Next, the operation of each of the switches 11, 12, 14, and 15 during a period in which each row of the second group is selected one by one will be described. During this period, since POL ₂ becomes low level, the potential corresponding to the n pixel values for one row are output from the potential output terminals D ₂ to D n + _1. Since POL ₁ remains at a low level, the even-numbered potential output terminals D ₂ , D ₄ ,... From the left output a positive potential, and the odd-numbered potential output terminals D ₃ , D ₅ ,. ... outputs a negative polarity potential.

When the switch 11 detects the rising edge of the STB corresponding to the first row of the second group, the switch 11 connects the source line S ₁ to the V _n setting wiring 6 during the period of selecting each row of the second group one by one. (See FIG. 21B). Within this period, the source line S ₁ is not used for the potential setting of the pixel electrode, the potential of the source line S ₁ is maintained at V _n.

When the switch 12 detects the rising edge of the STB corresponding to the first row of the second group, the source line S _{n + 1} when the STB becomes high level within a period of selecting each row of the second group one by _one. Is connected to the V _n setting wiring 6, and when the STB becomes a low level, the source line S _{n + 1} is connected to the potential output terminal D _{n + 1} . Therefore, in this period, the setting mode in which the negative potential according to the pixel value is set after the precharge potential V _n is set in the source line S _{n + 1} is repeated.

Even-numbered switches 14 from the left repeat the same operation as in the period in which each row in the first group is selected one by one in the period in which each row in the second group is selected one by one. Therefore, even in a period in which each row of the second group is selected one by one, in each even-numbered source line from the left, after the precharge potential V _p is set, the positive potential corresponding to the pixel value is set. The setting mode is repeated.

The odd-numbered switches 15 from the left repeat the same operation as in the period in which each row in the first group is selected one by one in the period in which each row in the second group is selected one by one. Accordingly, even in a period for selecting line by line the row of the second group, the odd-numbered each source line from the left, since the set precharge voltage V _n, is set to a negative polarity potential corresponding to the pixel value The setting mode is repeated.

  Thereafter, each of the switches 11, 12, 14, and 15 repeats the operation of the scanning period for the two groups within this frame. As a result, the polarities of the pixels in each row are as shown in FIG. That is, in the period in which each row of the odd-numbered group is selected one by one, from the left, the negative polarity, the positive polarity, the negative polarity, the positive polarity,..., And the period in which each row in the even-numbered group is selected one by one Then, from the left, they are positive, negative, positive, negative, and so on.

Since POL ₁ changes alternately every frame, the polarity of each pixel changes alternately between the state shown in FIG. 24 and the state shown in FIG. 26 for each frame.

In the second embodiment, whether POL ₁ POL ₁ is a frame to be high level regardless of whether the frame as a low level, each of the source lines, a corresponding potential output terminal is in a high impedance state Even if it is, it is maintained at a positive potential or a negative potential. Therefore, also in this embodiment, the potential of each source line does not become unstable.

  Also, as shown in FIGS. 24 and 26, the polarities of adjacent pixels are different from each other in the horizontal direction. As for the vertical direction, the rows belonging to the same group have the same polarity, but the polarity is inverted when the groups are switched. Therefore, although the same polarity may continue in the vertical direction, the number of pixels having the same polarity as the entire pixel can be reduced, and crosstalk can be prevented.

Also in the second embodiment, the potential of the individual source lines, kept in one frame in a positive polarity potential or negative potential, it does not vary across the V _COM. Therefore, power consumption can be suppressed. Further, when a potential corresponding to the pixel value is set for each source line, if the potential is a positive potential, the driving device 1 sets the potential of the source line to V _p and then according to the pixel value. Set the potential. Further, when the potential corresponding to the pixel value is negative potential, the driving device 1, the potential of the source line from the V _n, sets the potential corresponding to the pixel value. Therefore, power consumption can be suppressed.

  In the above description, the scanning period for one group in the first half of the scanning period for two groups is a scanning period for odd-numbered groups, and is a period during which all rows of the odd-numbered groups are selected. It can be said. Similarly, the scanning period for one group in the latter half of the scanning period for two groups is a scanning period for the even-numbered group, and it can be said that all the rows of the even-numbered group are selected. .

Further, as described in the first embodiment, the control unit 8 does not generate POL ₂ , but the driving device 1 (for example, the potential setting unit 2 in the driving device 1) generates POL ₂ , You may operate according to POL2.

  Note that the first embodiment corresponds to a case where only one row belongs to each group in the second embodiment. Therefore, it can be said that the first embodiment is a kind of the second embodiment.

[Embodiment 3]
FIG. 27 is an explanatory diagram illustrating an example of a liquid crystal display device according to a third embodiment of the present invention. Constituent elements similar to those in the first embodiment are denoted by the same reference numerals as those in FIGS. 1 and 2, and detailed description thereof is omitted. The liquid crystal display device according to the third embodiment includes a plurality of driving devices 1 _a and 1 _b , a liquid crystal display panel 20 _b , a control unit 8, and a power supply unit 9.

In this embodiment, the liquid crystal display panel 20 _b two drive apparatus 1 _a, 1 _b will be described as an example a case of driving, but there a configuration in which three or more drive devices for driving the liquid crystal display panel 20 _b May be. Hereinafter, a driving device disposed on the leftmost side as viewed from the viewing side referred to as a first driving device 1 _a. Also, mark the driving device disposed on the most right side viewed from the viewing side and a second drive unit 1 _b. Further, in the case where more than two drives are present, a first driving device 1 _a and a second drive device 1 _b other than the driving device (not shown in FIG. 27) referred to as a third driving device. FIG. 27 shows a case where two drive devices (first drive device 1 _a and second drive device 1 _b ) are provided, and the third drive device is not provided. As shown in FIG. 27, the driving devices 1 _a and 1 _b are arranged side by side. However, when the third drive device is provided, it is arranged between the first drive device _1a and the second drive device _1b . The number of third drive devices is not limited.

Each of the driving devices 1 _a and 1 _b includes a potential setting unit 2 (not shown in FIG. 27; see FIGS. 28 and 30), and a potential output terminal of the potential setting unit 2 has a switch (FIGS. 28 and 28 described later). Any one of the switches 11, 12, 14, 15, 91, and 92 shown in FIG. At this time, between adjacent driving devices, the rightmost potential output terminal of the left driving device viewed from the viewing side and the leftmost potential output terminal of the right driving device viewed from the viewing side are connected to a common source line. Is done. In Figure 27, the rightmost potential output terminal of the first driving apparatus 1 _a, and the leftmost potential output terminal of the second driving device 1 _b, via a switch (not shown in FIG. 27.), A source line The case where it is connected to _{Sn + 1} is illustrated.

The control unit 8 outputs the control signals POL ₁ , POL ₂ , SCLK, STB, STV, etc., as in the first embodiment. However, the control unit 8 outputs a control signal to each of the driving devices 1 _a and 1 _b . When the third driving device is provided, a control signal is also output to the third driving device. The power supply unit 9 supplies a voltage in the same manner as in the first embodiment. However, the power supply unit 9 supplies a voltage to each of the driving devices 1 _a and 1 _b . In the case where a third driving device is provided, a voltage is also supplied to the third driving device.

The liquid crystal display panel 20 _b includes a plurality of pixel electrodes 21 arranged in a matrix, for sandwiching a liquid crystal (not shown) between the common electrode (not shown in FIG. 27). In the present embodiment, in each row of the liquid crystal display panel 20 _b, each pixel R, G, will be described as an example in which the repeating arranged in the order of B.

The liquid crystal display panel 20 _b, is provided with a plurality of source lines, between adjacent source lines, and a pixel electrode for one column. Therefore, in the pixel electrode group arranged in a matrix, the number of pixel electrode columns is one less than the number of source lines. In other words, the liquid crystal display panel 20 _b includes a source line on the left side of each column of pixel electrodes, and also includes a source line on the right side of the rightmost pixel column. This point is the same as in the first embodiment.

However, in the third embodiment, the number of pixel electrode columns is larger than the number of potential output terminals of the potential setting unit 2 (not shown in FIG. 27) in one driving device. Here, a case where the number of columns of pixel electrodes is 2n and the number of source lines is 2n + 1 is taken as an example. S _{1 to} S _{2n + 1} from the source line on the left side when viewed from the viewing side. As described above, the (n + 1) th source line S _{n + 1} from the left is connected to the potential output terminals of both the driving devices 1 _a and 1 _b . In FIG. 27, the source line S _{n + 1} is shown thicker than the other source lines for the sake of convenience, but each of the source lines S _{1 to} S _{2n + 1} has the same thickness.

FIG. 28 is an explanatory diagram showing _a configuration example of the first drive device _1a . The same components as those of the driving device 1 in the first embodiment are denoted by the same reference numerals as those in FIG. The first driving device 1 _a includes a potential setting unit 2, a V _p setting unit 3, a V _n setting unit 4, a V _p setting wiring 5, and a V _n setting wiring 6.

The potential setting unit 2 includes n + 1 potential output terminals D _{1 to} D _{n + 1} . The operation in which the potential setting unit 2 captures image data according to the control signals SLCK and STB from the control unit 8 and determines the output potentials of the potential output terminals D _{1 to} D _{n + 1} according to POL ₁ and POL ₂ is the same as in the first embodiment. It is. However, in this embodiment, one row of pixels in the liquid crystal display panel 20 _b is when repeatedly arranged R, G, in the order of B, n is assumed to be a multiple of 6. Therefore, n + 1 is a value obtained by adding 1 to a multiple of 6, and is an odd number. The reason why n is a multiple of 6 is as follows. In order to set R, G, and B as a set, n needs to be a multiple of 3. Also, different polarities of the n-th pixel from the leftmost pixel and the left, the polarity of the left n + 1 th pixel is driven by the second drive unit 2 _b is the same as the polarity of the leftmost pixel In order to be n, n must be an even number. Therefore, n needs to be a multiple of 6 in order to satisfy these requirements.

Each switch provided in association with the _nth potential output terminals D _{1 to} D _n as viewed from the viewing side is the same as in the first embodiment. That is, for the potential output terminals _{D 1,} switch 11 is provided. Further, switches 14 are provided at even-numbered potential output terminals D ₂ , D ₄ ,... From the left. Further, switches 15 are provided at odd-numbered potential output terminals D ₃ , D ₅ ,... From the left. However, D _{n + 1} is excluded.

As a switch corresponding to the (n + 1) th potential output terminal D _{n + 1} from the left, a third end switch 91 (hereinafter simply referred to as a switch 91) is provided. This is different from the driving apparatus 1 (see FIG. 1) in which the switch 12 is provided at the potential output terminal Dn _{+ 1} .

The (n + 1) th source lines S _{1 to} S _{n + 1} from the left are connected to potential output terminals D _{1 to} D _{n + 1} via switches (any one of the switches 11, 14, 15, 91). Here, the source line _{Sn + 1} includes a first branch part 41 and a second branch part 42. Hereinafter, the first branch part 41 may be simply referred to as “branch part 41”, and the second branch part 42 may be simply referred to as “branch part 42”.

Here, the source line having the first branch portion 41 and the second branch portion 42 will be described in the case where u drive devices are present. Let u be the number of drive devices and v be an integer between 1 and less than u. At this time, the v · n + 1-th source line S _{v · n + 1} from the left has the first branch portion 41 and the second branch portion 42, and the other source lines have no branch portion. Then, the source line S _{v · n + 1,} from the left in the v-th of the driving device from the left and the (n + 1) th potential output terminal D _{n + 1,} from the left in the left-v + 1 th drive first and potential output terminals D ₁ Are connected to the two potential output terminals. Specifically, the first branch portion 41 of the source line S _{v · n + 1} is connected to the potential output terminal D _{n + 1} in the v-th driving device from the left via the switch 91 (see FIGS. 28 and 32). . Further, the second branch section 42 of the source line S _{v · n + 1} is connected to the potential output terminal D ₁ of the v + 1-th driving device from the left via the switch 92 (see FIGS. 30 and 32).

In the example shown in FIG. 27, since the number u of driving devices is “2”, the value that v can take is only “1”. Therefore, the source line having the branch portion is S _{n + 1} among S _{1 to} S _{2n + 1} . The first branch portion 41 of the source line _{S n + 1} is the potential output terminal _{D n + 1} in the first driving device _{1 a} from the left, is connected via a switch 91 (see FIG. 28). The second branch portion 42 of the source line _{S n + 1} is the potential output terminals _{D 1} at the second drive unit _{1 b} from the left, is connected via a switch 92 (see FIG. 30).

As described above, one branch section 41 is connected to the switch 91 arranged n + 1 from the left. Connecting the source lines S ₁ to S _n, the corresponding switch is similar to the first embodiment, the description thereof is omitted.

  The operations of the switches 11, 14, and 15 are the same as the operations of the switches 11, 14, and 15 in the first embodiment, and a description thereof is omitted.

FIG. 29 is an explanatory diagram illustrating a source line connection destination switching operation by the switch 91 corresponding to the potential output terminal Dn _{+ 1} . FIG. 29A shows a case where POL ₁ is at a high level, and FIG. 29B shows a case where POL ₁ is at a low level. When the switch 91 detects the rising edge of the STB during the period when the STV is at the high level, thereafter, the switch 91 repeats the operation defined for each switch for each period of two STB cycles in the frame.

With reference to FIG. 29A, the operation of the switch 91 in a frame in which POL ₁ becomes high level will be described. When the switch 91 detects the first rising edge in the period corresponding to the STB2 period, the switch 91 connects the branch portion 41 of the source line Sn _{+ 1} to the potential output terminal Dn _{+ 1} for the period corresponding to the STB1 period from the rising edge. As a result, the branch part 41 of the source line _{Sn + 1} is in a high impedance state. However, the switch 91 does not connect the branch portion 41 of the source line S _{n + 1 to} any _one of the potential output terminal D _{n + 1} , the V _p setting wiring 5 and the V _n setting wiring 6 (that is, an open state) The high impedance state. When This lack the demultiplexer 41 is connected to the potential output terminal D _{n + 1,} in the period of the STB1 period, the potential output terminals D _{n + 1} may not be a high-impedance state.

Next, when detecting the second rising edge of STB in the period corresponding to two cycles of STB, the switch 91 causes the branch part 41 of the source line _{Sn + 1} to the V _p setting wiring 5 while the STB is at the high level. Connect. Next, when the switch 91 detects the falling edge of STB, the switch 91 connects the branch part 41 of the source line S _{n + 1} to the potential output terminal D _{n + 1} while the STB is at the low level.

With reference to FIG. 29B, the operation of the switch 91 in a frame in which POL ₁ is at a low level will be described. When the switch 91 detects the first rising edge in the period corresponding to the STB2 period, the switch 91 connects the branch portion 41 of the source line Sn _{+ 1} to the potential output terminal Dn _{+ 1} for the period corresponding to the STB1 period from the rising edge. As a result, the branch part 41 of the source line _{Sn + 1} is in a high impedance state. However, as described above, the switch 91 does not connect the branch portion 41 of the source line S _{n + 1} to any of the potential output terminal D _{n + 1} , the V _p setting wiring 5, and the V _n setting wiring 6. It may be in an impedance state. When This lack the demultiplexer 41 is connected to the potential output terminal D _{n + 1,} in the period of the STB1 period, the potential output terminals D _{n + 1} may not be a high-impedance state.

Then, upon detecting the second rising edge of STB in the period STB2 period, the switch 91 while the STB is at the high level, the branch portion 41 of the source line _{S n + 1} to _{V n} setting wiring 6 Connect. Next, when the switch 91 detects the falling edge of STB, the switch 91 connects the branch part 41 of the source line S _{n + 1} to the potential output terminal D _{n + 1} while the STB is at the low level.

  Thereafter, within this frame, the switch 91 repeats the operation for two STB cycles.

FIG. 30 is an explanatory diagram showing a configuration example of the second drive device _1b . The same components as those of the driving device 1 in the first embodiment are denoted by the same reference numerals as those in FIG. The second driving device 1 _b includes a potential setting unit 2, a V _p setting unit 3, a V _n setting unit 4, a V _p setting wiring 5, and a V _n setting wiring 6.

The potential setting unit 2 includes n + 1 potential output terminals D _{1 to} D _{n + 1} . As already described, n + 1 is a value obtained by adding 1 to a multiple of 6 and is an odd number.

Further, the potential setting section 2 of the second drive unit 1 _b, each switch provided in association with the potential output terminals D ₂ to D n + ₁ from the second from the left to the n + 1 th, as in the first embodiment It is. That is, the switches 14 are provided at the even-numbered potential output terminals D ₂ , D ₄ ,... From the left of the potential setting unit 2. Further, switches 15 are provided at odd-numbered potential output terminals D ₃ , D ₅ ,... From the left. However, _{D 1} is excluded. Further, the n + 1-numbered potential output terminals _{D n + 1} from the left, switch 12 is provided.

The potential setting section 2 of the second drive unit 1 _b, as a switch corresponding to the No. 1 potential output terminals D ₁ of the left, the fourth end switch 92 (hereinafter. Referred to as simply switch 92) is provided. In this respect, it differs from the driving device 1 (see FIG. 1) the switch 11 is provided on the potential output terminals D _1.

In the source line _{S n + 1} of the liquid crystal display panel 20 _b, the branch portion 42 of which it is not connected the first drive device _{1 a} of the switch 91 is connected to the switch 92. As a result, the potential output terminals D _{n + 1} of the first driving apparatus 1 _a, the potential output terminals D ₁ of the second drive unit 1 _b, so that the common source line S _{n + 1} is connected.

The liquid crystal display panel 20 _b each source from the left of the (n + 2) -th and subsequent in-line _S n + _{2 to S 2n + 1} is connected to the switch as follows. Among these source lines, the even-numbered source lines S _{n + 2} , S _{n + 4} ,... From the left in the liquid crystal display panel 20 _b are connected to the switch 14. Among these source lines, odd-numbered source lines S _{n + 3} , S _{n + 5} ,... From the left in the liquid crystal display panel 20 _b are connected to the switch 15. The rightmost source line S _{2n + 1} is connected to the switch 12.

  The operations of the switches 12, 14, and 15 are the same as the operations of the switches 12, 14, and 15 in the first embodiment, and a description thereof is omitted.

Figure 31 is an explanatory diagram showing a connection destination switching operation of the source lines by the switch 92 corresponding to the potential output terminals D ₁ of the second drive unit 1 _b. FIG. 31A shows a case where POL ₁ is at a high level, and FIG. 31B shows a case where POL ₁ is at a low level. When the switch 92 detects the rising edge of the STB during the period when the STV is at the high level, thereafter, the switch 92 repeats the operation determined for each switch for each period of two STB periods in the frame.

With reference to FIG. 31A, the operation of the switch 92 in a frame in which POL ₁ is at a high level will be described. When the switch 92 detects the first rising edge in the period corresponding to two STB cycles, the switch 92 connects the branch part 42 of the source line _{Sn + 1} to the V _p setting wiring 5 while the STB is at the high level. . Then, upon detecting the falling edge of STB, while the STB is at the low level, the switch 92 connects the branch portion 42 of the source line _{S n + 1} to the potential output terminal _{D 1.}

Next, when the second rising edge of STB in the period corresponding to two STB periods is detected, the switch 92 continues to connect the branch section 42 of the source line _{Sn + 1} to the potential output terminal D _{1 for} the period corresponding to the STB1 period from the rising edge. Connect to. As a result, the branch part 42 of the source line _{Sn + 1} is in a high impedance state. However, the switch 92 does not connect the branch portion 42 of the source line S _{n + 1 to} any _one of the potential output terminal D ₁ , the V _p setting wiring 5, and the V _n setting wiring 6, thereby setting the high impedance state. Good. When the thus does not connect the branching unit 42 to the potential output terminals D _1, in the period of the STB1 period, the potential output terminals D ₁ may not be a high-impedance state.

With reference to FIG. 31B, the operation of the switch 92 in a frame in which POL ₁ is at a low level will be described. When the switch 92 detects the first rising edge in the period corresponding to two STB cycles, the switch 92 connects the branch portion 42 of the source line S _{n + 1} to the V _n setting wiring 6 while the STB is at the high level. . Then, upon detecting the falling edge of STB, while the STB is at the low level, the switch 92 connects the branch portion 42 of the source line _{S n + 1} to the potential output terminal _{D 1.}

Next, when the second rising edge of STB in the period corresponding to two STB periods is detected, the switch 92 continues to connect the branch section 42 of the source line _{Sn + 1} to the potential output terminal D _{1 for} the period corresponding to the STB1 period from the rising edge. Connect to. As a result, the branch part 42 of the source line _{Sn + 1} is in a high impedance state. However, the switch 92 does not connect the branch portion 42 of the source line S _{n + 1 to} any _one of the potential output terminal D ₁ , the V _p setting wiring 5, and the V _n setting wiring 6, thereby setting the high impedance state. Good. When the thus does not connect the branching unit 42 to the potential output terminals D _1, in the period of the STB1 period, the potential output terminals D ₁ may not be a high-impedance state.

  Thereafter, within this frame, the switch 92 repeats the operation for this STB2 period.

Next, the operation in the third embodiment will be described. Here, it is assumed that R, G, and B pixels are repeatedly arranged in each row of the liquid crystal display panel 20b. In this case, as already described, n is a multiple of 6, and as a result, n + 1 is an odd number. Changes in the control signals STB, POL ₁ and POL ₂ output from the control unit 8 are the same as those in the first embodiment.

First, the operation of the frame in which POL ₁ becomes high level will be described. Control unit 8, when the first launch STB in the frame POL ₁ is at high level, in accordance with the rising edge of the STB, switch the POL ₁ to high level, since the high and POL ₁ in this frame Keep level. Further, the control unit 8 switches POL ₂ to high level during the period when STB first becomes high level in the frame, and thereafter switches the level of POL ₂ alternately for each STB cycle.

When the rising edge of the first STB in the frame in which POL ₁ becomes high level is detected, each switch operates as follows during the period in which STB is high level.

The switch 11 of the first driving device 1 _a connects the source line S ₁ to the V _p setting wiring 5. As a result, the potential of the source line _{S 1} becomes _{V p.}

Each switch 14 in each driving device 1 _a , 1 _b connects the even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left to the V _n setting wiring 6. As a result, the potential of these even-numbered each source line becomes V _n.

In addition, each switch 15 in each driving device 1 _a , 1 _b has odd-numbered source lines S ₃ , S ₅ ,..., S _n−1 , S _{n + 3 ,.} , _Vp setting wiring 5 is connected. As a result, the potential of each odd-numbered source line becomes V _p .

Further, (see FIG. 28) switches 91 to connect the branch portions 41 of the source line _{S n + 1} to the potential output terminal _{D n + 1,} (see FIG. 29) switches 92, the branch portion 42 of the source line _{S n + 1 V p} set Connect to the wiring 5 for use. Accordingly, the output of the potential output terminal D _{n + 1} of the first driving device 1 _a is in a high impedance state, but the potential of the source line S _{n + 1} is V _p .

The switch 12 of the second drive unit _{1 b} may be connected to the source line _{S 2n + 1} to the wiring 5 for _{V p} configuration. Therefore, the potential output terminal _{D n + 1} is in a high impedance state, the potential of the source line _{S 2n + 1} becomes _{V p.}

Subsequently, when the falling edge of STB is detected, each switch operates as follows during a period in which STB is at a low level. At this time, the potential setting unit 2 of each of the driving devices 1 _a and 1 _b outputs a potential corresponding to the pixel value from the potential output terminals D _{1 to} D _n and sets the output of the potential output terminal D _{n + 1} to high. Set to impedance state. The output potential from the odd-numbered potential output terminal from the left is a positive potential, and the output potential from the even-numbered potential output terminal from the left is a negative potential.

The first driving device _{1 a} of the switch 11 to connect the source lines _{S 1} to the potential output terminal _{D 1.} As a result, the potential of the source line S ₁ is changed to the positive polarity potential corresponding to the pixel value. That is, the source line S ₁ from being set to the precharge voltage V _p, will be set to a positive polarity potential corresponding to the pixel value.

Each switch 14 of the first driving device _{1 a} is even-numbered from the left each of the source lines _{S 2, S} 4, the potential output terminals of ... _{D 2, D} 4, is connected to .... Each switch 14 of the second driving device _1b also connects the even-numbered source lines S _{n + 2} , S _{n + 4} ,... From the left to the potential output terminals D ₂ , D ₄ ,. As a result, the potentials of even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left become negative potentials corresponding to the pixel values. That is, the even-numbered each source line from the left, consisting of is set to the precharge voltage V _n, to be set to a negative polarity potential corresponding to the pixel value.

Each switch 15 of the first drive device _{1 a} is odd-numbered source lines _S 3 from the left, _{respectively,} S 5, _{..., S n-1} the potential output terminals _{D 3, D} 5, connected to ... Let Each switch 15 of the second driving device _1b also connects the odd-numbered source lines S _{n + 3} , S _{n + 5} ,..., S _2n−1 from the left to the potential output terminals D ₃ , D ₅ ,. Let As a result, the odd-numbered source lines _S 3 from the _{left, S 5, ···, S n} -1, S n + 3, S n + 5, ···, the potential of _{S 2n-1} is positive polarity corresponding to the pixel value It becomes a potential. That is, these source lines consists is set to the precharge voltage V _p, to be set to a positive polarity potential corresponding to the pixel value.

The switch 91 (see FIG. 28) keeps the branch portion 41 of the source line _{Sn + 1} connected to the potential output terminal Dn _{+ 1} , and the switch 92 (see FIG. 29) connects the branch portion 42 of the source line _{Sn + 1.} It is connected to the potential output terminal D _1. Accordingly, the output of the potential output terminal D _{n + 1} of the first driving device 1 _a is in a high impedance state, but the potential of the source line _{Sn + 1} is changed to the pixel value by the potential output terminal D _{1 of} the second driving device 1 _b. Is set to a positive potential corresponding to. That is, the source line S _{n + 1} from being set to the precharge voltage V _p, will be set to a positive polarity potential corresponding to the pixel value.

The switch 12 of the second driving device _{1 b} is remains to connect the source lines _{S 2n + 1} to _{V p} setting wiring 5. Therefore, the potential of the source line S _{2n + 1} remains V _p . At this time, the output of the potential output terminal D _{2n + 1} is in a high impedance state, and the source line S _{2n + 1} is not used for pixel setting of the pixel electrode. However, as described above, the potential of the source line S _{2n + 1} becomes V _p and does not become unstable.

  As a result, the 2n pixel electrodes in the first row are each set to a potential corresponding to the pixel value by the left source line when viewed from the viewing side, and the polarity of each pixel is positive, negative, Positive polarity, negative polarity, and so on.

  Next, when the rising edge of STB is detected, each switch operates as follows during a period in which STB is at a high level.

The switch 11 of the first driving device 1 _a connects the source line S ₁ to the V _p setting wiring 5. As a result, the potential of the source line _{S 1} becomes _{V p.}

Each switch 14 in each driving device 1 _a , 1 _b connects the even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left to the V _n setting wiring 6. As a result, the potential of these even-numbered each source line becomes V _n.

In addition, each switch 15 in each driving device 1 _a , 1 _b has odd-numbered source lines S ₃ , S ₅ ,..., S _n−1 , S _{n + 3 ,.} , _Vp setting wiring 5 is connected. As a result, the potential of each odd-numbered source line becomes V _p .

The switch 91 (see FIG. 28) connects the branch portion 41 of the source line S _{n + 1} to the V _p setting wiring 5, and the switch 92 (see FIG. 29) outputs the branch portion 42 of the source line S _{n + 1} to the potential output. It is connected to the end _{D 1.} Thus, the output of the potential output terminals D ₁ of the second driving device 1 _b is a high impedance state, the potential of the source line S _{n + 1} becomes V _p.

The switch 12 of the second drive unit _{1 b} may be connected to the source line _{S 2n + 1} to the wiring 5 for _{V p} configuration. Therefore, the potential output terminal _{D n + 1} is in a high impedance state, the potential of the source line _{S 2n + 1} becomes _{V p.}

Subsequently, when the falling edge of STB is detected, each switch operates as follows during a period in which STB is at a low level. At this time, the potential setting unit 2 of each of the driving devices 1 _a and 1 _b outputs a potential corresponding to the pixel value from the potential output terminals D _{2 to} D _{n + 1} , and sets the output of the potential output terminal D ₁ to high. Set to impedance state. The output potential from the odd-numbered potential output terminal from the left is a positive potential, and the output potential from the even-numbered potential output terminal from the left is a negative potential.

The switch 11 of the first driving device 1 _a keeps the source line S ₁ connected to the V _p setting wiring 5. Thus, the potential of the source line _{S 1} remains of _{V p.} At this time, the output of the potential output terminals D ₁ is a high-impedance state, the source line S ₁ is not used in the pixel set of the pixel electrode. However, as described above, the potential of the source line S ₁ is V _p becomes does not become unstable.

Each switch 14 of the first driving device _{1 a} is even-numbered from the left each of the source lines _{S 2, S} 4, the potential output terminals of ... _{D 2, D} 4, is connected to .... Each switch 14 of the second driving device _1b also connects the even-numbered source lines S _{n + 2} , S _{n + 4} ,... From the left to the potential output terminals D ₂ , D ₄ ,. As a result, the potentials of even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left become negative potentials corresponding to the pixel values. That is, the even-numbered each source line from the left, consisting of is set to the precharge voltage V _n, to be set to a negative polarity potential corresponding to the pixel value.

Each switch 15 of the first drive device _{1 a} is odd-numbered source lines _S 3 from the left, _{respectively,} S 5, _{..., S n-1} the potential output terminals _{D 3, D} 5, connected to ... Let Each switch 15 of the second driving device _1b also connects the odd-numbered source lines S _{n + 3} , S _{n + 5} ,..., S _2n−1 from the left to the potential output terminals D ₃ , D ₅ ,. Let As a result, the odd-numbered source lines _S 3 from the _{left, S 5, ···, S n} -1, S n + 3, S n + 5, ···, the potential of _{S 2n-1} is positive polarity corresponding to the pixel value It becomes a potential. That is, these source lines consists is set to the precharge voltage V _p, to be set to a positive polarity potential corresponding to the pixel value.

The switch 91 (see FIG. 28) connects the branch portion 41 of the source line _{Sn + 1} to the potential output terminal Dn _{+ 1} , and the switch 92 (see FIG. 29) connects the branch portion 42 of the source line _{Sn + 1} to the potential output terminal. and while keeping connected to D _1. Thus, the output of the potential output terminals D ₁ of the second driving device 1 _b is a high impedance state, the potential of the source line S _{n + 1} is the potential output terminals D _{n + 1} of the first drive device 1 _a, pixel values Is set to a positive potential corresponding to. That is, the source line S _{n + 1} from being set to the precharge voltage V _p, will be set to a positive polarity potential corresponding to the pixel value.

The switch 12 of the second drive unit _{1 b} may be connected to the source line _{S 2n + 1} to the potential output terminal _{D n + 1.} Therefore, the potential of the source line S _{2n + 1} is set to a positive potential according to the pixel value. That is, the source line S _{2n + 1} is set to the positive potential according to the pixel value after being set to the precharge potential V _p .

  As a result, the 2n pixel electrodes in the second row are each set to a potential corresponding to the pixel value by the source line on the right side when viewed from the viewing side, and the polarity of each pixel is negative, positive, Negative polarity, positive polarity,...

In the frame of POL ₁ is at high level, since, repeated STB2 period of operation of the.

Next, the operation of a frame in which POL ₁ is at a low level will be described. Control unit 8, when the first launch STB in the frame POL ₁ is at low level, in accordance with the rising edge of the STB, switch the POL ₁ to low level, since the low and POL ₁ in this frame Keep level. The control of POL ₂ is the same as the frame in which POL ₁ becomes high level.

When the rising edge of the first STB in the frame in which POL ₁ is at the low level is detected, each switch operates as follows during the period when the STB is at the high level.

The switch 11 of the first driving device 1 _a connects the source line S ₁ to the V _n setting wiring 6. As a result, the potential of the source line _{S 1} becomes _{V n.}

Each switch 14 in each driving device 1 _a , 1 _b connects the even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left to the V _p setting wiring 5. As a result, the potential of these even-numbered each source line becomes V _p.

In addition, each switch 15 in each driving device 1 _a , 1 _b has odd-numbered source lines S ₃ , S ₅ ,..., S _n−1 , S _{n + 3 ,.} , it is connected for _{V n} set wire 6. As a result, the potential of these odd-numbered each source line becomes V _n.

Further, (see FIG. 28) switches 91 to connect the branch portions 41 of the source line _{S n + 1} to the potential output terminal _{D n + 1,} (see FIG. 29) switches 92, _{V n} setting the branch portion 42 of the source line _{S n + 1} Connect to the wiring 6 for use. Accordingly, the output of the potential output terminal D _{n + 1} of the first driving device 1 _a is in a high impedance state, but the potential of the source line S _{n + 1} is V _n .

The switch 12 of the second drive unit _{1 b} may be connected to the source line _{S 2n + 1} to _{V n} setting wire 6. Therefore, the potential output terminal _{D n + 1} is in a high impedance state, the potential of the source line _{S 2n + 1} becomes _{V n.}

Subsequently, when the falling edge of STB is detected, each switch operates as follows during a period in which STB is at a low level. At this time, the potential setting unit 2 of each of the driving devices 1 _a and 1 _b outputs a potential corresponding to the pixel value from the potential output terminals D _{1 to} D _n and sets the output of the potential output terminal D _{n + 1} to high. Set to impedance state. The output potential from the odd-numbered potential output terminal from the left is a negative potential, and the output potential from the even-numbered potential output terminal from the left is a positive potential.

The first driving device _{1 a} of the switch 11 to connect the source lines _{S 1} to the potential output terminal _{D 1.} As a result, the potential of the source line S ₁ is changed to the negative polarity potential corresponding to the pixel value. That is, the source line S ₁ from being set to the precharge voltage V _n, will be set to a negative polarity potential corresponding to the pixel value.

Each switch 14 of the first driving device _{1 a} is even-numbered from the left each of the source lines _{S 2, S} 4, the potential output terminals of ... _{D 2, D} 4, is connected to .... Each switch 14 of the second driving device _1b also connects the even-numbered source lines S _{n + 2} , S _{n + 4} ,... From the left to the potential output terminals D ₂ , D ₄ ,. As a result, the potentials of the even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left become positive potentials corresponding to the pixel values. That is, the even-numbered each source line from the left, consisting of is set to the precharge voltage V _p, to be set to a positive polarity potential corresponding to the pixel value.

Each switch 15 of the first drive device _{1 a} is odd-numbered source lines _S 3 from the left, _{respectively,} S 5, _{..., S n-1} the potential output terminals _{D 3, D} 5, connected to ... Let Each switch 15 of the second driving device _1b also connects the odd-numbered source lines S _{n + 3} , S _{n + 5} ,..., S _2n−1 from the left to the potential output terminals D ₃ , D ₅ ,. Let As a result, the odd-numbered source lines _S 3 from the _{left, S 5, ···, S n} -1, S n + 3, S n + 5, ···, the potential of _{S 2n-1,} a negative polarity corresponding to the pixel value It becomes a potential. That is, these source lines consists is set to the precharge voltage V _n, to be set to a negative polarity potential corresponding to the pixel value.

The switch 91 (see FIG. 28) keeps the branch portion 41 of the source line _{Sn + 1} connected to the potential output terminal Dn _{+ 1} , and the switch 92 (see FIG. 29) connects the branch portion 42 of the source line _{Sn + 1.} It is connected to the potential output terminal D _1. Accordingly, the output of the potential output terminal D _{n + 1} of the first driving device 1 _a is in a high impedance state, but the potential of the source line _{Sn + 1} is changed to the pixel value by the potential output terminal D _{1 of} the second driving device 1 _b. Is set to a negative potential corresponding to the above. That is, the source line S _{n + 1} is set to the negative potential according to the pixel value after being set to the precharge potential V _n .

The switch 12 of the second driving device _{1 b} is remains to connect the source lines _{S 2n + 1} to _{V n} setting wire 6. Therefore, the potential of the source line S _{2n + 1} remains V _n . At this time, the output of the potential output terminal D _{2n + 1} is in a high impedance state, and the source line S _{2n + 1} is not used for pixel setting of the pixel electrode. However, as described above, the potential of the source line S _{2n + 1} becomes V _n and does not become unstable.

  As a result, the 2n pixel electrodes in the first row are each set to a potential corresponding to the pixel value by the left source line when viewed from the viewing side, and the polarity of each pixel is negative, positive, Negative polarity, positive polarity,...

  Next, when the rising edge of STB is detected, each switch operates as follows during a period in which STB is at a high level.

The switch 11 of the first driving device 1 _a connects the source line S ₁ to the V _n setting wiring 6. As a result, the potential of the source line _{S 1} becomes _{V n.}

Each switch 14 in each driving device 1 _a , 1 _b connects the even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left to the V _p setting wiring 5. As a result, the potential of these even-numbered each source line becomes V _p.

In addition, each switch 15 in each driving device 1 _a , 1 _b has odd-numbered source lines S ₃ , S ₅ ,..., S _n−1 , S _{n + 3 ,.} , it is connected for _{V n} set wire 6. As a result, the potential of these odd-numbered each source line becomes V _n.

The switch 91 (see FIG. 28) connects the branch portion 41 of the source line S _{n + 1} to the V _n setting wiring 6, and the switch 92 (see FIG. 29) outputs the branch portion 42 of the source line S _{n + 1} to the potential output. It is connected to the end _{D 1.} Thus, the output of the potential output terminals D ₁ of the second driving device 1 _b is a high impedance state, the potential of the source line S _{n + 1} becomes V _n.

The switch 12 of the second drive unit _{1 b} may be connected to the source line _{S 2n + 1} to _{V n} setting wire 6. Therefore, the potential output terminal _{D n + 1} is in a high impedance state, the potential of the source line _{S 2n + 1} becomes _{V n.}

Subsequently, when the falling edge of STB is detected, each switch operates as follows during a period in which STB is at a low level. At this time, the potential setting unit 2 of each of the driving devices 1 _a and 1 _b outputs a potential corresponding to the pixel value from the potential output terminals D _{2 to} D _{n + 1} , and sets the output of the potential output terminal D ₁ to high. Set to impedance state. The output potential from the odd-numbered potential output terminal from the left is a negative potential, and the output potential from the even-numbered potential output terminal from the left is a positive potential.

The switch 11 of the first driving device 1 _a keeps the source line S ₁ connected to the V _n setting wiring 6. Thus, the potential of the source line _{S 1} remains of _{V n.} At this time, the output of the potential output terminals D ₁ is a high-impedance state, the source line S ₁ is not used in the pixel set of the pixel electrode. However, as described above, the potential of the source line S ₁ is next to V _n, it does not become unstable.

Each switch 14 of the first driving device _{1 a} is even-numbered from the left each of the source lines _{S 2, S} 4, the potential output terminals of ... _{D 2, D} 4, is connected to .... Each switch 14 of the second driving device _1b also connects the even-numbered source lines S _{n + 2} , S _{n + 4} ,... From the left to the potential output terminals D ₂ , D ₄ ,. As a result, the potentials of the even-numbered source lines S ₂ , S ₄ ,..., S _2n from the left become positive potentials corresponding to the pixel values. That is, the even-numbered each source line from the left, consisting of is set to the precharge voltage V _p, to be set to a positive polarity potential corresponding to the pixel value.

Each switch 15 of the first drive device _{1 a} is odd-numbered source lines _S 3 from the left, _{respectively,} S 5, _{..., S n-1} the potential output terminals _{D 3, D} 5, connected to ... Let Each switch 15 of the second driving device _1b also connects the odd-numbered source lines S _{n + 3} , S _{n + 5} ,..., S _2n−1 from the left to the potential output terminals D ₃ , D ₅ ,. Let As a result, the odd-numbered source lines ₃ from the _{left, S 5, ···, S n} -1, S n + 3, S n + 5, ···, the potential of _{S 2n-1,} a negative polarity potential corresponding to the pixel value It becomes. That is, these source lines consists is set to the precharge voltage V _n, to be set to a negative polarity potential corresponding to the pixel value.

The switch 91 (see FIG. 28) connects the branch portion 41 of the source line _{Sn + 1} to the potential output terminal Dn _{+ 1} , and the switch 92 (see FIG. 29) connects the branch portion 42 of the source line _{Sn + 1} to the potential output terminal. and while keeping connected to D _1. Thus, the output of the potential output terminals D ₁ of the second driving device 1 _b is a high impedance state, the potential of the source line S _{n + 1} is the potential output terminals D _{n + 1} of the first drive device 1 _a, pixel values Is set to a negative potential corresponding to the above. That is, the source line S _{n + 1} is set to the negative potential according to the pixel value after being set to the precharge potential V _n .

The switch 12 of the second drive unit _{1 b} may be connected to the source line _{S 2n + 1} to the potential output terminal _{D n + 1.} Therefore, the potential of the source line S _{2n + 1} is set to a negative potential according to the pixel value. That is, the source line S _{2n + 1} is set to the negative potential according to the pixel value after being set to the precharge potential V _n .

  As a result, the 2n pixel electrodes in the second row are each set to a potential corresponding to the pixel value by the source line on the right side when viewed from the viewing side, and the polarity of each pixel is positive, negative, Positive polarity, negative polarity, and so on.

In the frame in which POL ₁ is at a low level, the above operation for the STB2 period is repeated.

In this embodiment, each source line, when not connected to the potential output terminal for outputting a potential corresponding to the pixel value is connected to V _p setting wiring 5 or V _n setting wire 6. Therefore, the potential of the source line does not become unstable. Also in the source line _{S 1, S 2n +} 1 is not used in the potential setting of the pixel electrode selection period, the source lines _{S 1, S 2n +} 1 is coupled to _{V p} setting wiring 5 or _{V n} setting wire 6. Therefore, the potential does not become unstable with respect to the source lines S ₁ and S _{2n + 1} .

As for the source line _{Sn + 1} , one of the two branch portions 41 and 42 may be connected to the high impedance state potential output terminal, but the other branch portion is used for V _p setting. line 5, V _n setting wire 6, or is connected to the potential output terminal for outputting a potential corresponding to the pixel value. Therefore, the potential does not become unstable with respect to _{Sn + 1} .

  Moreover, since the polarities of adjacent pixels are different from each other, crosstalk can be prevented.

The potential of each source line is maintained at the positive polarity voltage or a negative polarity voltage in one frame, it does not change across the V _COM. Therefore, power consumption can be suppressed. Further, when a potential corresponding to a pixel value is set for each source line, a potential corresponding to the pixel value is set after setting a precharge potential. Therefore, power consumption can be further suppressed.

Moreover, although the case where the control unit 8 generates POL ₂ has been described in the above description, the driving devices 1 _a and 1 _b may generate POL ₂ .

Next, the third drive device when three or more drive devices are provided side by side will be described. FIG. 32 is an explanatory diagram showing a configuration example of the third drive device _1c . The first driving device 1 _a and the second drive unit 1 _b and similar components are denoted by the same reference numerals as in FIG. 28 and FIG. 30, detailed description thereof is omitted. The third driving device 1 _c includes a potential setting unit 2, a V _p setting unit 3, a V _n setting unit 4, a V _p setting wiring 5, and a V _n setting wiring 6. All of these elements are the potential setting unit 2, the V _p setting unit 3, the V _n setting unit 4, the V _p setting wiring 5, V, and the like included in the first driving device 1 _a and the second driving device 1 _{b. This is the same as the n} setting wiring 6 (see FIGS. 28 and 30).

Also, for each switch 14, 15 provided in association with the potential output terminals D ₂ to D _n from the second from the left to the n-th when viewed from the viewing side, the first driving device 1 _a and the second drive switch 15 (see FIGS. 28 and 30) the device _{1 b} is provided it is the same as.

Switch 91 provided in association with the left to the (n + 1) th potential output terminal D _{n + 1} as seen from the viewing side, is similar to the switch 91 provided in the first driving device 1 _a (see FIG. 28).

Switch 92 provided in association with the potential output terminal D ₁ of the leftmost as viewed from the viewing side, it is similar to the switch 92 (see FIG. 30) provided in the second drive unit 1 _b. When a plurality of driving devices are employed, each of the plurality of driving devices may be a driving device having the same function. For example, when arranging three driving device, arranged three the third driving device 1 _c shown in FIG. 32, the switch provided the leftmost potential output terminal of the leftmost drive, a switch 11 What is necessary is just to control so that it may have the same function. Further, a switch provided at the (n + 1) th potential output terminal from the left in the third driving device from the left may be controlled so as to have the same function as the switch 12.

The second embodiment may be applied to the third embodiment. That is, consecutive rows of pixel electrodes 21 arranged in a matrix are grouped together, the pixel electrodes of each row of the odd-numbered group are connected to the left source line, and the pixel electrodes of each row of the even-numbered group are connected to the right side. It may be configured to be connected to the source line. At this time, POL ₁ and POLS ₂ may be generated in the same manner as in the second embodiment. In this case, the switches 11, 12, 14, and 15 may operate in the same manner as the switches 11, 12, 14, and 15 in the second embodiment.

  Further, when the second embodiment is applied to the third embodiment, the switches 91 and 92 only need to repeat the operation for every two groups of scanning periods.

FIG. 33 is an explanatory diagram showing the operation of the switch 91 when the second embodiment is applied to the third embodiment. In this case, in a frame in which POL ₁ is at a high level (see FIG. 33A), the switch 91 branches the source line _{Sn + 1} during the scanning period for one group corresponding to the first half of the scanning period for two groups. What is necessary is just to continue connecting the part 41 to the electric potential output terminal Dn _{+ 1} . As a result, the branch part 41 of the source line _{Sn + 1} is in a high impedance state. However, the switch 91 does not connect the branch portion 41 of the source line S _{n + 1 to} any _one of the potential output terminal D _{n + 1} , the V _p setting wiring 5, and the V _n setting wiring 6, thereby setting the high impedance state. Good. When This lack the demultiplexer 41 is connected to the potential output terminal D _{n + 1,} during the scan period of the one group, the potential output terminals D _{n + 1} may not be a high-impedance state.

Further, during the scanning period for one group corresponding to the latter half of the scanning period for two groups, when the STB is at a high level, the branch part 41 of the source line _{Sn + 1} is connected to the V _p setting wiring 5, and the STB The branch portion 41 of the source line _{Sn + 1} may be connected to the potential output terminal Dn _{+ 1} when the level is low.

In a frame in which POL ₁ is at a low level (see FIG. 33B), the switch 91 is a branching section of the source line _{Sn + 1} during the scanning period for one group corresponding to the first half of the scanning period for two groups. What is necessary is just to continue connecting 41 to the potential output terminal Dn _{+ 1} . As a result, the branch part 41 of the source line _{Sn + 1} is in a high impedance state. However, as described above, the switch 91 does not connect the branch portion 41 of the source line S _{n + 1} to any of the potential output terminal D _{n + 1} , the V _p setting wiring 5, and the V _n setting wiring 6. It may be in an impedance state. When This lack the demultiplexer 41 is connected to the potential output terminal D _{n + 1,} during the scanning period of one group, the potential output terminals D _{n + 1} it may not be a high-impedance state.

Further, during the scanning period for one group corresponding to the latter half of the scanning period for two groups, when the STB is at a high level, the branch part 41 of the source line S _{n + 1} is connected to the V _n setting wiring 6 so that the STB The branch portion 41 of the source line _{Sn + 1} may be connected to the potential output terminal Dn _{+ 1} when the level is low.

FIG. 34 is an explanatory diagram showing the operation of the switch 92 when the second embodiment is applied to the third embodiment. In this case, in a frame in which POL ₁ is at a high level (see FIG. 34A), the switch 92 operates when the STB is at a high level during the scanning period for one group corresponding to the first half of the scanning period for two groups. a branch portion 42 of the source line _{S n + 1} is connected to _{V p} setting wiring 5, STB is it is only necessary to connect the branch portions 42 of the source line _{S n + 1} to the potential output terminals _{D 1} at a low level.

Also, during the one group of the scanning period corresponding to the latter half of the scanning period of the second group component may be it continues to connect the branch portions 42 of the source line S _{n + 1} to the potential output terminal D _1. As a result, the branch part 42 of the source line _{Sn + 1} is in a high impedance state. However, the switch 92 does not connect the branch portion 42 of the source line S _{n + 1 to} any _one of the potential output terminal D ₁ , the V _p setting wiring 5, and the V _n setting wiring 6, thereby setting the high impedance state. Good. When the thus does not connect the branching unit 42 to the potential output terminals D _1, during the scanning period of the one group, the potential output terminals D ₁ may not be a high-impedance state.

In a frame in which POL ₁ is at a low level (see FIG. 34 (b)), the switch 92 causes the source line when the STB is at a high level during the scanning period for one group corresponding to the first half of the scanning period for two groups. a branch portion 42 of the S _{n + 1} is connected to _{V n} setting wiring 6, STB is it is only necessary to connect the branch portions 42 of the source line _{S n + 1} to the potential output terminals _{D 1} at a low level.

Also, during the one group of the scanning period corresponding to the latter half of the scanning period of the second group component may be it continues to connect the branch portions 42 of the source line S _{n + 1} to the potential output terminal D _1. As a result, the branch part 42 of the source line _{Sn + 1} is in a high impedance state. However, as described above, the switch 92 does not connect the branch portion 42 of the source line S _{n + 1 to} any _one of the potential output terminal D ₁ , the V _p setting wiring 5, and the V _n setting wiring 6. It may be in an impedance state. When the thus does not connect the branching unit 42 to the potential output terminals D _1, during the scanning period of the one group, the potential output terminals D ₁ may not be a high-impedance state.

  In addition, the liquid crystal display device of each embodiment of the present invention may be normally black or normally white.

  In each of the above embodiments, the case where pixels are arranged in the order of R, G, and B in each row of the liquid crystal display panel has been described as an example. However, the arrangement mode of the R, G, and B pixels is not particularly limited. . Further, the liquid crystal display panel may perform monochrome display.

  In addition, it can be said that the STB described in each of the above embodiments is a signal that defines a precharge period and a period in which a potential corresponding to a pixel value is set for a source line. That is, the period during which STB is at a high level corresponds to the precharge period. In addition, a period in which STB is at a low level corresponds to a period in which a potential corresponding to a pixel value is set for the source line.

  The present invention is preferably applied to an active matrix liquid crystal display device.

DESCRIPTION OF SYMBOLS 1 Drive apparatus 1 _a 1st drive apparatus 1 _b 2nd drive apparatus 1 _c 3rd drive apparatus 2 Potential setting part 3 _Vp setting part (1st precharge electric potential setting part)
4 V _n setting unit (second precharge potential setting unit)
5 _Vp setting wiring (first precharge potential setting wiring)
6 V _n setting wiring (second precharge potential setting wiring)
11, 12, 14, 15, 91, 92 switch

Claims (5)

An active matrix liquid crystal display panel;
A driving device for driving the liquid crystal display panel;
The liquid crystal display panel is
A common electrode;
A plurality of pixel electrodes arranged in a matrix;
Including one more source line than the number of columns of pixel electrodes,
Each column of pixel electrodes is disposed between adjacent source lines,
When the pixel electrode rows are grouped for each row or for each of a plurality of consecutive rows, the pixel electrodes of each row of the odd-numbered group are predetermined among the source lines existing on both sides of the pixel electrode. The pixel electrodes of each row of the even-numbered group are connected to the source line on the opposite side to the predetermined side among the source lines existing on both sides of the pixel electrode,
The driving device includes:
A positive electrode that has a potential output terminal that outputs a potential corresponding to a pixel value included in image data to the source line for each source line, and is higher than the potential of the common electrode from the odd-numbered potential output terminal from the predetermined side. A first potential output mode that outputs a negative potential that is lower than the potential of the common electrode from an even-numbered potential output terminal from the predetermined side, and an odd-numbered potential from the predetermined side A potential output unit that outputs a negative potential from an output end and alternately switches a second potential output mode that outputs a positive potential from an even-numbered potential output end from the predetermined side;
First preliminary potential output means for outputting a first preliminary potential that is a potential set in the source line before a positive potential corresponding to the pixel value is output to the source line;
Second preliminary potential output means for outputting a second preliminary potential that is a potential set in the source line before a negative potential corresponding to the pixel value is output to the source line;
The potential output means includes
Assuming that the number of source lines is n + 1, the potential output terminals from the first to the nth from the predetermined side after the preliminary potential setting period in the period in which each row of the odd-numbered group is selected in each frame. In the period in which the potential corresponding to the pixel value is output from each row and all the rows in the even-numbered group are all selected, the pixels from the second to n + 1th potential output ends from the predetermined side after the preliminary potential setting period, respectively. Output the potential according to the value,
The driving device includes:
A first source line that connects the first source line from the predetermined side to the first preliminary potential output means, the second preliminary potential output means, or the first potential output terminal from the predetermined side in the potential output means. Switching means,
For the final source line that connects the n + 1th source line from the predetermined side to the n + 1th potential output terminal from the predetermined side in the first preliminary potential output means, the second preliminary potential output means, or the potential output means Switching means;
Among the source lines other than the first and n + 1th source lines from the predetermined side, even-numbered source lines are even numbers from the predetermined side in the first preliminary potential output means, the second preliminary potential output means, or the potential output means. Switching means for even-numbered source lines connected to the first potential output terminal,
Out of the first and n + 1th source lines from the predetermined side, odd-numbered source lines are odd numbers from the predetermined side in the first preliminary potential output means, the second preliminary potential output means, or the potential output means. Switching means for odd-numbered source lines connected to the first potential output terminal,
The first source line switching means is:
The first source line from the predetermined side is used as the first preliminary potential output means during the preliminary potential setting period during the period in which each row of the odd-numbered group is selected in the frame serving as the first potential output mode. After the preliminary potential setting period, the source line is connected to the first potential output terminal from the predetermined side, and the source line is connected to the first line during a period when all the rows of the even-numbered group are selected. Connect to the preliminary potential output means,
In the frame in which the second potential output mode is selected, the first source line from the predetermined side is used as the second preliminary potential output means during the preliminary potential setting period during the period when all the rows of the odd-numbered group are selected. After the preliminary potential setting period has elapsed, the source line is connected to the first potential output terminal from the predetermined side, and the source line is connected to the second line during a period in which all the rows in the even-numbered group are selected. Connect to the preliminary potential output means,
The switching means for the final source line is
During the period when all the rows of the odd-numbered group are selected in the frame that is the first potential output mode, the n + 1th source line from the predetermined side is connected to the first preliminary potential output means or the second preliminary potential output. The source line is connected to the first preliminary potential output means or the second preliminary potential output means during the preliminary potential setting period during which all the rows of the even-numbered groups are selected. After the elapse of time, the source line is connected to the (n + 1) th potential output terminal from the predetermined side,
In the frame in which the second potential output mode is selected, the n + 1th source line from the predetermined side is connected to the first preliminary potential output means and the second preliminary potential output during the period when all the rows of the odd-numbered group are selected. Among the means, the source line is connected to the one different from the frame serving as the first potential output mode, and the source line is connected to the first preliminary potential during the preliminary potential setting period during the period when all the rows of the even-numbered group are selected. The output means and the second preliminary potential output means are connected to a different one from the frame that is the first potential output mode, and after the preliminary potential setting period, the n + 1th potential output terminal from the predetermined side Connect the source lines,
The switching means for even-numbered source lines is
Within the frame serving as the first potential output mode, the even-numbered source lines from the predetermined side are connected to the second preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period has elapsed, Connect the source line to the even-numbered potential output terminal from the side,
Within the frame serving as the second potential output mode, the even-numbered source lines from the predetermined side are connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period has elapsed, Connect the source line to the even-numbered potential output terminal from the side,
The switching means for odd-numbered source lines is
Within the frame serving as the first potential output mode, an odd-numbered source line from the predetermined side is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period has elapsed, The source line is connected to the odd-numbered potential output terminal from the side,
In the frame serving as the second potential output mode, an odd-numbered source line from the predetermined side is connected to the second preliminary potential output means in the preliminary potential setting period, and after the preliminary potential setting period has elapsed, A liquid crystal display device comprising: the source line connected to an odd-numbered potential output terminal from the side. An active matrix liquid crystal display panel;
A plurality of driving devices arranged side by side to drive the liquid crystal display panel;
The liquid crystal display panel is
A common electrode;
A plurality of pixel electrodes arranged in a matrix;
Including one more source line than the number of columns of pixel electrodes,
Each column of pixel electrodes is disposed between adjacent source lines,
When the pixel electrode rows are grouped for each row or for each of a plurality of consecutive rows, the pixel electrodes of each row of the odd-numbered group are predetermined among the source lines existing on both sides of the pixel electrode. The pixel electrodes of each row of the even-numbered group are connected to the source line on the opposite side to the predetermined side among the source lines existing on both sides of the pixel electrode,
Each of the plurality of driving devices is
A positive potential having a plurality of potential output terminals for outputting a potential corresponding to a pixel value included in the image data to the source line, which is higher than the potential of the common electrode from the odd-numbered potential output terminal from the predetermined side. And a negative potential that is lower than the potential of the common electrode from the even-numbered potential output terminal from the predetermined side, and an odd-numbered potential output terminal from the predetermined side A potential output means for outputting a negative potential from the second potential output mode for alternately outputting a positive potential from an even-numbered potential output terminal from the predetermined side for each frame;
First preliminary potential output means for outputting a first preliminary potential that is a potential set in the source line before a positive potential corresponding to the pixel value is output to the source line;
Second preliminary potential output means for outputting a second preliminary potential that is a potential set in the source line before a negative potential corresponding to the pixel value is output to the source line;
When the number of potential output terminals of the potential output means provided in each driving device is n + 1, n + 1 is an odd number,
When the number of the plurality of driving devices is u and v is an integer greater than or equal to 1 and less than u, the v · n + 1th source line from the predetermined side has a first branch portion and a second branch portion,
The first branch portion of the (v · n + 1) th source line from the predetermined side is connected to the (n + 1) th potential output terminal from the predetermined side in the vth driving device from the predetermined side, and the first branch portion of the source line is connected. The two branch portions are connected to the first potential output terminal from the predetermined side in the (v + 1) th driving device from the predetermined side,
The potential output means provided in each driving device, respectively,
In the period in which each row of the odd-numbered group is selected in each frame, the potential corresponding to the pixel value is output from the first to nth potential output terminals from the predetermined side after the preliminary potential setting period. In the period in which all the rows of the even-numbered groups are selected, the potential corresponding to the pixel value is output from the second to n + 1th potential output terminals from the predetermined side after the preliminary potential setting period,
Of the plurality of drive devices, a first drive device that is a drive device arranged first from the predetermined side is:
The source line corresponding to the first potential output terminal from the predetermined side in the potential output means of the driving device itself is connected to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal. First switching means;
The first branch portion of the source line corresponding to the (n + 1) th potential output terminal from the predetermined side in the potential output means of the driving device itself is connected to the first preliminary potential output means, the second preliminary potential output means, or the potential A second switching means to be connected to the output end or not to be connected to either,
Of the plurality of drive devices, a second drive device that is a drive device disposed at a position farthest from the predetermined side,
The second branch portion of the source line corresponding to the first potential output terminal from the predetermined side in the potential output means of the driving device itself is connected to the first preliminary potential output means, the second preliminary potential output means, or the potential A third switching means to be connected to the output terminal or not to be connected to either of them;
A source line corresponding to the (n + 1) th potential output terminal from the predetermined side in the potential output means of the driving device itself is connected to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal. A fourth switching means,
The plurality of driving devices are all
Fifth switching means for connecting a source line corresponding to an even-numbered potential output terminal from the predetermined side in the potential output means to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal; ,
Sixth switching means for connecting a source line corresponding to an odd-numbered potential output terminal from the predetermined side in the potential output means to the first preliminary potential output means, the second preliminary potential output means, or the potential output terminal; With
The first switching means is
The first potential from the predetermined side in the potential output means of the driving device provided with the first switching means during a period in which all the rows of the odd-numbered group are selected in the frame serving as the first potential output mode. The source line corresponding to the output terminal is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the source line is connected to the potential output terminal, and each row of the even-numbered group During the period in which all are selected, the source line is connected to the first preliminary potential output means,
During the period when all the rows of the odd-numbered group are selected in the frame that is the second potential output mode, the source line is connected to the second preliminary potential output means during the preliminary potential setting period, and the preliminary potential setting period After the elapse of time, the source line is connected to the potential output terminal, and the source line is connected to the second preliminary potential output means during a period in which all the rows of the even-numbered groups are selected,
The second switching means is
The n + 1th potential from the predetermined side in the potential output means of the driving device provided with the second switching means during the period when all the rows of the odd-numbered group are selected in the frame that is the first potential output mode. The first branch portion of the source line corresponding to the output terminal is set to the high impedance state, and the first branch portion of the source line is set to the first spare in the spare potential setting period during the period when all the rows of the even-numbered group are selected. Connected to the potential output means, and after the preliminary potential setting period, the first branch portion of the source line is connected to the potential output terminal,
In a frame in which the second potential output mode is selected, the first branch portion of the source line is set to a high impedance state and all the rows of the even-numbered groups are selected during a period in which all the rows of the odd-numbered groups are selected. During the period, the first branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the first branch portion of the source line is connected to the potential output terminal. Connect
The third switching means is
The first potential from the predetermined side in the potential output means of the driving device provided with the third switching means during the period in which all the rows of the odd-numbered group are selected in the frame serving as the first potential output mode. The second branch portion of the source line corresponding to the output terminal is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the second branch section of the source line is connected to the potential output terminal. And the second branch portion of the source line is in a high impedance state during a period in which each row of the even-numbered group is all selected,
The second branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period during a period in which each row of the odd-numbered group is selected in the frame serving as the second potential output mode. After the elapse of the preliminary potential setting period, the second branch part of the source line is connected to the potential output terminal, and the second branch part of the source line is set to the high level during the period when all the rows of the even-numbered group are selected. Impedance state,
The fourth switching means is
The n + 1th potential from the predetermined side in the potential output means of the driving device provided with the fourth switching means during a period in which all the rows of the odd-numbered group are selected in the frame serving as the first potential output mode. The source line corresponding to the output terminal is connected to the first preliminary potential output means, and the source line is used as the first preliminary potential output means during the preliminary potential setting period during the period when all the rows of the even-numbered group are selected. After the preliminary potential setting period has elapsed, connect the source line to the potential output terminal,
In the frame in which the second potential output mode is selected, the source lines are connected to the second preliminary potential output means during the period in which all the odd-numbered groups are selected, and all the even-numbered groups are selected. The source line is connected to the second preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the source line is connected to the potential output terminal,
The fifth switching means is
In the frame serving as the first potential output mode, the source line corresponding to the even-numbered potential output terminal from the predetermined side in the potential output means is connected to the second preliminary potential output means during the preliminary potential setting period, After the potential setting period, connect to the potential output terminal,
In the frame serving as the second potential output mode, the source line is connected to the first preliminary potential output means during the preliminary potential setting period, and is connected to the potential output terminal after the preliminary potential setting period has elapsed.
The sixth switching means is
In the frame serving as the first potential output mode, the source line corresponding to the odd-numbered potential output terminal from the predetermined side in the potential output means is connected to the first preliminary potential output means during the preliminary potential setting period, After the potential setting period, connect to the potential output terminal,
In the frame serving as the second potential output mode, the source line is connected to the second preliminary potential output means during the preliminary potential setting period, and is connected to the potential output terminal after the preliminary potential setting period has elapsed. A liquid crystal display device. 3. The liquid crystal display according to claim 2, wherein among the plurality of driving devices, each driving device other than the first driving device and the second driving device includes the second switching unit and the third switching unit. apparatus. The potential output means provided in each driving device, respectively,
After the preliminary potential setting period in which the source line is set to the first preliminary potential or the second preliminary potential, the first or n + 1th potential output terminal from the predetermined side is set to the high impedance state, and the pixels from the other potential output terminals are respectively Output the potential according to the value,
In the period in which each row of the odd-numbered group is selected in each frame, the potential corresponding to the pixel value is output from the first to nth potential output terminals from the predetermined side after the preliminary potential setting period. In the period in which the n + 1th potential output terminal is set to the high impedance state and all the rows of the even-numbered group are selected, the second to n + 1th potential output terminals from the predetermined side after the preliminary potential setting period. Each outputs a potential according to the pixel value, and the first potential output terminal is in a high impedance state,
The second switching means is
The n + 1th potential from the predetermined side in the potential output means of the driving device provided with the second switching means during the period when all the rows of the odd-numbered group are selected in the frame that is the first potential output mode. The first branch part of the source line corresponding to the output terminal is connected to the potential output terminal, and the first branch part of the source line is set to the preliminary potential setting period during the period when all the rows of the even-numbered group are selected. Connected to the first preliminary potential output means, and after the preliminary potential setting period, the first branch portion of the source line is connected to the potential output terminal,
In a frame in which the second potential output mode is selected, the first branch portion of the source line is connected to the potential output terminal while all the odd-numbered groups of rows are selected, and all the even-numbered groups of rows are all connected. During the selected period, the first branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the first branch portion of the source line is connected to the potential. Connect to the output end,
The third switching means is
The first potential from the predetermined side in the potential output means of the driving device provided with the third switching means during the period in which all the rows of the odd-numbered group are selected in the frame serving as the first potential output mode. The second branch portion of the source line corresponding to the output terminal is connected to the first preliminary potential output means during the preliminary potential setting period, and after the preliminary potential setting period, the second branch section of the source line is connected to the potential output terminal. And connecting the second branch portion of the source line to the potential output terminal during a period in which all the rows of the even-numbered group are selected.
The second branch portion of the source line is connected to the second preliminary potential output means during the preliminary potential setting period during a period in which each row of the odd-numbered group is selected in the frame serving as the second potential output mode. After the elapse of the preliminary potential setting period, the second branch part of the source line is connected to the potential output terminal, and the second branch part of the source line is connected to the potential output terminal during the period when all the rows of the even-numbered group are selected. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is connected to a potential output terminal. A negative polarity potential corresponding to the maximum tone and V _b, a positive polarity potential corresponding to the maximum gradation when the V _a, the first preliminary _{potential, V b + (3/4) ×} (V a - a V _b), the second preliminary _{potential, V b + (1/4) ×} (V a -V b) a liquid crystal display device as claimed in any one of claims 4 .

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