JP2013109130A - Electro-optical device, electronic apparatus and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a reduction in gradation expression capability in a case where a subfield system is used in an electro-optical device having pixels arranged in a Bayer arrangement.SOLUTION: An electro-optical device includes: a plurality of pixels of which first color pixels, second color pixels and third color pixels are arranged in a Bayer arrangement; a first scan line group including a plurality of scan lines for selecting the first color pixels out of the plurality of pixels; a second scan line group including a plurality of scan lines for selecting the second color pixels and the third color pixels out of the plurality of pixels; and a scan line driving circuit that sequentially selects one scan line out of the first scan line group and the second scan line group when a mode signal indicates a first mode and sequentially selects one scan line out of the first scan line group when the mode signal indicates a second mode.

Description

  The present invention relates to a technique for driving a plurality of pixels arranged in a Bayer subfield.

  As a gradation control method in an electro-optical element such as a liquid crystal element, in addition to a voltage modulation method that modulates a voltage applied to the electro-optical element, so-called subfield driving that modulates a time during which a constant voltage is applied to the electro-optical element. The method is known. In the subfield driving method, one frame is divided into a plurality of subfields. The gray level of the electro-optic element is controlled by a combination (precisely permutation) of a subfield that turns on and off a voltage application among a plurality of subfields.

  One technique for improving gradation expression in subfield driving is to shorten one subfield. As a technique for shortening the subfield, so-called area scanning driving is known (Patent Document 1).

  A so-called Bayer arrangement is known as a method for two-dimensionally arranging three primary colors of red (R), green (G), and blue (B) (Patent Document 2). The Bayer arrangement is an arrangement in which one R pixel and one B pixel and one G2 pixel are combined. In the Bayer arrangement, G has twice as much information as R and B per unit area. This is in consideration of human visibility characteristics.

JP 2004-177930 A U.S. Pat. No. 3,971,065

When white balance is achieved in an electro-optical device having pixels arranged in a Bayer arrangement, it is conceivable that the luminance of the G pixel is half that of the R and B pixels. If this is to be realized by the sub-field driving method, it is necessary to set the luminance of the G pixel to a half of the period of one frame. This means that the number of subfields that can be used for gradation expression in the G pixel is smaller than that in the R and B pixels. That is, the G gradation expression is reduced.
On the other hand, the present invention provides a technique for suppressing a reduction in gradation expression capability when a subfield method is used in an electro-optical device having pixels arranged in a Bayer arrangement.

The present invention relates to a plurality of pixels in which a first color pixel, a second color pixel, and a third color pixel are arranged in a Bayer arrangement, and a plurality of pixels for selecting the first color pixel among the plurality of pixels. A first scanning line group including a plurality of scanning lines, a second scanning line group including a plurality of scanning lines for selecting the pixels of the second color and the third color among the plurality of pixels, and a mode signal When the first mode is indicated, one scanning line is sequentially selected from the first scanning line group and the second scanning line group, and when the mode signal indicates the second mode, the first mode is selected. An electro-optical device having a scanning line driving circuit for sequentially selecting one scanning line from a scanning line group is provided.
According to the electro-optical device, it is possible to suppress a decrease in gradation expression capability as compared with a configuration that does not have an operation mode in which one scanning line is sequentially selected from the first scanning line group.

In a preferred aspect, the electro-optical device converts the image data indicating the gradation value of the pixel and applies a voltage corresponding to the subfield code indicating the on / off permutation of the plurality of subfields to the plurality of pixels. A data line driving circuit may be provided, and the number of subfields in the pixels of the first color may be different from the number of subfields in the pixels of the second color and the third color.
According to this electro-optical device, it is possible to suppress a decrease in gradation expression capability due to a decrease in the number of subfields.

In another preferable aspect, the plurality of pixels are arranged in a matrix of m rows and n columns, and the first scanning line group and the second scanning line group have (m + 1) scanning lines in total. The scanning lines of the first scanning line group and the scanning lines of the second scanning line group are alternately arranged, and the electro-optical device transfers the start pulse signal step by step, and the (m + 1) lines are transferred. (M + 1) stages of first shift registers corresponding to a plurality of scanning lines, the mode signal being transferred one stage at a time, and (m + 1) stages of second shift registers corresponding to the (m + 1) scanning lines, A signal corresponding to the start pulse signal is output to the scan line of the first scan line group, and a signal corresponding to the logical product of the start pulse signal and the mode signal is output to the scan line of the second scan line group. May be included.
According to this electro-optical device, it is possible to suppress a decrease in gradation expression capability when scanning is started by a start pulse signal.

In still another preferred embodiment, the first shift register and the second shift register transfer the start pulse signal and the mode signal to a subsequent stage at a timing according to a clock signal, and the electro-optical device transmits the clock signal. A first enable signal line for transmitting a first enable signal for selecting one of the plurality of sub-periods obtained by dividing the unit period into a plurality of sub-periods. And a second enable signal line for transmitting a second enable signal for selecting a sub period different from the one sub period, and the output circuit includes a first scan line of the first scan line group. , Outputting a signal corresponding to a logical product of the start pulse signal and the first enable signal, and adjacent to the first scanning line. A signal corresponding to the logical product of the start pulse signal, the mode signal, and the first enable signal is output to the second scan line of the two scan line groups, and is output to the third scan line of the first scan line group. Outputs a signal corresponding to the logical product of the start pulse signal and the second enable signal, and the start pulse signal is applied to the fourth scan line of the second scan line group adjacent to the third scan line, A signal corresponding to the logical product of the mode signal and the second enable signal may be output.
According to this electro-optical device, when a plurality of scans coexist in one clock, it is possible to suppress a decrease in gradation expression capability.

In still another preferred embodiment, the first shift register transfers the start pulse signal in a direction corresponding to a direction signal indicating a signal transfer direction, and the second shift register is in a direction corresponding to the direction signal. The mode signal may be transferred.
According to this electro-optical device, the scanning direction can be switched.

The present invention also provides an electronic apparatus having any one of the above electro-optical devices.
According to this electronic apparatus, it is possible to suppress a decrease in gradation expression capability as compared with a configuration that does not have an operation mode in which one scanning line is sequentially selected from the first scanning line group.

Further, the present invention selects a first color pixel, a second color pixel, a plurality of pixels in which a third color pixel is arranged in a Bayer arrangement, and the first color pixel among the plurality of pixels. A first scanning line group including a plurality of scanning lines, and a second scanning line group including a plurality of scanning lines for selecting the pixels of the second color and the third color among the plurality of pixels. In the control method of the electro-optical device, when the mode signal indicates the first mode, one scanning line is sequentially selected from the first scanning line group and the second scanning line group, and the mode signal is selected. Provides a control method including a step of sequentially selecting one scanning line from the first scanning line group.
According to this control method, it is possible to suppress a decrease in gradation expression capability as compared with a configuration that does not have an operation mode in which one scanning line is sequentially selected from the first scanning line group.

1 is a diagram showing an outline of an electronic device 1. FIG. 2 is a block diagram showing a circuit configuration of the liquid crystal panel 100. FIG. FIG. 6 shows an equivalent circuit of a pixel 111. The figure which shows the correspondence of a pixel and a scanning line. FIG. 9 shows a structure of a scan line driver circuit 130. FIG. 11 shows a structure of a shift circuit 1311. FIG. 4 is a diagram showing a configuration of a data line driving circuit 140. 4A and 4B illustrate an outline of operation of a scan line driver circuit 130. FIG. FIG. 6 is a diagram illustrating a timing chart of the scan line driver circuit 130. FIG. 10 is a diagram showing a configuration of a scanning line driving circuit according to a first modification.

1. Embodiment 1-1. Configuration FIG. 1 is a diagram illustrating an outline of an electronic apparatus 1 according to an embodiment. The electronic device 1 is a device that displays an image, in this example, a projector. “Video” is a concept that includes still images and moving images. The electronic device 1 is a device that displays an image indicated by the video signal Vid-in supplied from the host device on the liquid crystal panel 100 at a timing based on the synchronization signal Sync.

  The electronic apparatus 1 includes an electro-optical device 10 and a video processing circuit 20. The electro-optical device 10 includes a liquid crystal panel 100 (an example of an electro-optical panel), a control circuit, a light source, and an optical system (other than the liquid crystal panel 100 is not shown). The liquid crystal panel 100 has a plurality of pixels arranged in a matrix of m rows and n columns. The liquid crystal panel 100 is a color liquid crystal panel, and has pixels of three primary colors of red (R), green (G), and blue (B).

  The R, G, and B pixels are arranged in a Bayer arrangement. In the Bayer arrangement, R, G, and B pixels are arranged in units of 4 pixels in 2 rows and 2 columns (hereinafter referred to as “unit region”). The unit area includes one R pixel and one B pixel, and two G pixels. The two G pixels are arranged obliquely.

  The video processing circuit 20 performs image processing, for example mosaic processing, on the input image data. Hereinafter, input image data is referred to as “input image data”, and an image indicated by the input image data is referred to as “input image”. The input image data includes three color components R, G, and B per pixel. Consider a case where the number of pixels of the input image is m × n, that is, the number of pixels of the liquid crystal panel 100 is equal. In this case, for R and B, the number of pixels of the liquid crystal panel 100 is 1/4 of the input image, and for G, the number of pixels of the liquid crystal panel 100 is 1/2 of the input image. For example, when R is considered, a process (mosaicing process) for converting 4-pixel data of an input image into 1-pixel data is necessary. Various algorithms for mosaicing processing are known, and any algorithm may be used here.

  FIG. 2 is a block diagram illustrating a circuit configuration of the liquid crystal panel 100. The liquid crystal panel 100 is a device that displays an image according to a supplied signal. The liquid crystal panel 100 includes a display area 101, a scanning line driving circuit 130, and a data line driving circuit 140. A plurality of pixels 111 are arranged in the display area 101. In this example, m rows and n columns of pixels 111 are arranged in a matrix. The liquid crystal panel 100 includes an element substrate 100a, a counter substrate 100b, and a liquid crystal layer 105. The element substrate 100a and the counter substrate 100b are bonded to each other with a constant interval. A liquid crystal layer 105 is sandwiched between the element substrate 100a and the counter substrate 100b. The element substrate 100 a is provided with (m + 1) scanning lines 112 and n data lines 114. The scanning lines 112 and the data lines 114 are provided on the surface facing the counter substrate 100b. The scanning line 112 and the data line 114 are electrically insulated. A pixel 111 is provided corresponding to the intersection of the scanning line 112 and the data line 114. In the following, in order to distinguish between the plurality of scanning lines 112, scanning of the first, second, third,..., (M−1) th, (m + 1) th, and mth rows in order from the top in FIG. This is called line 112. Similarly, when distinguishing a plurality of data lines 114, they are referred to as the first, second, third,..., (N−1) th, nth column data lines 114 in order from the left in FIG. In FIG. 2, since the opposing surface of the element substrate 100a is the back side of the paper surface, the scanning lines 112 and the data lines 114 provided on the opposing surface should be indicated by broken lines. Is shown.

  A common electrode 108 is provided on the counter substrate 100b. The common electrode 108 is provided on one surface facing the element substrate 100a. The common electrode 108 is common to all the pixels 111. That is, the common electrode 108 is a so-called solid electrode provided over almost the entire surface of the counter substrate 100b.

  The liquid crystal panel 100 further includes a plurality of enable signal lines, in this example, six enable signal lines ENB1 to ENB6. The enable signal will be described later.

  FIG. 3 is a diagram illustrating an equivalent circuit of the pixel 111. The pixel 111 includes a TFT (Thin Film Transistor) 116, a liquid crystal element 120, and a capacitor element 125. The TFT 116 is an example of a switching unit that controls application of a voltage to the liquid crystal element 120. In this example, the TFT 116 is an n-channel field effect transistor. The liquid crystal element 120 is an element whose optical state changes according to an applied voltage. In this example, the liquid crystal panel 100 is a transmissive liquid crystal panel, and the optical state that changes is the transmittance. The liquid crystal element 120 includes a pixel electrode 118, a liquid crystal layer 105, and a common electrode 108. In the pixel 111 in the i-th row and the j-th column, the gate and the source of the TFT 116 are connected to the scanning line 112 in the i-th row and the data line 114 in the j-th column, respectively. The drain of the TFT 116 is connected to the pixel electrode 118. The capacitor element 125 is an element that holds a voltage written in the pixel electrode 118. One end of the capacitive element 125 is connected to the pixel electrode 118, and the other end is connected to the capacitive line Vcom.

  When a signal indicating an H level voltage is input to the i-th scanning line 112, the source and drain of the TFT 116 become conductive. When the source and drain of the TFT 116 are conducted, the pixel electrode 118 has the same potential as the data line 114 in the j-th column (ignoring the on-resistance between the source and drain of the TFT 116). In the data line 114 in the j-th column, the voltage corresponding to the gradation value of the pixel 111 in the i-th row and the j-th column (hereinafter referred to as “data voltage”) indicates the data voltage in accordance with the video signal Vid-in. The signal is referred to as a “data signal”. A common potential LCcom is applied to the common electrode 108 by a circuit (not shown). The capacitor line Vcom is given a temporally constant potential Vcom (in this example, Vcom = LCcom) by a circuit (not shown). That is, a voltage corresponding to the difference between the data voltage and the common potential LCcom is applied to the liquid crystal element 120. Hereinafter, description will be made using an example in which the liquid crystal layer 105 is a VA (Vertical Alignment) type and is a normally black mode in which the gradation of the liquid crystal element 120 is in a dark state (black state) when no voltage is applied. Unless otherwise specified, the ground potential not shown is a voltage reference (zero V).

  Since the liquid crystal panel 100 is driven in a subfield, the absolute value of the voltage applied to the liquid crystal element 120 is 2 of VH (an example of the first voltage, for example, 5 V) or VL (an example of the second voltage, for example, zero V). One of the values.

  FIG. 4 is a diagram illustrating a correspondence relationship between pixels and scanning lines. In this example, the G pixel is on the odd-numbered ((2k + 1) th row: k is a natural number including zero) scanning line 112, and the R pixel and B pixel are on the even-numbered ((2k + 2)) scanning line 112. Each is connected. That is, when the odd-numbered scanning line 112 is selected, only the G pixel is selected (R and B pixels are not selected), and when the even-numbered scanning line 112 is selected, only the R and B pixels are selected (G pixel). Can not choose). The odd-numbered scanning lines 112 are an example of a first scanning line group, and the even-numbered scanning lines 112 are an example of a second scanning line group.

  FIG. 5 is a diagram illustrating a configuration of the scanning line driving circuit 130. The scanning line driving circuit 130 is a circuit that outputs a scanning signal G for selecting the scanning line 112 in accordance with an input control signal. As the control signals, a start pulse signal SPY, a clock signal CKY, an enable signal ENB, and a mode signal MODE are used. A scanning signal supplied to the i-th scanning line 112 is referred to as a scanning signal Gi. The scanning signal Gi is a signal for selecting one scanning line 112 from among (m + 1) scanning lines 112. The scanning signal Gi is a signal that becomes a selection voltage (H level) for the selected scanning line 112 and a non-selection voltage (L level) for the other scanning lines 112. A signal indicating the selection voltage is referred to as a selection signal, and a signal indicating the non-selection voltage is referred to as a non-selection signal.

  In this example, the scanning line driving circuit 130 selects a plurality of scanning lines 112 in a single clock (an example of a unit period). More specifically, one clock is further divided into a plurality of periods (hereinafter, this subdivided period is referred to as “address”, which is an example of a sub-period), and a single scanning line at a single address. 112 is selected. When one clock is composed of a addresses, a maximum of a scanning lines 112 can be selected with one clock. The enable signal is a signal for specifying an address to be used among the a addresses. In this example, since the liquid crystal panel 100 has six enable signal lines ENB1 to ENB6, one clock is divided into six addresses (a = 6).

  The scan line driver circuit 130 includes a shift register 131, a logic circuit 132, a logic circuit 133, a shift register 134, and an output circuit 135. The i-th stage logic circuit 132 is referred to as a logic circuit 132 (i). The same applies to other elements. The shift register 131 is a circuit that transfers (shifts) the start pulse signal SPY by one stage (one row) for each clock indicated by the clock signal CKY. The shift register 131 includes (m + 1) stages of shift circuits 1311. Each shift circuit 1311 has a one-to-one correspondence with the scanning line 112.

  FIG. 6 is a diagram illustrating a configuration of the shift circuit 1311. The shift circuit 1311 includes a clocked inverter 13111, a clocked inverter 13112, and an inverter 13113. The odd-numbered clocked inverter 13111 is a circuit that functions as an inverter when the clock signal CK is at an H level and has a high impedance when the clock signal CK is at an L level. The odd-numbered clocked inverter 13112 is a circuit that functions as an inverter when the clock signal CKB is at the H level and has a high impedance when the clock signal CKB is at the L level.

  The odd-numbered shift circuit 1311 (i) receives the clock signal CKY as the clock signal CK and the inverted signal of the clock signal CKY as the clock signal CKB. The even-numbered shift circuit 1311 (i + 1) receives an inverted signal of the clock signal CKY as the clock signal CK and a clock signal as the clock signal CKB. When the clock signal CKY is at the H level, an output signal corresponding to the input signal input to the input IN of the odd-numbered shift circuit 1311 (i) is output to the output OUT. If the potential of the input IN of the odd-numbered shift circuit 1311 (i) is H level, the potential of the output OUT is also H level. At this time, the shift circuit 1311 (i + 1) of the next stage (even number stage) is in a high impedance state. When the clock signal CKY is inverted to the L level, the shift circuit 1311 (i) enters a high impedance state, and an output signal corresponding to the input signal input to the input IN of the shift circuit 1311 (i + 1) is output to the output OUT. . If the output OUT of the shift circuit 1311 (i) is H level with the previous clock, the output OUT of the shift circuit 1311 (i + 1) becomes H level. In this way, the H level signal is transferred to the shift circuit 1311 at the subsequent stage by one clock.

  Refer to FIG. 5 again. The logic circuit 132 (i) is a circuit that outputs an inverted value of the logical product of the input IN and the output OUT of the i-th shift circuit 1311 (i), that is, a NAND circuit. An output signal of the logic circuit 132 (i) is represented as a signal SRi. The signal SRi is a signal that becomes L level when the start pulse signal SPY is transferred to the i-th stage, and becomes H level in other cases.

  The shift register 134 includes (m + 1) stages of shift circuits 1341. The shift register 134 is a circuit that transfers (shifts) the mode signal MODE one step at a time indicated by the signal SRi. Each shift circuit 1341 has a one-to-one correspondence with the scanning line 112. The structure of the shift circuit 1341 is the same as that of the shift circuit 1311. Since the signal SRi and the inverted signal of the signal SRi are used as the clock signal of the shift circuit 1341, when the signal SRi is at the L level, the shift circuit 1341 (i) outputs an output signal corresponding to the input signal input to the input IN. Output to output OUT. At this time, if the potential of the input IN is H level, the potential of the output OUT is also H level. When the signal SRi becomes H level and the signal SRi + 1 becomes L level, the input IN and the output OUT of the shift circuit 1341 (i) in the (i + 1) -th stage become conductive and both become H level. In this way, the H level signal is transferred to the subsequent shift circuit 1341 by one clock. A signal output from the output OUT of the i-th stage shift circuit 1341 (i) is represented as a signal LATi.

  The odd-stage logic circuit 133 (i) (that is, when i is an odd number) is a circuit that outputs a logical product of the inverted value of the signal SRi and the inverted value of the power supply voltage VSS (corresponding to the L level). That is, the odd-stage logic circuit 133 (i) outputs an L level signal when the signal SRi is at an H level, and outputs an H level signal when the signal SRi is at an L level. The even-numbered logic circuit 133 (i) (that is, when i is an even number) is a circuit that outputs a logical product of the inverted value of the signal SRi and the inverted value of the output signal LATi of the shift circuit 1341 (i). That is, even-numbered logic circuit 133 (i) outputs an H level signal when both transferred start pulse signal SPY and mode signal MODE are at H level (when both signal SRi and signal LATi are at L level). Otherwise, an L level signal is output.

  The i-th stage output circuit 135 is a circuit that outputs a logical product of the enable signal ENBr and the output signal of the logic circuit 133 (i). Here, r is a remainder when i / 2 is divided by a for even rows (that is, when i is an even number), that is, r = ((i / 2) mod a) (where ((i / 2) When mod a) = 0, r = a). The odd row (that is, when i is an odd number) has the same value as r after one row (that is, the (i + 1) th row). For example, consider the case where a = 6. The first-stage output circuit 135 (1) is a circuit that outputs a logical product of the enable signal ENB1 and the output signal of the logic circuit 133 (1). The second-stage output circuit 135 (2) is a circuit that outputs a logical product of the enable signal ENB1 and the output signal of the logic circuit 133 (2). The third-stage output circuit 135 (3) is a circuit that outputs a logical product of the enable signal ENB2 and the output signal of the logic circuit 133 (3). The twelfth stage output circuit 135 (12) is a circuit that outputs a logical product of the enable signal ENB6 and the output signal of the logic circuit 133 (12). The 13th stage output circuit 135 (13) is a circuit that outputs a logical product of the enable signal ENB1 and the output signal of the logic circuit 133 (13). The 14th stage output circuit 135 (14) is a circuit for outputting a logical product of the enable signal ENB1 and the output signal of the logic circuit 133 (14).

  FIG. 7 is a diagram showing a configuration of the data line driving circuit 140. The data line driving circuit 140 is a circuit that samples the data signal DAT according to an input control signal and outputs a data signal S indicating a data voltage written to the pixel 111. A data signal supplied to the data line 114 in the j-th column is referred to as a data signal Sj. As the control signal, a start pulse signal SPX, a clock signal CKX, and a latch signal LAT are used.

  The data line driver circuit 140 includes a shift register 141, a first latch circuit 142, and a second latch circuit 143. The shift register 141 is a circuit that transfers the start pulse signal SPX by one stage (one column) for each clock indicated by the clock signal CKX. The first latch circuit 142 is a circuit that latches the data signal DAT at a timing indicated by an output signal from the shift register 141. The data signal DAT is dot sequential data, and the first latch circuit 142 sequentially latches the data of each pixel. The second latch circuit 143 is a circuit that latches the output signal from the first latch circuit 142 at a timing indicated by the signal LAT, and outputs it to the data line 114 as a line-sequential data signal Sj. Data signal Sj indicates voltage VH when the subfield code is on, and indicates voltage VL when the subfield code is off.

  The video processing circuit 20 is a circuit that generates a data signal DAT and a control signal based on input video data. A control signal generated by the video processing circuit 20 is input to the scanning line driving circuit 130 and the data line driving circuit 140. In this example, the video processing circuit 20 performs mosaicing processing and subfield code conversion processing. The mosaicing process is a process of converting input image data including three color components of R, G, and B per pixel into data indicating the gradation values of the pixels arranged in the Bayer arrangement.

  The subfield code conversion process is a process for converting the gradation value of each pixel after the mosaicing process into a subfield code. For example, the subfield has a configuration in which a basic unit (4SF or 6SF) is repeated a predetermined number of times. For example, when the basic unit is repeated five times in one frame, if the basic unit is 4SF (R pixel and B pixel), one frame is composed of 20SF. In this case, the subfield code is 20-bit data indicating either on or off for each subfield. In this case, when the basic unit is 6SF (G pixel), one frame is composed of 30SF. In this case, the subfield code is 30-bit data. In this example, the subfield code conversion process is performed with reference to a conversion table (not shown). The conversion table is stored in, for example, a built-in memory of the video processing circuit 20.

1-2. Operation FIG. 8 is a diagram for explaining the outline of the operation of the scanning line driving circuit 130. In FIG. 8, the horizontal axis indicates time, and the vertical axis indicates a selected row. In order to avoid complication of the drawing, in FIG. 8, the address is not considered, and a plurality of scanning lines 112 are selected at the same time. The R and B pixels are selected as indicated by solid lines (SCAN1, SCAN2, SCAN3, and SCAN6), and data is written. That is, for R and B pixels, the basic unit of the subfield is composed of four subfields (SF1 to SF4). The G pixel is selected as indicated by broken lines (SCAN4 and SCAN5) in addition to the solid line, and data is written therein. That is, for the G pixel, the basic unit of the subfield is composed of 6 subfields (SF1G to SF6G).

In this example, if only the G pixel is not scanned, the number of subfields is four for SF1 to SF4 for all color pixels. Under this condition, in order to reduce the luminance of G to half of R and B, for example, SF4 is always turned off in the G pixel. Then, the number of subfields that can be used for gradation expression is three. In the subfield driving method, theoretically, 2 ^k gradation representations are possible (k is the number of subfields). Therefore, if the number of subfields that can be used for gradation expression is reduced by one, theoretically, the gradation expression ability is halved. On the other hand, if only scanning of G pixels is used, it is possible to suppress a decrease in gradation expression capability as described below.

  FIG. 9 is a diagram illustrating a timing chart of the scanning line driving circuit 130. In this example, only signals corresponding to the scanning lines 112 in the first to fourth rows are shown. The clock signal CKY is a signal that alternately switches between the H level and the L level. The timing of switching between the H level and the L level indicates the start of the clock. The enable signals ENB1 to ENB6 are signals indicating addresses to be used in one clock. The period during which the enable signal is at the H level indicates the address to be used. For example, in the first clock and the second clock, the enable signal ENB1 is at the H level at the first address. Looking at the same enable signal, the address that is at the H level moves by one address every two clocks. For example, for the enable signal ENB1, the addresses at the H level are the first address, the first address, the sixth address, the sixth address, the fifth address, the fifth address, the fourth address, and the fourth address in order from the first clock. Address, address 3, address 3, address 2, address 2, address 1, address 1, address 6, address, and so on. Further, when looking at the same clock, the address that is at the H level differs depending on the enable signal. For example, for the first clock, the addresses at which the enable signals ENB1 to ENB6 are at the H level are the first address to the sixth address, respectively.

  Signals SR1 to SR4 are signals to which the start pulse signal SPY is transferred. When start pulse signal SPY is not input (at the L level), signals SR1 to SR4 are at the H level. When the start pulse signal is input, the L level state is sequentially transferred from the signal SR1. Of the clocks in which the signal SRi is at L level, the scanning signal Gi is at H level at the address where the corresponding enable signal is at H level. For example, when the start pulse signal SPY is input in the first clock, the signal SR1 becomes L level. Since the signal SR1 is at the L level in the first clock and the enable signal ENB1 is at the H level at the first address at this time, the scanning signal G1 is at the H level at the first address. Since the signal SR2 is at the L level in the second clock and the enable signal ENB1 is at the H level at the first address at this time, the scanning signal G2 is at the H level at the first address. Since the signal SR3 is at the L level in the third clock and the enable signal ENB2 is at the H level at the first address at this time, the scanning signal G3 is at the H level at the first address. Signals after the scanning signal G4 sequentially become H level at the first address.

  In another example, when the start pulse signal SPY is input in the fifth clock, the signal SR1 becomes L level. Since the signal SR1 is at the L level at the fifth clock and the enable signal ENB1 is at the H level at the fifth address at this time, the scanning signal G1 is at the H level at the fifth address. Signals after the scanning signal G2 sequentially become H level at the fifth address.

  As already described, the scanning line driving circuit 130 can parallel a (six in this example) scanning. When scanning using the first address, the start pulse signal SPY may be input at a clock at which the enable signal corresponding to the first row (the enable signal ENB1 in this example) is at the H level at the first address.

  The mode signal MODE is a signal indicating the scanning mode of the scanning line 112. The scanning mode includes two modes, a first mode and a second mode. The first mode is a mode for sequentially selecting all the scanning lines. The L level mode signal MODE indicates the first mode. That is, the description so far is the description of the first mode.

  The second mode is a mode in which only a specific scanning line (in this example, the scanning line 112 corresponding to the G pixel) is sequentially selected. The H level mode signal MODE indicates the second mode. The H level mode signal MODE is input at the same clock as the start pulse signal SPY for starting the scan in the second mode. In the example of FIG. 9, when the start pulse signal SPY is input at the 15th clock and the signal SR1 is at the L level, the H level mode signal MODE indicating the second mode is input. The H level mode signal MODE is sequentially transferred from the LAT 1 as an H level signal.

  The odd-numbered output circuits 135 output a selection signal regardless of the signal LAT. Therefore, the scanning signal of the odd-numbered row becomes H level according to the enable signal ENB corresponding to the signal SRi regardless of the signal LAT. On the other hand, when the signal LATi is at the H level (that is, when the mode signal MODE is at the H level), the even row scanning signals are at the L level regardless of the signal SRi. For example, the scanning signals G1 and G3 become H level at the 15th clock and the 17th clock, respectively, but the scanning signals G2 and G4 remain at the L level at the 16th clock and the 18th clock.

  When scanning SCAN1, SCAN2, SCAN3, and SCAN6 in FIG. 8, an L-level mode signal MODE may be input at a clock for inputting a start pulse signal. When scanning with SCAN4 and SCAN5, an H level mode signal MODE may be input in a clock for inputting a start pulse signal.

  In the example of FIG. 9, the signals LAT <b> 1 to LAT <b> 4 remain at the H level in the clock after the H level mode signal MODE is input and transferred. However, if the mode signal MODE is L level when a new start pulse signal SPY is next input, the signals LAT1 to LAT4 are sequentially reset to L level.

  As described above, according to the present embodiment, only the scanning line 112 corresponding to the G pixel can be scanned. Thereby, the number of subfields of the G pixel, the R pixel, and the B pixel can be made different. For example, when the luminance of the G pixel is half that of the R pixel and the B pixel, gradation can be expressed using five subfields SF1G to SF5G even if SF6G is always turned off. That is, in the case of using the subfield method in an electro-optic device having Bayer-arranged pixels, a decrease in gradation expression capability is suppressed as compared to when all of the R pixel, G pixel, and B pixel are scanned each time. can do.

  In this example, the video processing circuit 20 outputs data corresponding to the subfield codes of the R pixel, the G pixel, and the B pixel in synchronization with the scans of SCAN1, SCAN2, SCAN3, and SCAN6. Output to. In addition, the video processing circuit 20 outputs data corresponding to the SF4G and SF5G subfield codes of the G pixel to the data line driving circuit 140 in synchronization with the scans of SCAN4 and SCAN5.

2. Modifications The present invention is not limited to the above-described embodiment, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

2-1. Modification 1
FIG. 10 is a diagram illustrating a configuration of the scanning line driving circuit 130 according to the first modification. The scanning line driving circuit 130 described in FIG. 5 sequentially selects the scanning lines 112 in the order from the first row to the (m + 1) th row. However, the scanning line driving circuit 130 according to the first modification changes the scanning direction to the first direction. It is possible to switch between the direction from the first row to the (m + 1) th row and the direction from the (m + 1) th row to the first row.

  The scanning line driving circuit 130 according to the first modification includes a switch circuit 136 and a switch circuit 137 in addition to the configuration of FIG. The switch circuit 136 is a circuit for switching the scanning direction in accordance with the direction signal DIR and the direction signal DIRB. The direction signal DIRB is an inverted signal of the direction signal DIR. The switch circuit 136 includes a switch 1361 and a switch 1362. Switch 1361 and switch 1362 are transmission gates. The switch 1361 is a switch that is turned on when the direction signal DIR is at the L level. The switch 1362 is a switch that is turned on when the direction signal DIR is at the H level.

  The switch circuit 136 is provided in (m + 2) stages with respect to the (m + 1) stage shift circuit 1311. The start pulse signal SPY is input to the first-stage switch 1362 and the (m + 2) -th switch 1361. When the direction signal DIR is at the H level, the first-stage switch 1362 is turned on, and the (m + 2) -th stage switch 1361 is turned off. Therefore, the start pulse signal SPY is transferred from the first stage toward the (m + 1) th stage. That is, the scanning line 112 is scanned from the first row to the (m + 1) th row. On the other hand, when the direction signal DIR is at the L level, the first-stage switch 1362 is turned off and the (m + 2) -th stage switch 1361 is turned on. Therefore, the start pulse signal SPY is transferred from the (m + 1) th stage toward the first stage. That is, the scanning line 112 is scanned from the (m + 1) th row toward the first row.

  Similarly to the switch circuit 136, the switch circuit 137 is provided in (m + 2) stages. The switch circuit 137 includes a switch 1371 and a switch 1372. Switch 1371 and switch 1372 are transmission gates. The mode signal MODE is transferred from the first stage to the (m + 1) th stage when the direction signal DIR is at the H level. That is, the scanning line 112 is scanned from the first row to the (m + 1) th row. When the direction signal DIR is at L level, the mode signal MODE is transferred from the (m + 1) th stage toward the first stage. That is, the scanning line 112 is scanned from the (m + 1) th row toward the first row.

  Thus, according to the first modification, the scanning direction of the scanning line 112 can be switched using the direction signal DIR.

2-2. Modification 2
Specific examples of the Bayer arrangement are not limited to those described in the embodiment. In the Bayer arrangement, the pixels of the first color, the second color, and the third color are arranged with 4 pixels in 2 rows and 2 columns as a basic unit. The basic unit includes two pixels of the first color and one pixel of the second color and one of the third color. The pixels of the first color are arranged obliquely in the basic unit. In the embodiment, the example in which the first color is G, the second color is R, and the third color is B has been described, but each color is not limited to this.

2-3. Modification 3
The arrangement of the pixels 111 in the electro-optical device 10 is not limited to that illustrated in FIG. In the arrangement of FIG. 2, the number of loads connected to the scanning lines 112 in the first row (TFT 116 and pixel electrode 118) and the scanning lines 112 in the (m + 1) th row is the second row. ~ Half of the load connected to the m-th row scanning line 112. Thus, when the number of loads is different, the gradation may be adversely affected. In order to avoid this adverse effect, dummy pixels may be connected to the scanning lines 112 of the first row and the (m + 1) th row. A dummy pixel is a pixel that has the same structure as the pixel 111 but does not contribute to image display. By reducing the load difference by the dummy pixel, it is possible to reduce the adverse effect on the gradation.

2-4. Other Modifications The electronic device according to the present invention is not limited to a projector. Television, viewfinder type / monitor direct view type video tape recorder, car navigation device, pager, electronic notebook, calculator, word processor, workstation, video phone, POS terminal, digital still camera, mobile phone, equipment with touch panel, etc. The present invention may be used.

  The configuration of the electro-optical device 10 is not limited to that described in the embodiment. For example, the electro-optical element used in the electro-optical device 10 is not limited to the liquid crystal element 120. Instead of the liquid crystal element 120, another electro-optical element such as an organic EL (Electro-Luminescence) element may be used. Further, the electro-optical device 10 may include the image processing circuit 20 described in the embodiment.

  The parameters described in the embodiment (for example, the number of subfields, the frame speed, the number of pixels, etc.) and the signal polarity and level are merely examples, and the present invention is not limited to this.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 10 ... Electro-optical apparatus, 20 ... Image processing circuit, 100 ... Liquid crystal panel, 101 ... Display area, 105 ... Liquid crystal layer, 108 ... Common electrode, 111 ... Pixel, 112 ... Scanning line, 114 ... Data line 116 ... TFT, 118 ... Pixel electrode, 120 ... Liquid crystal element, 125 ... Capacitor element, 130 ... Scanning line drive circuit, 131 ... Shift register, 132 ... Logic circuit, 133 ... Logic circuit, 134 ... Shift register, 135 ... Output Circuit, 136 ... Switch circuit, 137 ... Switch circuit, 140 ... Data line driving circuit, 141 ... Shift register, 142 ... First latch circuit, 143 ... Second latch circuit, 1311 ... Shift circuit, 1341 ... Shift circuit, 1361 ... Switch, 1362 ... Switch, 1371 ... Switch, 1372 ... Switch, 13111 ... Clocked Nbata, 13112 ... clocked inverter, 13113 ... inverter

Claims (7)

A plurality of pixels in which a first color pixel, a second color pixel, and a third color pixel are arranged in a Bayer arrangement;
A first scanning line group including a plurality of scanning lines for selecting the pixel of the first color among the plurality of pixels;
A second scanning line group including a plurality of scanning lines for selecting the pixels of the second color and the third color among the plurality of pixels;
When the mode signal indicates the first mode, one scanning line is sequentially selected from the first scanning line group and the second scanning line group, and when the mode signal indicates the second mode, And a scanning line driving circuit that sequentially selects one scanning line from the first scanning line group. A data line driving circuit configured to apply a voltage to the plurality of pixels according to a subfield code that is converted from image data indicating a gradation value of the pixel and indicates a permutation of on or off of the plurality of subfields;
2. The electro-optical device according to claim 1, wherein the number of subfields in the pixels of the first color is different from the number of subfields in the pixels of the second color and the third color. The plurality of pixels are arranged in a matrix of m rows and n columns,
The first scanning line group and the second scanning line group have (m + 1) scanning lines in total,
The scanning lines of the first scanning line group and the scanning lines of the second scanning line group are alternately arranged,
A start pulse signal is transferred step by step, and (m + 1) first shift registers corresponding to the (m + 1) scan lines;
Transferring the mode signal step by step, and (m + 1) second shift registers corresponding to the (m + 1) scanning lines;
A signal corresponding to the start pulse signal is output to the scan line of the first scan line group, and a signal corresponding to the logical product of the start pulse signal and the mode signal is output to the scan line of the second scan line group. The electro-optical device according to claim 1, further comprising: an output circuit that outputs a signal. The first shift register and the second shift register transfer the start pulse signal and the mode signal to a subsequent stage at a timing according to a clock signal,
A first enable signal line for transmitting a first enable signal for selecting one sub-period among a plurality of sub-periods obtained by dividing the unit period into a plurality of unit periods indicated by the clock signal;
A second enable signal line for transmitting a second enable signal for selecting a sub period different from the one sub period in the unit period;
The output circuit outputs a signal corresponding to a logical product of the start pulse signal and the first enable signal to the first scan line of the first scan line group, and the first scan line adjacent to the first scan line. A signal corresponding to a logical product of the start pulse signal, the mode signal, and the first enable signal is output to the second scanning line of the two scanning line groups,
A signal corresponding to the logical product of the start pulse signal and the second enable signal is output to the third scanning line of the first scanning line group, and the second scanning line group adjacent to the third scanning line is output. The electro-optical device according to claim 3, wherein a signal corresponding to a logical product of the start pulse signal, the mode signal, and the second enable signal is output to the fourth scanning line. The first shift register transfers the start pulse signal in a direction corresponding to a direction signal indicating a signal transfer direction;
The electro-optical device according to claim 3, wherein the second shift register transfers the mode signal in a direction corresponding to the direction signal.   An electronic apparatus comprising the electro-optical device according to claim 1. A plurality of pixels in which a first color pixel, a second color pixel, and a third color pixel are arranged in a Bayer arrangement, and a plurality of scanning lines for selecting the first color pixel among the plurality of pixels. An electro-optical device control method comprising: a first scanning line group including: a second scanning line group including a plurality of scanning lines for selecting the pixels of the second color and the third color among the plurality of pixels. Because
When the mode signal indicates the first mode, one scanning line is sequentially selected from the first scanning line group and the second scanning line group, and when the mode signal indicates the second mode, A control method comprising: sequentially selecting one scanning line from the first scanning line group.

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