JPH11102174A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a dot inversion driving for a liquid crystal display device by driving respective signal lines with voltages having polarities of one side of either a positive polarity or a negative polarity always during the period of frame scanning to reduce power consumption. SOLUTION: During the period of frame scanning, respective signal liens X1 -X4 are always driven with voltages having polarities of one side of either a positive polarity or a negative polarity. For example, a signal line X1 being at the left end is always driven with a voltage having a positive polarity by a first channel driving part CR1 and it is never driven with a voltage having a negative polarity. Moreover, a signal line X2 being adjacent to it is always driven with a voltage having the negative polarity while being alternately connected to first and second channel driving parts CR1 , CR2 and it is never driven with the voltage having the positive polarity. In next frame scanning, the same operations are performed except that a second output mode and a first output mode are respectively selected for the horizontal scanning period of odd numbered rows and for that period of even numbered rows. Thus, polarities of gradation voltages to be written to pixel electrodes of respective pixels are inverted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0010]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) type liquid crystal display (T
FT-LCD).

[0020]

2. Description of the Related Art FIG. 11 schematically shows a configuration of an active matrix type full-color TFT-LCD. The conventional TFT-LCD is configured such that a plurality of gate lines Y1, Y2,... And a plurality of signal lines X1, X2,. It has a liquid crystal panel 100. And
As peripheral circuits of the liquid crystal panel 100, gate lines Y1,
Gate lines drivers G1, G2,... Connected in parallel for driving Y2,.
, A source line driver S1, S2,... For controlling the operation of each unit, and an image signal processing circuit for performing required signal processing on an image signal to be displayed 104 and a gradation voltage generation circuit 106 for generating multi-gradation voltages for realizing full color (multi-gradation display).

The image signal processing circuit 104 supplies digital image data DX representing the gradation of display of each pixel to each signal line driver S1, S2,. For example, in the case of 64 gradations, 6-bit image data D for each of R, G, and B pixels
X is output from the image signal processing circuit 104 to each signal line driver S1,
S2, ... The controller 102 sends various control signals or timing signals synchronized with the horizontal synchronizing signal HS and the vertical synchronizing signal VS to each of the gate line drivers G1, G
, And the signal line drivers S1, S2,. The gray scale voltage generation circuit 106 generates multi-stage gray scale voltages having voltage levels corresponding to multiple gray scales of display based on the V (voltage) -T (transmittance) characteristics of the liquid crystal panel 100, for each signal line driver. Are supplied to S1, S2,.

FIG. 12 shows the internal configuration (for one pixel) of the liquid crystal panel 100. Two glass substrates 110 and 112
The liquid crystal 114 is sealed or filled in between. On the inner surface of one glass substrate 110, each gate line Yi
(Not shown) and one pixel electrode Pi, j made of a transparent conductive film near the intersection of each signal line Xj (not shown).
A plurality of thin film transistors TFTi, j are formed, the pixel electrode Pi, j is connected to the signal line Xj via the TFTi, j, and the gate electrode Tg of the TFTi, j is connected to the gate line Yi. The inner surface of the other glass substrate 112 has R
An opposing (common) electrode 116 made of a transparent conductive film is formed on one surface via color filters 115 for (red), G (green), and B (blue). Deflection plates 118 and 120 are provided on the outer surfaces of both glass substrates 110 and 112 such that their deflection axes are parallel or perpendicular to each other.

In FIG. 12, Ts is a source electrode, Td is a drain electrode, 124 is a semiconductor layer, 126 is a protective film, 128 is a gate insulating film, and 130 is a black matrix.

FIG. 13 shows a circuit configuration in the liquid crystal panel 100. Each pixel electrode Pi, j, the counter electrode 116, and the liquid crystal 114 interposed therebetween constitute a signal storage capacitor Cs for one pixel. In each column, all the pixel electrodes P
, Are respectively connected to the signal lines X of the respective columns via the corresponding thin film transistors TFT1, j, TFT2, j,.
j is electrically connected in common. In each row, all the thin film transistors TFTi, 1 and TFTi, 2 in that row
,... Are electrically connected to a common gate line Yi.

The gate lines Y1, Y2,... Are normally selected line by line by line scanning within one frame period (1V) by the gate line drivers G1, G2,.

When the gate line Yi in the i-th row is driven, all the thin-film transistors TFTi, 1, TFTi, 2,... In the i-th row connected to the gate line Yi are turned on. In synchronization with this, the signal line drivers S1, S2,.
Analog gray scale voltages are output to all the pixels on the row, and these gray scale voltages are output from the signal lines X1, X2,... And the thin-film transistors TFTi, 1, TFTi,
,..., The corresponding pixel electrodes Pi, 1, P
applied to i, 2, ... Thereafter, in the next (i + 1) -th row, the gate line Yi + 1 is selected, and the same operation as described above is performed. In row i, the thin film transistors TFTi,
When the TFTs 1, 2,... Are turned off, the charge written to each pixel loses its escape route, and each of the electrodes Pi, 1, P
The gradation voltages i, 2,... are held until the next selection time.

As described above, the gradation voltage is applied to each pixel electrode in one frame cycle. However, in the liquid crystal display, in order to prevent the deterioration of the liquid crystal molecules, the voltage is not applied to the liquid crystal in an AC form. must not. TFT-LCD
, There is a common constant driving method as a method of applying an AC voltage to the liquid crystal.

In the common constant driving method, as shown in FIG. 14, a voltage having a positive polarity and a negative polarity with respect to the counter electrode voltage (constant value) are applied to the pixel electrode while the voltage of the counter electrode is fixed at a constant level. Are alternately applied. This driving method enables dot inversion (complete dot inversion) in both X and Y directions, and is excellent in display quality.

FIG. 15 shows a complete dot inversion pattern. As shown in the figure, every time the frame F is switched, (F
n, Fn + 1) and the polarity of the gradation voltage written to each pixel in the liquid crystal panel 100 is alternately inverted. Then, the polarity of each pixel is reversed every line in the Y direction, and X
In the direction, the polarity is inverted for each pixel.

In the common constant driving method, since the positive and negative gradation voltages can be simultaneously selected at an arbitrary point in time from the viewpoint of the counter electrode voltage, as shown in FIG. It is possible to alternately invert the polarity for each pixel not only in the frame period and the Y direction but also in the X direction. In this way, by inverting the polarity of the gray scale voltage between adjacent signal lines or pixel electrodes, currents flowing through the counter electrodes and the like at the time of writing cancel each other out, thereby suppressing a decrease in display quality.

[0130]

In order to realize the complete dot inversion as described above, in the conventional TFT-LCD, each signal line Xj is set to a positive polarity by one line (one horizontal scanning period) by a signal line driver S. And the negative voltage.

For example, in the frame Fn of FIG. 15A, focusing on the signal line X1 in the first column, when the gate line Y1 in the first row is selected (the gradation voltage is applied to the corresponding pixel electrode P1,1). Is written), a positive voltage is applied, and a charging current flows on the signal line X1. However, when the gate line Y2 in the second row is selected (when a gradation voltage is written to the corresponding pixel electrode P2,1), the signal line X1 is driven to a negative voltage, and the discharge current on the signal line X1 is reduced. Flows. Then, when the gate line Y3 of the third row is selected (the corresponding pixel electrode P3,1).
When a gray scale voltage is written to the pixel line), the signal line X1 is driven to a positive voltage, and a charging current flows on the signal line X1.

Thus, as schematically shown in FIG. 16 (when the gradation is constant at a high value), the voltage alternates between the positive electrode and the negative electrode every one line (one horizontal scanning period) on the signal line X1. And a charge or discharge current flows with the polarity inversion. On the other signal lines X2, X3,..., The same voltage polarity inversion and charge / discharge as described above are repeated for each line.

As described above, since each signal line Xj must be alternately driven to the positive electrode and the negative electrode while charging or discharging for each line, the load on the signal line driver S is large and a large amount of power is consumed. I was

The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide a liquid crystal display device capable of performing dot inversion driving by greatly reducing power consumption.

[0180]

In order to achieve the above object, a liquid crystal display device of the present invention comprises a liquid crystal filled between a plurality of pixel electrodes arranged in a matrix and one counter electrode. Odd-numbered pixel electrodes in a column are electrically connected to a first signal line via a corresponding thin film transistor, and even-numbered pixel electrodes are electrically connected to a second signal line via a corresponding thin film transistor. A liquid crystal panel in which the control terminals of all the thin film transistors are electrically connected to a common gate line in each row; a unit for applying a constant counter electrode voltage to the counter electrode; A gate line driving unit that is activated for each row by scanning, and a corresponding pixel electrode of each column is activated when an odd-numbered gate line is activated in each frame scan. And applying a gradation voltage having a voltage level corresponding to the display gradation and having one polarity relatively to the counter electrode voltage via the first signal line, and When a line is activated, a gray level having a voltage level corresponding to a desired display gray level for a corresponding pixel electrode in each column and having the other polarity relatively to the counter electrode voltage Signal line driving means for applying a voltage via the second signal line, and the polarity of the gradation voltage output from the signal line driving means on the first and second signal lines is alternately inverted for each frame And a polarity switching means.

As one embodiment of the liquid crystal display device of the present invention, the pixel electrodes in two adjacent columns share the first signal line for one column and the second signal line for the other column. .

In another embodiment of the liquid crystal display device of the present invention, the first and second signal lines dedicated to the pixel electrodes of each pair of adjacent columns are provided.

As another embodiment of the liquid crystal display device of the present invention, the signal line driving means has a channel driving section corresponding to the pixel electrode of each column, and the channel driving section of each column is provided every one horizontal scanning period. A grayscale voltage of a positive polarity and a grayscale voltage of a negative polarity are output, and are alternately switched and connected to the first signal line and the second signal line every horizontal scanning period.

Further, as another embodiment of the liquid crystal display device of the present invention, the signal line driving means has a channel driving unit connected to each signal line in a one-to-one relationship, and each channel driving unit is connected to each row. A first output mode in which a positive polarity gray scale voltage is output each time the gate line is activated, and a second output mode in which a negative polarity gray scale voltage is output each time the gate line of each row is activated. The output mode and the output mode are alternately switched for each frame.

Further, in the liquid crystal panel of the present invention, a liquid crystal is filled between a plurality of pixel electrodes arranged in a matrix and one counter electrode, and an odd-numbered pixel electrode in each column has a thin film transistor corresponding thereto. And the even-numbered pixel electrodes are electrically connected to the second signal lines via the corresponding thin film transistors, and the control terminals of all the thin film transistors in each row are electrically connected to the first signal lines via the corresponding thin film transistors. It has a configuration electrically connected to a common gate line.

[0240]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a circuit configuration of a TFT liquid crystal panel according to one embodiment of the present invention. This liquid crystal panel 10 has basically the same structure as that shown in FIG. 12 for each pixel, and the pixel electrodes Pi, 1,.
The electrical connection between Pi, 2, Pi, 3... And the gate line Y is the same as that of the conventional panel structure (FIG. 13), but the pixel electrodes P1, j, P2, j, P3 in each column are arranged. , j ……
And the signal line X are different from the conventional panel in electrical connection.

That is, the pixel electrodes P1, j, P2, j of each column
, P3, j... Are assigned a pair of left and right signal lines Xj, Xj + 1, and odd-numbered pixel electrodes P1, j, P3, j, P5, j.
.. Represent the corresponding thin film transistors TFT1, j, T
Are electrically connected to the left (first) signal line Xj via FT3, j, TFT5, j..., And the even-numbered pixel electrodes P2, j,.
Are electrically connected to the right (second) signal line Xj + 1 via the corresponding thin film transistors TFT2, j, TFT4, j, TFT6, j.

In each column, in each odd-numbered pixel (an odd row in the entire panel), each thin film transistor TFT
Are arranged closer to the left (first) signal line Xj, whereas the thin-film transistors T are arranged in even-numbered pixels (even-numbered rows in the entire panel).
FT2, j, TFT4, j, TFT6, j... Are arranged closer to the right (second) signal line Xj + 1.

In this liquid crystal panel 10, the number of pixel columns (X
Assuming that the number of dots in the direction is n, (n + 1) signal lines X1 to Xn + 1 are provided. Among them, the leftmost signal line X1
Are the odd-numbered pixel electrodes P1,1, P3,1, P5,1 in the first column.
, And the rightmost signal line Xn + 1 is connected to the nth
It is electrically connected only to the even-numbered pixel electrodes P2, n, P4, n, P6, n... In the column. Each intermediate signal line Xj (X2 to X
n) is an even-numbered pixel electrode P2, j- in the left column.
, P4, j-1, P6, j-1... Are electrically connected as right (second) signal lines, and the odd-numbered pixel electrodes P1, j, P3, j in the column on the right thereof are connected. , P5, j... Are electrically connected as left (first) signal lines.

When the liquid crystal panel 10 is driven by the common constant driving method, a constant value, for example, a common electrode voltage VCOM of 5 volts is applied to the common electrode 12.

FIG. 2 shows a TFT according to an embodiment of the present invention.
2 shows a configuration of a main part of the LCD. This TFT-LCD uses the liquid crystal panel 10 having the above configuration. Gate line driver G
May be a conventional one and a controller (not shown)
, The gate lines Y1, Y2,... Of the liquid crystal panel 10 are selected and activated one by one by line-sequential scanning within one frame period.

In the signal line driver S of the TFT-LCD, the output terminal of the channel drive section CRj assigned to each column (channel) of the liquid crystal panel 10 is connected to the liquid crystal through a pair (left and right) of changeover switches SWja and SWjb. The pixel electrodes P1, j, P2, j,.
, A pair of (left and right) signal lines Xj, X
It is electrically connected to j + 1. The data register unit GR
Image data DX1 and DX2 indicating the display gradation of the corresponding pixel of each column from an image signal processing unit (not shown) for each line
.. Are distributed to the respective channel drivers CR1, CR2,.

Switch for each row [SWja, SWjb]
Is configured to alternately switch between a first (left) position indicated by a solid line and a second (right) position indicated by a dotted line every line (horizontal scanning period) under the control of the controller. . When each switch is switched to the first (left) position, the output terminal of the channel driver CRj is connected to the left signal line Xj by the left switch SWja. When the switch is switched to the second (right) position, the output terminal of the channel driver CRj is connected to the right signal line Xj + 1 by the right switch SWjb.

FIG. 3 shows a circuit configuration of the channel driving section CRj for one channel. The register 14j takes in the image data DXj of one pixel assigned to each corresponding channel from the data register unit GR. Then, in response to the data latch signal TP from the controller synchronized with the horizontal synchronizing signal, the data latch circuit 16j latches the image data DXj for one pixel.

An output terminal of the data latch circuit 16j is connected to an input terminal of a DA converter 20j via a level shifter 18j. The level shifter 18j raises the logic voltage of image data (for example, 5 volts) to a higher voltage (for example, 10 volts) so that circuit elements in the DA converter 20j can handle both positive and negative gradation voltages by the common constant driving method. ).

The DA converter 20j supplies all (K) gray-scale voltages V1 to V from the gray-scale voltage generation circuit 24.
K and all (K) gradation voltages V'K to V'1 of the negative polarity are supplied. The gray scale voltage generating circuit 24 is composed of, for example, a resistive voltage dividing circuit, and is connected to an appropriate portion so as to obtain each gray scale voltage having a voltage level corresponding to each display gray scale according to the VT characteristic of the liquid crystal panel 10. A reference voltage v for correction is supplied to a point (node).

For example, in the common constant driving method, the voltage VCOM of the common electrode is fixed to 5 volts, and the positive gradation voltage (5 to 10 volts) and the negative gradation voltage (5 to 0 volts) are applied to each pixel electrode. Volts) are applied alternately, the maximum grayscale voltage VK of the positive polarity is set to the value closest to 10 volts, the maximum grayscale voltage V'K of the negative polarity is set to the value closest to 0 volts, The minimum gray scale voltages V1 and V'1 are set near 5 volts.

The DA converter 20j receives an AC signal or an inversion control signal R for inverting the polarity of the gradation voltage every line (horizontal scanning period) from the controller.
V is given. The inversion control signal RV is given by inverting the logic values of the odd-numbered channel driving units CR1, CR3,... And the even-numbered channel driving units CR2, CR4,.

The DA converter 20j includes the level shifter 1
8j, the image data DXj for one pixel is decoded, and grayscale voltages Vx and V'x having a voltage level corresponding to the display grayscale represented by the image data are first selected, and then the logic of the inversion control signal RV is determined. The gradation voltages Vx, V'x according to the values
Is output. For example, when RV is at an H level, a positive gradation voltage Vx is output, and when RV is at an L level, a negative gradation voltage V'x is output.
Is output.

As described above, the DA converter 20j is substantially a decoder circuit, but is a DA converter in the sense of converting digital data into an analog voltage.

The output amplifier 22j is composed of a voltage follower of an operational amplifier having an impedance conversion function, and operates in a sink state for a positive voltage and operates in a source state for a negative voltage. ing.

In the signal line driver S of this embodiment, in order to perform complete dot inversion driving, odd-numbered (column) channel driving units CR1, CR3,... Are controlled by the inversion control signal RV from the controller as described above. A first output mode in which the grayscale voltages of the positive polarity are output and the even-numbered (column) channel drivers CR2, CR4... Output the grayscale voltages of the negative polarity; CR
The second output mode in which 1, CR3... Outputs a negative gradation voltage and the even-numbered (column) channel driving units CR2, CR4. It is alternately repeated every time.

Next, the operation of this TFT-LCD will be described.

First, when the gate line Y1 of the first row is activated, the changeover switches [SW1a, SW1b],
[SW2a, SW2b],... Are switched to the first (left) position shown by the solid line in FIG. To the signal line Xj. One mode, for example, the first mode is selected by the control of the inversion control signal RV.

Thus, the positive gradation voltages from the odd-numbered channel driving units CR1, CR3,... Are supplied to the left signal lines X1, X3,... Via the left switches SW1a, SW3a,. And the corresponding thin film transistors TF in the first row in the ON state from the signal lines X1, X3.
The corresponding pixel electrodes P1,1 and P are connected via T1,1 and TFT1,3.
1,3 ... applied.

On the other hand, each even-numbered channel driver CR
Are supplied to the left signal lines X2, X4,... Via the left switches SW2a, SW4a... In the corresponding columns, and are turned on from the respective signal lines X2, X4. Each corresponding thin film transistor TFT1,2 in the first row
, TFT1,4,..., The corresponding pixel electrodes P1,2, P1,4,.
Is applied to

In this manner, in the first row, the positive gradation voltage is written to the odd-numbered (column) pixel electrodes P1,1, P1,3,..., And the even-numbered (column) pixel electrodes P1, 2, P1,
4 is written with a negative gradation voltage.

Next, when the gate line Y2 in the second row is activated, the changeover switches [SW1a, SW1b],
[SW2a, SW2b],... Are switched to the second (right) position shown by the dotted line in FIG. To the signal line Xj + 1. The second mode is selected this time by controlling the inversion control signal RV.

Thus, the negative gradation voltages from the odd-numbered channel drive units CR1, CR3,... Are supplied to the right signal lines X2, X4,... Via the right switches SW1b, SW3b,. And the corresponding thin film transistors TF in the first row in the ON state from the signal lines X2, X4.
The corresponding pixel electrodes P2,1, P2 through T2,1, TFT2,3.
Written in 2,3….

On the other hand, each even-numbered channel driver CR
Are supplied to the right signal lines X3, X5,... Via the right switches SW2b, SW4b... In each corresponding column, and are turned on from the respective signal lines X3, X5. Each corresponding thin film transistor TFT2,2 in the second row
, TFT2,4,..., The corresponding pixel electrodes P2,2, P2,4,.
Is written to.

In the second row, the negative gradation voltage is written to the odd-numbered column pixel electrodes P2,1, P2,3,..., And the positive gradation voltage is written to the even-numbered pixel electrodes P2,2, P2,4,. Is written.

Next, when the gate line Y3 in the third row is activated, the changeover switches [SW1a, SW1b], [SW2a, SW2b],... In each column are activated as in the case of the first row. FIG.
And the output terminal of each channel driving unit CRj is connected to the left signal line Xj of each column via the switch SWja on the left of each column. The first mode is selected by controlling the inversion control signal RV.

Therefore, in the third row, a positive gradation voltage is written to the odd-numbered column pixel electrodes P3,1, P3,3,. Is written.

[0531] Thereafter, the same operation as that of the first row or the second row as described above is repeated in the fourth row and thereafter, depending on whether the row is an odd row or an even row. Thus, the dot inversion drive is performed in the X direction and the Y direction.

During the frame scanning as described above, each of the signal lines X1, X2, X3,... Is always driven by a voltage of either the positive polarity or the negative polarity. For example, the left end signal line X1 is always driven by the first channel driver CR1 at a positive voltage, and is not driven by a negative voltage. The adjacent signal line X2 is alternately connected to the first and second channel drivers CR1 and CR2,
It is always driven with a negative voltage and is not driven with a positive voltage.

In the next frame scanning, the second output mode is selected in the horizontal scanning period of the odd-numbered row, and the first output mode is selected in the horizontal scanning period of the even-numbered row, under the control of the inversion control signal RV. Except for this, the same operation as described above is performed. Therefore, the polarity of the gradation voltage written to the pixel electrode of each pixel is inverted.

In this case, each of the signal lines X1, X2, X3,... Has a polarity opposite to that of the previous frame, and is always driven by a voltage of either the positive polarity or the negative polarity. For example, the leftmost signal line X1 is always driven by the first channel driving unit CR1 with a negative voltage. Further, the second signal line X2 is always driven with a positive voltage and is not driven with a negative voltage, while being alternately connected to the first and second channel driving units CR1 and CR2.

Thus, as schematically shown in FIG. 4 (when the gradation is constant at a high value), a considerable charge or discharge current only temporarily flows on each signal line X during frame switching. Since the voltages are maintained at the same polarity during the frame scanning period, a charging / discharging current that does not cause a problem flows.

According to each channel drive section CRj, 1
A positive voltage and a negative voltage are alternately output for each line. The positive voltage is supplied to a signal line (for example, Xj) dedicated to the positive electrode through the frame scanning period, and the negative voltage is supplied to the frame scanning period during the frame scanning period. Since the power is supplied to the signal line (Xj + 1) dedicated to the negative electrode through this, there is no need to invert or swing the signal line voltage between the positive electrode and the negative electrode for each line as in the related art.

Therefore, in each channel driving unit CRj, particularly in the output amplifier 22j, the circuit scale can be reduced, and the power consumption can be significantly reduced.

FIG. 5 shows a TF according to a second embodiment of the present invention.
1 shows a configuration of a T-LCD. In the second embodiment, the signal line driver S is modified in the first embodiment. That is, in this embodiment, the channel driving unit CR
And the signal lines X1 to Xn + 1 of the liquid crystal panel 10
The changeover switch SW is omitted by directly connecting the output terminals of the channel driving units CR1 to CRn + 1 one by one.

In this embodiment, the data shift circuit 26 is provided at the preceding stage of the data register portion GR of the signal line driver S.
Is provided. As shown in FIG. 6, this data shift circuit 26 includes n (n columns) grayscale data DX1 to DX provided by an image signal processing unit (not shown) for each line.
n for the odd-numbered lines, the first to n-th channel driving units C
R1 to CRn, and in even lines, the second to (n)
Data operation is performed so as to be assigned to the channel driving units CR2 to CRn + 1 of (+1).

In FIG. 6, a data invalid period DM * for several clocks is inserted in the horizontal blanking period. The data shift circuit 26 variably controls the length of the data invalid period DM * by a delay function, thereby outputting the gradation data DX1 to DXn through the odd lines and passing the gradation data DX1 to DXn through the even lines. Is shifted (delayed) by a predetermined number of clocks and output.

Referring again to FIG. 5, in this embodiment, each channel driver CR outputs a gradation voltage with either one of the positive polarity and the negative polarity throughout the frame scanning period. More specifically, the odd-numbered channel driving units CR1,
CR3... Continue to output positive gradation voltages, and even-numbered channel driving units CR2, CR4... Continue outputting negative gradation voltages, and odd-numbered channel driving units CR1. , CR3... Continue to output a negative gradation voltage, and the even-numbered channel driving units CR2, CR4
Are alternately switched for each frame. For this,
The inversion control signal RV supplied from the controller to the DA converter of each channel drive unit CR is controlled so that the logical value is inverted every frame.

Next, the operation of the second embodiment will be described.

First, when the gate line Y1 in the first row is activated, the grayscale data DX1 to DXn for one row is converted into the first to n-th rows under the control of the data shift circuit 26 as described above.
To the channel drive units CR1 to CRn. At this time, the right end, that is, the (n + 1) th channel driver CRn +
1 is not given any gradation data. It is assumed that the first output mode is selected during the frame scanning period.

Accordingly, each odd-numbered gradation data DX
The odd-numbered channel driving units C corresponding to 1, DX3.
The positive gradation voltages output from R1, CR3,... Are supplied to corresponding signal lines X1, X3,.
From the corresponding thin film transistor T in the first row in the on state
The corresponding pixel electrodes P1,1,... Via FT1,1, TFT1,3.
P1,3...

[0670] On the other hand, each even-numbered gradation data DX2, DX
4... Corresponding to the even-numbered channel driving units CR2, C
The negative gradation voltages output from R4... Are supplied to the corresponding signal lines X2, X4..., And the corresponding thin film transistors TFT1 in the first row in the ON state from the signal lines X2, X4.
2, the corresponding pixel electrodes P1,2, P1,4 via TFT1,4,.
... are applied.

Thus, in the first row, the positive gradation voltage is written to the odd-numbered (column) pixel electrodes P1,1, P1,3,..., And the even-numbered (column) pixel electrodes P1, 2, P1,
4 is written with a negative gradation voltage.

Next, when the gate line Y2 in the second row is activated, the grayscale data DX1 to DXn for one row is changed to the second to (n + 1) th rows under the control of the data shift circuit 26 as described above. To the channel driving units CR2 to CRn + 1. At this time, no significant gradation data is given to the left end, that is, the first channel drive section CR1.

In this case, each even-numbered channel driver CR2, CR4,... Outputs a negative-polarity gray scale voltage having a voltage level corresponding to the odd-numbered gray scale data DX1, DX3. I do. Then, this negative gradation voltage is supplied to the corresponding signal lines X2, X4,.
Are applied to the corresponding pixel electrodes P2,1, P2,3,... Through the corresponding thin-film transistors TFT2,1, TFT2,3,.

On the other hand, the third and subsequent odd-numbered channel driving units CR3, CR5,... Have positive gradations having voltage levels corresponding to the even-numbered gradation data DX2, DX4,. Output voltage. .. Are supplied to the corresponding signal lines X3, X5,..., And the corresponding thin film transistors TFT2, 2, TFT2, 4,. Are applied to the corresponding pixel electrodes P2,2, P2,4.

As a result, in the second row, a negative gradation voltage is written to the odd-numbered (column) pixel electrodes P2,1, P2,3,..., And the even-numbered (column) pixel electrodes P2,2,. The positive gradation voltage is written to P2,4.

Thereafter, the same operation as that of the first or second row described above is repeated in the third and subsequent rows according to whether the row is an odd row or an even row. In the next frame, the second output mode is selected, the odd-numbered channel driving units CR1, CR3,... Output negative gradation voltages, and the even-numbered channel driving units CR2, CR4,. And outputs a gray scale voltage of the same. Thereby, complete dot inversion is realized.

In this embodiment, as in the first embodiment, the signal lines X1, X2, X3 during the frame scanning period.
Are always driven by a voltage of one of the positive polarity and the negative polarity, and no charge / discharge current flows when the polarity is reversed.
Therefore, the load on the signal line driver S is light and the power consumption is small.

The data shift circuit 26 or a function corresponding thereto can be built in the image signal processing section or the controller.

FIGS. 7 and 8 show another embodiment of the circuit structure in the liquid crystal panel, particularly the wiring structure of the signal line X in the present invention.

In the liquid crystal panel 10 of FIG. 1 described above, except for the signal lines X1 and Xn + 1 at both ends, each signal line Xj is connected to the pixel electrodes [Pj-1, 1, P
j-1,2, Pj-1,3 ...], [Pj, 1, Pj, 2, Pj, 3 ...]
In contrast, the left (first) signal line and the right (second) signal line are also used.

On the other hand, in the panel configurations shown in FIGS. 7 and 8, the pixel electrodes [P1,1, P2,1, P3, P3,
.., P1,2, P2,2, P3,3.
1, X2 are assigned as first and second signal lines, respectively, and pixel electrodes [P1,3, P2,3, P3,
3..., P1,4, P2,4, P3,4.
3, X4 are assigned as the first and second signal lines, respectively. That is, a pair of adjacent columns [first and second
Columns, [third and fourth columns], [fifth and sixth columns]... Are assigned dedicated first and second signal lines.

In each pair of columns, for example, [first and second columns], the first signal line X1 is electrically connected to the pixel electrodes P1,1, P3,1,. Are electrically connected to the pixel electrodes P2,2, P4,2... On the second column side, whereas the second signal line X2 is electrically connected to the pixel electrodes P1,2, P3, P3, Are electrically connected to the pixel electrodes P2,1, P4,1,... On the first column in the even rows.

In the panel configuration of FIG. 7, each signal line X1, X2,
X3 are Y at equal intervals in the X direction as in the panel configuration of FIG.
It is wired linearly in the direction. But in even rows,
Odd-numbered (column) thin film transistors TFT2,1, TFT
Are exceptionally formed on the right side (closer to the second signal line), and the even-numbered (column) thin film transistors TF
T2,2, TFT2,4,... Are connected to the first signal line via wirings that straddle adjacent pixels.

[0810] The panel configuration shown in FIG. 8 comprises a pair of rows [first and second rows], [third and fourth rows] on both sides of the first and second signal lines [X1, X2], [X3, X4]. Column] ... pixels are arranged.
According to this configuration, each signal line X is connected by a relatively short distance wiring.
And each thin film transistor TFT can be electrically connected.

In the panel configuration of FIG. 9, the structure of each pixel is the same pattern, and each pair of signal lines X1, X2, X3... Is connected to each corresponding pixel electrode so as to obtain a required electrical connection relationship. The wires are arranged in a zigzag pattern between the columns.

FIG. 10 shows an example of the configuration of a signal line driver S 'adapted to a liquid crystal panel 10' having a structure as shown in FIGS.

In this signal line driver S ′, the output terminals of the channel drivers CR 1 to CRn + 1 are directly connected to the signal lines X 1 to Xn + 1 of the liquid crystal panel 10 on a one-to-one basis. Each channel driver CR may basically have the same circuit configuration as that of FIG.

[0850] In each pair of columns, however, four change-over switches a, b, c, and d are provided between the data latch circuit 16 and the level shifter circuit 18 in a connection relationship as shown. For example, in the [first and second columns], the changeover switches a and 1 are connected between the data latch circuit 16 (1) in the first column and the level shifter circuits 18 (1) and 18 (2) in the first and second columns. c is provided, and the data latch circuit 16 (1) of the second column is provided.
And the level shifter circuits 18 (1), 1 in the first and second columns
8 (2) are provided with changeover switches b and d.

[0859] In this signal line driver S ', similarly to the configuration example of FIG. 5, the odd-numbered channel drive units CR1 and CR3 are used.
.. Continue to output the positive-polarity gray scale voltage and the even-numbered channel drive units CR2, CR4... Continue to output the negative gray scale voltage, and the odd-numbered channel drive units CR1 and CR1 The second output mode in which CR3 continues to output a negative gradation voltage and the even-numbered channel drive units CR2, CR4 continue outputting a positive gradation voltage is alternately switched every frame. Can be

[0887] For example, in frame scanning in the first output mode, the following operation is performed.

When an odd-numbered line is selected, switches a and d are closed and switches b and c are cut off.
Thereby, for example, in the [first and second columns], the first
The grayscale data DX1 for the first column from the data latch circuit 16 (1) for the column is input to the level shifter 18 (1) for the first column via the switch a, and the data latch circuit 16 (1) for the second column. 2) is input to the level shifter 18 (2) of the second column via the switch d.

[0890] Therefore, the DA converter 20 in the first column
(1) Through the output amplifier 22 (1), a positive gradation voltage corresponding to the gradation data DX1 for the first column is output. This positive gradation voltage is supplied to the signal line X1, and is applied to the corresponding pixel electrode in the first column through the only thin film transistor on the signal line X1. Further, a negative gradation voltage is output from the DA converter 20 (2) or the output amplifier 22 (2) in the second column onto the signal line X2. It is applied to the corresponding pixel electrode in two columns.

When an even-numbered line is selected, the switches b and c are closed and the switches a and b are turned off. Thus, for example, in [first and second columns], the grayscale data DX1 of the first column from the data latch circuit 16 (1) of the first column is supplied via the switch c to the level shifter 18 (2) of the second column. ) And the second column of grayscale data DX from the second column of data latch circuits 16 (2).
2 is the first row of level shifters 18 (1) via switch b.
Is input to

[0991] Therefore, the DA converter 20 in the first column
(1) A positive-polarity gray scale voltage corresponding to the gray scale data DX2 for the second column is output from the output amplifier 22 (1). This positive gradation voltage is supplied to the signal line X1, and is applied to the corresponding pixel electrode in the second column via the thin film transistor which is ON only on the signal line X1. On the other hand, a negative gradation voltage is supplied to the signal line X2 from the DA converter 20 (2) or the output amplifier 22 (2) of the second column, and the thin film transistor which is ON only on this signal line X2 is To the corresponding pixel electrode in the first column.

The same operation as described above is performed for the other pair of rows [third and fourth rows]. Thereby, complete dot inversion is realized.

Also in this embodiment, since the signal lines X1, X2, X3,... Are always driven with either the positive polarity or the negative polarity during the frame scanning, the charge / discharge current accompanying the polarity inversion is reduced. You don't have to flush it. Therefore, the load on the signal line driver S can be reduced, and the power consumption can be greatly reduced.

In the TFT-LCD of this embodiment, the polarity of the voltage of each signal line X1, X2, X3... Is inverted for each frame in order to apply an AC voltage to each pixel, that is, for AC conversion. I have to. For this reason, at the start of each frame period, a charge or discharge current accompanying the polarity inversion flows temporarily on each of the signal lines X1, X2, X3,. The polarity inversion at the start of the frame may be performed at the time of writing the first row. However, in order to obtain good display quality from the first row, immediately before the line scanning of the first row (during the vertical retrace period, It is also possible to invert the polarity of the voltage of each signal line X1, X2, X3... By the signal line driver S.

The circuit configuration and the wiring pattern in the liquid crystal panel 10 (10 ′) in the above embodiment are merely examples, and various modifications are possible within the scope of the technical idea of the present invention. The circuit configuration of the signal line driver S (S ′) described above is also an example, and can be modified into various circuit configurations.

[0960]

According to the liquid crystal panel of the present invention, the pixels Pij arranged in a matrix of m rows and n columns are connected to the signal lines X1 to Xn in the i row and the signal lines X2 in the (i + 1) row. To Xn + 1, and during the frame scanning, each signal line is always driven with a voltage of either one of the positive polarity or the negative polarity. And the load on the signal line driver can be reduced, and the power consumption of the liquid crystal display device can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a TFT liquid crystal panel according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the TFT-LCD in the embodiment.

FIG. 3 is a block diagram showing a circuit configuration of a drive unit for one channel of a signal line driver in the embodiment.

FIG. 4 is a waveform diagram schematically showing a voltage and a current on each signal line in the example.

FIG. 5 is a block diagram illustrating a configuration of a main part of a TFT-LCD according to a second embodiment.

FIG. 6 is a diagram illustrating control for allocating gradation data to a channel driving unit according to a second embodiment.

FIG. 7 is a diagram schematically showing a wiring structure in a TFT liquid crystal panel according to another embodiment.

FIG. 8 is a diagram schematically showing a wiring structure in a TFT liquid crystal panel according to another embodiment.

FIG. 9 is a diagram schematically showing a wiring structure in a TFT liquid crystal panel according to another embodiment.

FIG. 10 is a block diagram showing a configuration example of a signal line driver applicable to the liquid crystal panel structure shown in FIGS. 7 to 9;

FIG. 11 shows an active matrix type full color TF.
FIG. 2 is a block diagram schematically illustrating a typical configuration of a T-LCD.

FIG. 12 is a partial cross-sectional view showing a typical configuration of a liquid crystal panel of a TFT-LCD.

FIG. 13 is a circuit diagram showing a circuit configuration in a liquid crystal panel of a conventional TFT-LCD.

FIG. 14 is a diagram showing voltage waveforms of a pixel electrode voltage and a counter electrode voltage by a common constant driving method.

FIG. 15 is a diagram showing a complete dot inversion pattern in a TFT-LCD.

FIG. 16 is a waveform diagram schematically showing voltage and current on each signal line in a conventional TFT-LCD.

[Explanation of symbols]

 10, 10 'liquid crystal panel 12 opposing electrodes S, S' signal line driver G gate line driver CR1, CR2 ... channel driver 24 gradation voltage generation circuit 26 data shift circuit

Claims (6)

[Claims] A liquid crystal is filled between a plurality of pixel electrodes arranged in a matrix and one counter electrode, and an odd-numbered pixel electrode in each column is connected to a first signal line via a corresponding thin film transistor. And the even-numbered pixel electrodes are electrically connected to the second signal line via the corresponding thin film transistor. In each row, the control terminals of all the thin film transistors are electrically connected to a common gate line. A liquid crystal panel connected to the common electrode; a means for applying a constant common electrode voltage to the common electrode; a gate line driving means for activating the gate line for each row by line sequential scanning; and an odd row in each frame scan. When the gate line is activated, the corresponding pixel electrode of each column has a voltage level corresponding to a desired display gray scale, and has a voltage level corresponding to the counter electrode voltage. A grayscale voltage having relatively one polarity is applied via the first signal line, and when the even-numbered gate lines are activated, a desired voltage is applied to a corresponding pixel electrode in each column. Signal line driving means for applying, via the second signal line, a gradation voltage having a voltage level corresponding to the display gradation of and having the other polarity relative to the counter electrode voltage; A liquid crystal display device comprising: polarity switching means for alternately inverting the polarity of the gradation voltage output from the signal line driving means onto the first and second signal lines for each frame. 2. The liquid crystal display device according to claim 1, wherein the pixel electrodes of two adjacent columns share the first signal line for one column and the second signal line for the other column. 3. The liquid crystal display device according to claim 1, wherein the first and second signal lines dedicated to the pixel electrodes of each pair of adjacent columns are provided. 4. The signal line driving means has a channel driving unit corresponding to a pixel electrode of each column, and the channel driving unit of each column is provided with a positive gradation voltage and a negative gradation voltage every one horizontal scanning period. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device outputs a modulation voltage and is alternately switched and connected to the first signal line and the second signal line every one horizontal scanning period. 5. The signal line driving means includes one-to-one correspondence with each signal line.
A first output mode in which each time the gate line of each row is activated, the channel drive section outputs a positive gray scale voltage, and the gate line of each row 2. The liquid crystal display device according to claim 1, wherein the second output mode in which the gray scale voltage of the negative polarity is output is alternately switched every frame. 6. A liquid crystal is filled between a plurality of pixel electrodes arranged in a matrix and one counter electrode, and an odd-numbered pixel electrode in each column is connected to a first signal line via a corresponding thin film transistor. And the even-numbered pixel electrodes are electrically connected to the second signal line via the corresponding thin film transistor, and the control terminals of all the thin film transistors in each row are electrically connected to a common gate line. LCD panel connected to.