Nothing Special   »   [go: up one dir, main page]

JP4710205B2 - Flip chip mounting method - Google Patents

Flip chip mounting method Download PDF

Info

Publication number
JP4710205B2
JP4710205B2 JP2001269826A JP2001269826A JP4710205B2 JP 4710205 B2 JP4710205 B2 JP 4710205B2 JP 2001269826 A JP2001269826 A JP 2001269826A JP 2001269826 A JP2001269826 A JP 2001269826A JP 4710205 B2 JP4710205 B2 JP 4710205B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
bag
anisotropic conductive
conductive film
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001269826A
Other languages
Japanese (ja)
Other versions
JP2003077953A (en
JP2003077953A5 (en
Inventor
雄一 高井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2001269826A priority Critical patent/JP4710205B2/en
Publication of JP2003077953A publication Critical patent/JP2003077953A/en
Publication of JP2003077953A5 publication Critical patent/JP2003077953A5/ja
Application granted granted Critical
Publication of JP4710205B2 publication Critical patent/JP4710205B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B30—PRESSES
    • B30B—PRESSES IN GENERAL
    • B30B5/00—Presses characterised by the use of pressing means other than those mentioned in the preceding groups
    • B30B5/02—Presses characterised by the use of pressing means other than those mentioned in the preceding groups wherein the pressing means is in the form of a flexible element, e.g. diaphragm, urged by fluid pressure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B30—PRESSES
    • B30B—PRESSES IN GENERAL
    • B30B15/00—Details of, or accessories for, presses; Auxiliary measures in connection with pressing
    • B30B15/06—Platens or press rams
    • B30B15/065—Press rams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75314—Auxiliary members on the pressing surface
    • H01L2224/75315—Elastomer inlay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75314—Auxiliary members on the pressing surface
    • H01L2224/75317—Removable auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83209—Compression bonding applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Fluid Mechanics (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明はフリップチップ実装方法及び装置、半導体装置に関する。
【０００２】
【従来の技術】
従来、ＩＣもしくは半導体チップの回路面を基板（配線基板ともいう）側に向けて電気的接続をとるフリップチップ実装では、ＩＣの端子にバンプを形成し、ＩＣと基板との間に異方性導電膜（ＡＣＦ：Anisotropic Conductive Film ）を介在させて、加熱加圧することによってＩＣの固定および電気的接続を行う、いわゆるＡＣＦ実装という技術がある。エレクトロニクス実装学会誌Ｖｏｌ．２．Ｎｏ．２（１９９９）によれば、現在、市場で製品化されているＡＣＦのほとんどはバインダ成分にエポキシ樹脂を使用した熱硬化型であり、含有する導電粒子として樹脂粒子に金属めっきを施したものを一般的に用いている。
【０００３】
図１０はＡＣＦ実装を説明するための概略図である。ＩＣ１は回路面を下方に向けた状態で、外部との接続端子に形成されたバンプ２と基板３に形成されたＩＣ１との接続用端子（電極）４とが接触することによって電気的に導通されている。ここで基板３は片面板、両面板あるいは、多層板である。すなわち、それぞれ基板の片面にのみ配線を施した配線基板、両面に配線を施した配線基板、および多層に配線を施した配線基板である。ＩＣ１と基板３との間にはＡＣＦ４が介在し、樹脂の硬化によってＩＣ１を基板３に固定している。場合によっては、ＩＣ１は図１１で示すように実装された状態で、その周辺を樹脂ｇで封止される（モールド）こともある。
【０００４】
図１２は従来技術によるＡＣＦ実装のプロセスフローを示す。図１２Ａで示すようにウエハ上に回路が形成されたものを切り出して得られるＩＣ１の回路面に作られた外部との接続端子にバンプ２を形成する（いわゆるベアチップと呼ばれる状態である）。一方、基板３には配線パターンが形成されているが、この電極もしくは端子４にＡＣＦ５が貼着される（図１２Ｂ）。
ついで図１２Ｃに示すようにＩＣ１の回路面を下にした状態で、装着装置Ｐで搬送し、ＩＣ１側のバンプ２と基板３の基板側の接続端子４とが重なり合うように位置合わせが行われる。そして加熱、加圧する。樹脂を硬化させるために一定の加熱時間１０〜４０秒程度が必要である。また，基板３の端子４が基板３内に沈み込む方向に数μｍ以上変形する程度に加圧することによって、ＩＣ１のバンプ２と基板３の接続端子４とが高い信頼性のもとに電気的導通を保つことができる。図１３はこのようにして得られた半導体装置Ｈの拡大側面図であるが図示するように異方性導電膜５がＩＣ１の側方から外方へとはみ出している。ＩＣ１が薄く加工されている場合には、このはみ出し量はさらに大きくなる。このはみ出し部分はほとんど加圧されていない。工程としてはここで終了させる場合もあるが、このように実装されたＩＣの周辺を図１２Ｄで示すように樹脂ｇで封止する場合もある。
【０００５】
特開２０００−２２３５３４号公報でも異方性導電性ペーストが半導体チップの両側方へ大きくはみ出ししている図が示されされているが，これに対する対策は何ら説明されていない。殆んどこのはみ出し部分は加圧されていないと思われる。
【０００６】
【発明が解決しようとする課題】
以上、従来の技術によると１個のＩＣを実装するためにそれぞれ１０〜４０秒ずつ加熱加圧する必要があったため、低い生産性や生産コストの高さが問題となっていた。これに対しては図１４で示すように１個の装着装置Ｐ’に２個のＩＣ１’を装着して基板３’にフリップチップ実装することも考えられるが２個のＩＣ１’、１’間にわずかに厚みの差があるだけでも加圧力、すなわち基板３’内への電極沈み込み量に大きな差が出てくる。また２台の装着装置Ｐを用いて同時に加圧するにしても装着装置Ｐ、Ｐと基板３’、３’との平行度を同一に現出することはきわめて困難である。
また品質上も、ＡＣＦ５のＩＣ１からはみ出した部分については、熱と圧力が十分に伝わらないために樹脂の硬化を制御することが困難である、という問題点があった。また樹脂硬化後のＡＣＦ５はみだし部分に空隙が残ってしまうという問題もあり信頼性を低下させる原因となっていた。これについては、はみ出し部分で顕著であり、特にＩＣ１周辺を樹脂ｇで図１１で示すように封止した場合に、信頼性に大きな影響が見られた。また、はみ出し部分には、配線や他の部品を配置させることができないため、回路設計上の制約となっていた。
本発明は以上の問題点に鑑みてなされ、これら問題点を解決するフリップチップ実装方法及び装置、半導体装置を提供することを課題とする。
【０００７】
【課題を解決するための手段】
以上の課題は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、異方性導電膜を介して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装方法において、前記配線基板に対し、前記半導体チップを位置決め配設した後、加熱して前記異方性導電膜を硬化度１５〜３０％の範囲内で半硬化させる工程と、この工程の後、少なくとも前記半導体チップ及び前記異方性導電膜に等方位に均等な圧力を加えながら、かつ加熱しながら前記異方性導電膜を硬化させて、前記配線基板に１個又は複数個の前記半導体チップを固定させる工程と、を有することを特徴とするフリップチップ実装方法、
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、異方性導電膜を介して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装方法において、複数枚の前記配線基板の各々に一個または複数個の前記半導体チップを対向して位置決め配設した後、加熱して前記異方性導電膜を硬化度１５〜３０％の範囲内で半硬化させる工程と、この工程の後、少なくとも前記半導体チップ及び前記異方性導電膜に等方位に均等な圧力を加えながら、かつ加熱しながら前記異方性導電膜を硬化させて、各前記配線基板に前記半導体チップを固定させる工程と、を有することを特徴とするフリップチップ実装方法、
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、異方性導電膜を介して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装装置において、前記配線基板に対し、前記半導体チップを位置決め配設する手段と、前記位置決めされた配設基板と半導体チップを加熱し前記異方性導電膜を硬化度１５〜３０％の範囲内で半硬化させる手段と、少なくとも前記半導体チップ及び前記異方性導電膜に等方位に均等な圧力を加える加圧手段とを設け、前記加圧手段により圧力を加えながら、かつ加熱しながら前記異方性導電膜を硬化させて、前記配線基板に前記半導体チップを固定させるようにしたことを特徴とするフリップチップ実装装置、
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、異方性導電膜を介して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装装置において、複数枚の前記配線基板の各々に一個または複数個の前記半導体チップを位置決め配設する手段と、加熱して前記異方性導電膜を硬化度１５〜３０％の範囲内で半硬化させる手段と、前記半硬化させた後、少なくとも前記半導体チップ及び前記異方性導電膜に等方位に均等な圧力を加える加圧手段とを設け、前記加圧手段により圧力を加えながら、かつ加熱しながら前記異方性導電膜を硬化させて、各前記配線基板に前記半導体チップを固定させるようにしたことを特徴とするフリップチップ実装装置、
又は、請求項１又は６に記載のフリップチップ実装方法により製造された半導体装置、
又は、請求項１０又は１５に記載のフリップチップ実装装置により製造された半導体装置
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、絶縁性樹脂膜を介して加圧して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装方法において、前記配線基板に対し、前記半導体チップを位置決め配設した後、加熱して前記樹脂を硬化度１５〜３０％の範囲内で半硬化させる工程と、この工程の後、少なくとも前記半導体チップ及び前記絶縁性樹脂膜に等方位に均等な圧力を加えながら、かつ加熱しながら前記絶縁性樹脂膜を硬化させて、前記配線基板に１個又は複数個の前記半導体チップを固定させるようにしたことを特徴とするフリップチップ実装方法、
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、絶縁性樹脂膜を介して加圧して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装方法において、複数枚の前記配線基板の各々に一個または複数個の前記半導体チップを位置決め配設した後、加熱して前記絶縁性樹脂膜を硬化度１５〜３０％の範囲内で半硬化させる工程と、この工程の後、少なくとも前記半導体チップ及び前記絶縁性樹脂膜に等方位に均等な圧力を加えながら、かつ加熱しながら前記絶縁性樹脂膜を硬化させて、各前記配線基板に前記半導体チップを固定させるようにしたことを特徴とするフリップチップ実装方法、
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、絶縁性樹脂膜を介して加圧して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装装置において、前記配線基板に一個又は複数個の前記半導体チップを位置決め配設する手段と、加熱して前記絶縁性樹脂膜を硬化度１５〜３０％の範囲内で半硬化させる手段と、少なくとも前記半導体チップ及び前記絶縁性樹脂膜に等方位に均等な圧力を加える加圧手段を設け、前記加圧手段により圧力を加えながら、かつ加熱しながら前記絶縁性樹脂膜を硬化させて、前記配線基板に前記半導体チップを固定させるようにしたことを特徴とするフリップチップ実装装置、
又は、複数の電極端子を有する配線基板と対向させて、複数の接続端子を有する半導体チップを配設し、絶縁性樹脂膜を介して加圧して前記配線基板の前記電極端子と前記半導体チップの前記接続端子とを電気的に接続するフリップチップ実装装置において、複数枚の前記配線基板の各々に一個または複数個の前記半導体チップを対向して位置決め配設する手段と、加熱して前記絶縁性樹脂膜を硬化度１５〜３０％の範囲内で半硬化させる手段と、前記半硬化させた後、少なくとも前記半導体チップ及び前記絶縁性樹脂膜に等方位に均等な圧力を加える加圧手段を設け、前記加圧手段により圧力を加えながら、かつ加熱しながら前記絶縁性樹脂膜を硬化させて、各前記配線基板に前記半導体チップを固定させるようにしたことを特徴とするフリップチップ実装装置、
又は、請求項２２又は２７に記載のフリップチップ実装方法により製造された半導体装置、
又は、請求項３１又は３４に記載のフリップチップ実装装置により製造された半導体装置、によって解決される。
【０００８】
【発明の実施の形態】
以下、本発明の実施の形態によるフリップチップ実装方法および装置について図面を参照して説明する。
【０００９】
図１は本実施の形態によるフリップチップ実装プロセスを示すが、図１Ａにおいて、ＩＣ１の外部接続用端子にはバンプ２が形成されている。これは例えば金属ワイヤーを超音波接合することによって形成してもよいし、めっき法、印刷法によって形成してもよい。基板３は片面、両面あるいは多層板でありＩＣ１のバンプ２に対応した端子４が表面に形成されている。基板３の上にはあらかじめ異方性導電膜５が形成されている（図１Ｂ）。これはエポキシ樹脂の中に導電性の粒子が含有されているもので、プロセス条件のばらつきを吸収し安定した導通を得る、という効果がある。
異方性導電膜（ＡＣＦとも言う）５としては例えば、フイルム状のものを貼り付けてもよいし、ペースト状のものを塗布あるいは印刷によって形成してもよい。なお、ＡＣＦ５を貼付するときには、若干の加熱加圧をこれに施すことが好ましい。例えば９．６ｍｍ角のＩＣに対して４０μｍ厚さで１０．０ｍｍ角のＡＣＦでは、８０℃、５秒間の加熱で１０Ｋｇｆの荷重をかけることが好ましい。
次に、図１Ｃで示すように、ＩＣ位置決め装置１０によってＩＣ１を真空吸着させて、基板３の直上方にまで搬送し、異方性導電膜５とＩＣ１の回路面が密着するように搭載する。このときＩＣ１のバンプ２と基板３の端子４とが正確に重なり合うように位置あわせする。位置決め装置１０はこれを実現するだけの性能を有するものである。例えばＩＣ１が９．６ｍｍ平方の大きさで、厚さ１００μｍであれば、このような場合、位置決めと共に１Ｋｇｆ（９．８Ｎ）の荷重が３秒間加えられる。これによって、より確実に正確な位置決めが行われる。次いで４Ｋｇｆ／ｃｍ2 （４．３Ｋｇ／ｃｍ2 もしくは３９．２×１０4 Ｐａ）の荷重で１７５℃の温度で２秒間加熱される。これが図１Ｄの状態である。これでＡＦＣの半硬化の状態が得られる。本実施の形態では以下のようにして硬化度もしくは反応率が測定される
ＡＣＦの硬化前のエポキシ量に対し、ある時間硬化後のそれがどれくらいの割合で減少しているかを比較することによって反応率を算出する。
１．ＡＣＦ（硬化前）を測定する。
２．ある時間硬化後のＡＣＦを測定する（サンプルを採取するときは圧着部（ＩＣ下部）から取る）。
＜反応率の算出＞
図３に示すような吸収スペクトルのチャートからメチル基（−ＣＨ３）とエポキシ基の吸光度を算出する。
メチル基の吸収波長は２９２２ｃｍ−１、エポキシ基は９１４ｃｍ−１
＜算出方法＞
エポキシ残存率（Ｘ）＝（ａ／ｂ）／（Ａ／Ｂ）×１００（％）
反応率＝１００−Ｘ（％）
Ａ：圧着前（硬化前）のエポキシ基吸収強度
Ｂ：圧着前（硬化前）のメチル基吸収強度
ａ：圧着後（硬化後）のエポキシ基吸収強度
ｂ：圧着後（硬化後）のメチル基吸収強度
本発明の実施の形態によれば、上述の反応率が１５〜３０％の範囲内の半硬化状態とされる。なお、メチル基の吸収強度は硬化前と硬化後とで図３のＡ、Ｂで示すように吸収強度は殆んど変化していない。すなわち、ｂ＝Ｂである。よってＸはエポキシ基の硬化前後の吸収強度の比によって決定し得る。
位置決め装置１０は異方性導電膜５が半硬化の状態になった後、ＩＣ１から離れて外方へと搬出される。次いで図２Ａで示すように本発明にかかわる等方加圧装置１２が半導体装置Ｈ’の直上方へと搬送され、そのケース１４がシール部材１６を介してステージ１７に圧設される。ケース１４内には柔軟な材質でなる袋状物２２が気密に取り付け板１８に固定されている。この取り付け板１８は図示せずともケース１４の内壁に固定されている。取り付け板１８の中央部に形成した開口には気密にパイプ２８が固定されており、油圧室２９内に連通している。油圧室２９内には、パイプ２８を介して高圧の油が供給される。袋状物２２はこれにより図示のように膨張し、ＩＣ１およびＡＦＣ５に袋状物２２を介して矢印で示すように等方的に均等な圧力が加えられる。他方、ステージ１７内に設けられたヒータ３２によって所定の温度で加熱される。所定の時間後ＡＣＦ５が本硬化する。なお、ヒータ３２により所定の温度（例えば約１８０℃）で加熱するとしたが、これに代えてパイプ２８を介して供給される油を油圧室２９で所定の温度に加熱するようにしてもよい。
またケース１４内にはパイプ２６を介して排気装置（図示せず）が接続されケース１４と袋状物２２との間の空間２０を真空状態に保つ。これにより袋状物２２の膜はぴったりとＩＣ１およびＡＣＦ５に押さえつけられる。よってＩＣ１およびＡＦＣ５にはより均一的で等方的な圧力（例えば約２０Ｋｇ／ｃｍ2 もしくは１９．６×１０4 Ｐａ）が加えられる。なお、図１Ｄで示すようにしてＡＣＦ５が半硬化状態とされているので、以上の操作で本硬化されるときには、位置ずれは全く生じない。
以上により、基板３の端子４が基板内に数μｍ以上沈み込む変形をし安定な電気的な導通を得る事ができる。またはみ出しているＡＦＣ５にも均一的に圧力を加えることができるので、はみ出し量も従来より大幅に小さくすることができ、またこの硬化状態も制御することができる。さらに真空状態に置かれることによって、より均一的な圧力を加えられることにより異方性導電膜５内の空隙（ｖｏｉｄ）を軽減することができる。これにより図２Ｂで示すように樹脂ｇで封止しも空隙が原因となる弊害はほとんど生ずることはない。
上述の反応率（本願では硬化度ともいう）１５〜３０％というのは、すなわちボイドが発生せず、かつ位置ずれがしない程度の硬化条件範囲である。図１Ｄの状態で反応を促進させ過ぎるとボイドの発生やはみ出し部の残存による信頼性の劣化が現れてくる。
【００１０】
図４は本発明の第２の実施の形態によるフリップチップ実装装置を示す。圧力容器３０内にはパイプ３９をとおって供給された加圧油３４が充填されている。圧力容器３０の底壁部３０ａにはヒータ３２が設けられておりこの上に上述のようにしてＡＣＦ５は半硬化状態とされている半導体装置ＨＡが配設されている。そしてこの上に柔軟なシート３８が被せられている。圧力容器３０の底壁３０ａには開口が形成されこれに気密にパイプ３６が接続され、これを介してシート３８の下方空間が排気されシート３８はぴったりと半導体装置ＨＡの外周面および圧力容器３０の底壁３０ａに吸着する。よって油３４の油圧が半導体装置ＨＡの外周面に等圧的に均等に加えられる。よって第一の実施の形態と同じ効果を奏することができる。
【００１１】
図５は本発明の第３の実施の形態によるフリップチップ実装装置を示す。ステージ４８上に基板４０が配設され、この上に高さもしくは厚さの相異なる半導体チップＩＣＡ、ＩＣＢ、ＩＣＣが上述と同様にしてフリップチップ実装されている。柔軟な材質でなる袋状物４２は取り付け板４４に気密に取り付けられている。これはケース４６に固定されており、このケース４６の内壁と袋状物４２との間の空間５２は上記第一の発明の実施の形態と同様に排気される。すなわち、半導体チップＩＣＡ，ＩＣＢ、ＩＣＣおよびＡＣＦ５1 、５2 、５3 （いずれも半硬化状態とされている）の表面は真空と接する。この上で袋状物４２内に加圧油５４が供給されると図示のように膨張し半導体チップＩＣＡ、ＩＣＢ、ＩＣＣおよびＡＣＦ５1 、５2 、５3 にぴったりと密着し加圧油５４の圧力がこの膜部材を介して等方的に、均等に加えられる。よって異なる厚さにもかかわらず各半導体チップＩＣＡ、ＩＣＢ、ＩＣＣのバンプはほぼ同等に基板４０内に、ほぼ所定量沈んだ電極（端子）４と当接し安定な導電性を得る事ができる。その他の効果は第一の実施の形態と同様である。また一度に複数枚の基板に半導体チップを固定させることができるので、従来の一枚ずつの処理に比べ、大幅に一枚あたりの時間を短縮することができ、生産効率を向上させることができる。
【００１２】
図６は本発明の第４の実施の形態を示しステージ６０の上には二枚の基板６２および６４が載置される。それぞれに半導体チップＩＣＤおよびＩＣＥ、ＩＣＦがフリップチップ実装されている。ＡＣＦ５1 〜５3 はいずれも半硬化状態とされている。その他の構成は第３の実施の形態と同様であるので同一の符号を符しその詳細な説明は省略する。本実施の形態では異なる厚さの基板６２、６４の上に異なる厚さの半導体チップＩＣＤ、ＩＣＥ、ＩＣＦが実装されているにもかかわらず各半導体チップＩＣＤ、ＩＣＥ、ＩＣＦが当接する基板の電極４の基板内への沈み量はほぼ同一であり安定な導電状態を得る事ができる。その他の効果は上記の実施の形態と同様である。
【００１３】
図７及び図８は、本発明の第５の実施の形態を示すが、図において油圧シリンダＡから突出する駆動ピストンＢの上端には、下型７１が固定されており、この上にパッキン７３が取り付けられている。またこれに対向して上壁体Ｄには、上型７２が固定されており、これに対向する環状サイド型７５が配設され、これは４本の案内ボルト７４により上下動をガイドされている。以上の構成要素は図７で断面で明確に示されている。図８において、塊状弾性部材Ｇが環状のサイド型７５と上型７２との間に弾接して配設されている。この材質としては、天然ゴムＳＢＲ、ＢＲ、ＩＲ及びＣＲ等のジエンコム、ＩＩＲ、ＥＰＭ及びＥＰＤＭ等のオレフィンゴム、アクリロニトリルブタジエンゴム、シリコーンゴム、フッ素ゴム、クロロスルホン化ポリエチレン、塩素化ポリエチレン、塩素化ブチルゴム、多流化ゴム、ウレタンゴム、アクリルゴム、エピクロルヒドリンゴム、ポリプロピレンオキシド、エチレン酢酸ビニル共重合体などの特殊合成ゴム、並びに熱可塑性エラストマ等のゴム弾性を有する柔軟弾性材料を挙げることができる。
【００１４】
図８において下型７１の載置面７１ａには基板３が載置され、更に上記の実施の形態と同様にしてこの上に位置決め装置により搬送されてきた半導体チップＩＣが載せられる。またＡＣＦ５は半硬化の状態とされている。シリンダＡを駆動し、ピストンＢを上昇させると、下型７１は上型７２に近接し、ついには基板３と半導体チップＩＣとで構成されている半導体装置ＨＤは塊状弾性部材Ｇに埋まるような形で圧接される。なお、上型７２及び下型７１にはヒーターが内蔵されており、弾性部材Ｇはこの加熱によりその柔軟性を増大せており、容易に半導体装置ＨＤは塊状弾性部材Ｇ中に埋め込まれるが如く、等方的かつ均等に圧接される。なお、弾性部材Ｇは、その外周面がサイド型７５及びその上面は上型７２の底面によってその変形を規制されており、結果として下型７１の載置面７１ａに載置されている半導体装置ＨＤの全体を等方的に均等加圧する。また下型７１に真空用孔ｈが形成されており、これを介して半導体装置ＨＤのまわりが真空とされている。よって、上記実施の形態と同様な効果を奏するものである。
【００１５】
図９は図７及び図８の装置を使って実験した載置面７１ａ上の半導体装置の載置図を示すものであるが、１４４ｍｍ角の載置面７１ａ上に、４隅及び中央にほぼ方形の配線基板８０を配設し、これらにＩＣを上述の実施の形態と同様にしてフリップチップ実装させた。また介在されているＡＣＦは半硬化の状態とされている。図７及び図８の装置により加圧して、柔軟な弾性部材Ｇの加圧により得られた結果を表１に示す。これによると、各基板８０内での電極（端子）の沈み込み量は平均値１７．１μｍ及び標準偏差σが１．２であり、十分に均等に沈み込んでいることがわかる。よってバンプと電極端子との電気的導通は安定に保たれていることがわかる。またＡＣＦが半硬化の状態とされてから、加圧されたので、ＩＣの基板に対する位置ずれは全くなかった。
【００１６】
【表１】

Figure 0004710205
【００１７】
更に図７及び図８の装置を使って、１枚の基板上に１００μｍと３００μｍの厚さの半導体チップをフリップチップ実装させ、同時に圧着する実験を行ったが、それぞれの沈み込み量は１００μｍ厚さで１６．３μｍ、３００μｍ厚さで１５．８μｍであり、良好な結果を得た。
なお、図７、図８の装置は、例えば特開２０００−７９６１１に開示された装置と類似の構成を有するものである。
【００１８】
以上、本発明の各実施の形態について説明したが、勿論、本発明はこれらに限定されることなく、本発明の技術的思想に基づいて種々の変形が可能である。
【００１９】
例えば以上の実施の形態では、圧力媒体として油が用いられたが、これに限ることなく他の流体、例えば水や空気であってもよい。
【００２０】
また、第２の実施の形態では、圧力容器３０内に油を充填させ、圧力容器３０の底壁３０ａに基板３を載置させ、この上に半導体チップをフリップチップ実装させて得られる半導体装置ＨＡ全体に柔軟な膜３８を覆うようにして等方的かつ、均等な圧力を加えるようにしたが、レトルト食品の如く、全体を柔軟な袋状物内に収容し、図２に示す圧力容器３０のほぼ中央部で浮遊させるような形で加熱、加圧させるようにしてもよい。
【００２１】
また、以上の実施の形態ではいわゆるフリップチップ実装を説明したが、本発明はこの技術的用語の範囲内に限定されることはない。一方の配線基板に対し、半導体素子を上記実施の形態のように単に搬送するだけでほとんど両者が静的な状態で行われたが、これに限ることなく、フィルム状に形成した配線基板をロール状に巻いて、これから一つずつ繰り出して所定の位置で半導体素子を加圧、加熱して電気的導通をとるようにした、いわゆるワイヤレスボンディング方式（フリップチップ実装もこの方式に属する）のＴＡＢ（Tape Automated Bonding）実装技術にも本発明は適用可能である。
【００２２】
また、以上の実施の形態ではＡＣＦ膜を用いたが、これに代えて絶縁性の樹脂を用いてもよい。この場合にも、勿論、図１Ｄに示す状態で加熱され半硬化の状態とされてから、全硬化の状態とすべく加熱と等方的加圧が行われる。
【００２３】
また、以上の実施の形態ではＡＣＦとして絶縁材で成る球に導電材をメッキしたものを含有させたものを用いたが、これに代えてカーボンファイバ、金属等を含有させたものを用いてもよい。
【００２４】
また、以上の実施の形態ではＩＣと基板との表面は真空に接するとしたが、大気であってもよい。しかし、真空の方が、より低い流体の加圧力で袋状物の膜材がぴったりとＩＣと基板の表面に密着する。
【００２５】
以上述べた本発明の実施の形態及び変形例の効果を要約すれば以下のようになる。
１．ＩＣと基板との間に位置ずれを生ずることなく、また生じてもわずかにして本発明による等方加圧方式により以下のような効果を奏することができる。
２．基板の端子とＩＣのバンプとを電気的に接続し、固定する工程において、ＩＣ上部とその周辺部を含む領域を等方位に均一な圧力を負荷することによって、異方性導電膜、あるいは樹脂のはみ出し部分の硬化条件を制御できるようになった。これによって信頼性の向上という効果が得られる。
３．基板の端子とＩＣのバンプとを電気的に接続し、固定する工程において、ＩＣ上部とその周辺部を含む領域を等方位に均一な圧力を負荷することによって、異方性導電膜、あるいは樹脂の中に生じる空隙を低減させることができるようになった。これによって信頼性の向上という効果が得られる。
４．上記の工程において周囲を真空状態に保つことによって、異方性導電膜あるいは樹脂に生じる空隙を激減させることができるようになった。これによって信頼性の向上という効果が得られる。
５．上記の工程において複数のＩＣに対して、同時に処理することができるようになった。これによって実装工程の大幅な製造時間の短縮と、それによるコスト削減という効果が得られる。例えば、１つのＩＣの実装に４０秒かかるとすれば、２つ同時に加圧すると製造時間は半分、３つ同時の場合製造時間は１／３となる。
６．上記工程において、複数の基板を同時に処理することができるようになった。これによって実装工程の大幅な製造時間の短縮と、それによるコスト削減という効果が得られる。例えば、２つのＩＣを実装する基板２枚を同時に処理した場合、その効果は従来方法の１／４となる。
７．複数のチップに対して均一な圧力を負荷することによって、大きさ・形の異なるＩＣを同時に処理することができるようになった。
８．複数のチップに対して均一な圧力を負荷することによって、厚さの異なるＩＣを同時に処理することができるようになった。
９．複数のチップに対して同時に異方性導電膜あるいは樹脂を硬化させることによって、ＩＣ間の距離を小さくすることができるようになった。従来方法によれば、はみ出し部分を考慮して、０．５ｍｍ〜１ｍｍ以上あけていたが、理論上０ｍｍとすることも可能となる。
なお、半硬化後のＡＦＣの硬化度は１週間放置しても殆んど変化がなく、直ちに本硬化せずとも上述と同等な効果が得られるので、生産管理上も好都合である。
【００２６】
【発明の効果】
以上述べたように本発明のフリップチップ実装方法及び装置、半導体装置によれば、低コストで生産性を高くして、高信頼性の半導体装置を製造することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態による半導体装置の製造プロセスを示すが、ＡはＩＣの側面図、Ｂは配線基板の端子上に異方性導電膜を貼着した状態を示す側面図、Ｃは位置決め装置により、ＩＣを配線基板の上に位置決めして搭載した状態を示す側面図である。
【図２】図１に続く工程を示す図でＡは半導体装置に等方的かつ、均等的な圧力を加える装置を適用した状態を示す側面図、Ｂは図２Ａで得られた半導体装置に、更に樹脂をモールドさせて得られた半導体装置の断面図である。
【図３】半硬化状態の反応率を測定する赤外線吸収スペクトルチャートでＡは未硬化及びＢは半硬化状態のエポキシ樹脂の赤外線吸収スペクトルである。
【図４】本発明の第２の実施の形態によるフリップチップ実装装置の断面図である。
【図５】本発明の第３の実施の形態によるフリップチップ実装装置の要部の拡大断面図である。
【図６】本発明の第４の実施の形態によるフリップチップ実装装置の要部の拡大断面図である。
【図７】本発明の第５の実施の形態によるフリップチップ実装装置の側面図である。
【図８】同装置の要部の拡大断面図である。
【図９】図７及び図８の装置を使った半導体装置の加圧実験方法を示す模式図である。
【図１０】従来の方法により製造した半導体装置の断面図である。
【図１１】図１０の半導体装置に樹脂でモールドした状況を示す断面図である。
【図１２】従来例のフリップチップ実装方法を示す工程図で、Ａは半導体チップの側面図、Ｂは配線基板の電極にＡＣＦを貼着した状況を示す側面図、Ｃは図１２Ａの半導体チップを図１２Ｂの配線基板に搭載した状態を示す側面図、Ｄは図１２Ｃで得られた半導体装置を樹脂で封止した状況を示す側面図である。
【図１３】図１２Ｃで得られた半導体装置の拡大断面図である。
【図１４】従来例で２個のＩＣを一台の装着装置で加圧する状況を示す側面図である。
【符号の説明】
１……ＩＣ、２……バンプ、３……基板、４……電極、５……異方性導電膜、５1 、５2 、５3 ……異方性導電膜、１２……等方加圧装置、２０……真空空間、２２……袋状物、３０……圧力容器、３４……加圧油、３８……柔軟な膜、４２……袋状物、６０……基板、Ｇ……塊状弾性部材、Ｈ、Ｈ’、ＨＡ、ＨＢ、ＨＣ、ＨＤ……半導体装置、ＩＣＡ、ＩＣＢ、ＩＣＣ、ＩＣＤ、ＩＣＥ、ＩＣＦ……半導体チップ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flip chip mounting method and apparatus, and a semiconductor device.
[0002]
[Prior art]
Conventionally, in flip chip mounting in which an electrical connection is made with the circuit surface of an IC or semiconductor chip facing the substrate (also referred to as a wiring substrate), bumps are formed on the terminals of the IC and anisotropy is formed between the IC and the substrate There is a so-called ACF mounting technique in which an IC is fixed and electrically connected by heating and pressing through a conductive film (ACF: Anisotropic Conductive Film). Electronics Packaging Society Journal Vol. 2. No. 2 (1999), most of the ACFs currently commercialized in the market are thermosetting using epoxy resin as the binder component, and the resin particles that have been subjected to metal plating as the contained conductive particles. Generally used.
[0003]
FIG. 10 is a schematic diagram for explaining the ACF mounting. The IC 1 is electrically conductive when the bump 2 formed on the connection terminal with the outside contacts the connection terminal (electrode) 4 with the IC 1 formed on the substrate 3 with the circuit surface facing downward. Has been. Here, the substrate 3 is a single-sided board, a double-sided board, or a multilayer board. That is, a wiring board in which wiring is provided only on one side of the board, a wiring board in which wiring is provided on both sides, and a wiring board in which wiring is provided in multiple layers. An ACF 4 is interposed between the IC 1 and the substrate 3, and the IC 1 is fixed to the substrate 3 by curing of the resin. In some cases, the periphery of the IC 1 may be sealed (molded) with the resin g in the mounted state as shown in FIG.
[0004]
FIG. 12 shows a process flow of ACF mounting according to the prior art. As shown in FIG. 12A, bumps 2 are formed on external connection terminals formed on the circuit surface of IC 1 obtained by cutting out a circuit formed on a wafer (this is a so-called bare chip state). On the other hand, a wiring pattern is formed on the substrate 3, and the ACF 5 is attached to the electrode or terminal 4 (FIG. 12B).
Next, as shown in FIG. 12C, with the circuit surface of the IC 1 facing down, the IC 1 is transported by the mounting device P, and alignment is performed so that the bumps 2 on the IC 1 side and the connection terminals 4 on the substrate side of the substrate 3 overlap. . And it heats and pressurizes. A constant heating time of about 10 to 40 seconds is required to cure the resin. Further, by pressing the terminal 4 of the substrate 3 so as to be deformed by several μm or more in the direction of sinking into the substrate 3, the bump 2 of the IC 1 and the connection terminal 4 of the substrate 3 are electrically connected with high reliability. Conductivity can be maintained. FIG. 13 is an enlarged side view of the semiconductor device H thus obtained. As shown in the figure, the anisotropic conductive film 5 protrudes from the side of the IC 1 to the outside. When the IC 1 is thinly processed, the amount of protrusion is further increased. This protruding portion is hardly pressurized. Although the process may be terminated here, the periphery of the IC thus mounted may be sealed with a resin g as shown in FIG. 12D.
[0005]
Japanese Patent Application Laid-Open No. 2000-223534 also shows a diagram in which the anisotropic conductive paste protrudes greatly on both sides of the semiconductor chip, but no countermeasure is provided for this. It seems that most of the protruding part is not pressurized.
[0006]
[Problems to be solved by the invention]
As described above, according to the conventional technique, it is necessary to heat and press each IC for 10 to 40 seconds in order to mount one IC, so that low productivity and high production cost are problems. In contrast to this, as shown in FIG. 14, two ICs 1 ′ may be mounted on one mounting device P ′ and flip-chip mounted on the substrate 3 ′, but between the two ICs 1 ′ and 1 ′. Even if there is a slight difference in thickness, a large difference appears in the applied pressure, that is, the amount of electrode sinking into the substrate 3 '. Further, even if the two mounting apparatuses P are used to pressurize simultaneously, it is extremely difficult to make the parallelisms of the mounting apparatuses P and P and the substrates 3 ′ and 3 ′ the same.
Further, in terms of quality, there is a problem that it is difficult to control the curing of the resin because the heat and pressure are not sufficiently transmitted to the portion of the ACF 5 that protrudes from the IC 1. In addition, the ACF 5 after curing the resin has a problem that voids remain in the protruding portion, which causes a decrease in reliability. This is prominent at the protruding portion, and particularly when the periphery of IC1 is sealed with resin g as shown in FIG. Further, since wiring and other parts cannot be arranged in the protruding portion, it has been a restriction in circuit design.
The present invention has been made in view of the above problems, and an object thereof is to provide a flip chip mounting method and apparatus and a semiconductor device that solve these problems.
[0007]
[Means for Solving the Problems]
The above-described problem is that a semiconductor chip having a plurality of connection terminals is disposed opposite to a wiring board having a plurality of electrode terminals, and the electrode terminals of the wiring board and the semiconductor chip are interposed via an anisotropic conductive film. In the flip chip mounting method of electrically connecting the connection terminals, the semiconductor chip is positioned and disposed with respect to the wiring board, and then heated to heat the anisotropic conductive film with a degree of cure of 15 to 30%. A step of semi-curing within the range, and after this step, at least the semiconductor chip and the anisotropic conductive film are cured while applying an equal pressure in the same direction and heating the anisotropic conductive film. A step of fixing one or a plurality of the semiconductor chips to the wiring board, and a flip chip mounting method,
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the connection between the electrode terminals of the wiring board and the semiconductor chip is performed via an anisotropic conductive film. In the flip chip mounting method for electrically connecting a terminal, one or a plurality of the semiconductor chips are positioned and disposed on each of a plurality of the wiring boards, and then heated to heat the anisotropic conductive film. A semi-curing step within a range of 15 to 30% of the curing degree, and after this step, applying the equal pressure to at least the semiconductor chip and the anisotropic conductive film in equal orientation and heating the different Curing the isotropic conductive film and fixing the semiconductor chip to each of the wiring boards, and a flip-chip mounting method,
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the connection between the electrode terminals of the wiring board and the semiconductor chip is performed via an anisotropic conductive film. In the flip chip mounting apparatus for electrically connecting terminals, means for positioning and arranging the semiconductor chip with respect to the wiring board, and heating the positioned arrangement board and the semiconductor chip to the anisotropic conductive film Is provided with a means for semi-curing within a range of 15 to 30% of the degree of cure, and a pressure means for applying an equal pressure to at least the semiconductor chip and the anisotropic conductive film in the same direction. A flip chip mounting apparatus, wherein the anisotropic conductive film is cured while heating and the semiconductor chip is fixed to the wiring board,
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the connection between the electrode terminals of the wiring board and the semiconductor chip is performed via an anisotropic conductive film. In a flip chip mounting apparatus for electrically connecting terminals, means for positioning and arranging one or a plurality of the semiconductor chips on each of the plurality of wiring boards, and heating and curing the anisotropic conductive film A means for semi-curing within a range of 15 to 30%; and a pressurizing means for applying an equal pressure to at least the semiconductor chip and the anisotropic conductive film after the semi-curing, The flip-chip chip is characterized in that the anisotropic conductive film is cured while pressure is applied by a pressurizing means and the semiconductor chip is fixed to each wiring board. Apparatus,
Or a semiconductor device manufactured by the flip-chip mounting method according to claim 1,
Or a semiconductor device manufactured by the flip chip mounting apparatus according to claim 10 or 15
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the electrode terminals of the wiring board and the semiconductor chip are pressed by pressing through an insulating resin film. In the flip chip mounting method for electrically connecting the connection terminals, the semiconductor chip is positioned and disposed with respect to the wiring board, and then heated to semi-cur the resin within a range of 15 to 30% curing. And after the step, at least one of the semiconductor chip and the insulating resin film is cured while heating the insulating resin film while applying equal pressure in the same direction and heating. Or a flip chip mounting method, wherein a plurality of the semiconductor chips are fixed,
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the electrode terminals of the wiring board and the semiconductor chip are pressed by pressing through an insulating resin film. In the flip chip mounting method in which the connection terminals are electrically connected, one or a plurality of the semiconductor chips are positioned and arranged on each of the plurality of wiring boards, and then the insulating resin film is cured by heating. A step of semi-curing within a range of 15 to 30%, and after this step, the insulating resin film is heated while applying an equal pressure to the semiconductor chip and the insulating resin film at the same orientation and at the same time. Flip chip mounting method, wherein the semiconductor chip is fixed to each wiring board by curing
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the electrode terminals of the wiring board and the semiconductor chip are pressed by pressing through an insulating resin film. In the flip chip mounting apparatus for electrically connecting the connection terminals, means for positioning and arranging one or a plurality of the semiconductor chips on the wiring board, and heating the insulating resin film to a degree of cure of 15 to 30 %, A means for semi-curing within a range, and a pressure means for applying an equal pressure evenly to the semiconductor chip and the insulating resin film are provided, while applying pressure by the pressure means and heating A flip chip mounting apparatus, wherein the insulating resin film is cured to fix the semiconductor chip to the wiring board;
Alternatively, a semiconductor chip having a plurality of connection terminals is arranged opposite to a wiring board having a plurality of electrode terminals, and the electrode terminals of the wiring board and the semiconductor chip are pressed by pressing through an insulating resin film. In the flip chip mounting apparatus for electrically connecting the connection terminals, means for positioning and arranging one or a plurality of the semiconductor chips on each of the plurality of wiring boards, and heating to insulate A means for semi-curing the resin film within a range of 15 to 30% in degree of curing and a pressurizing means for applying an equal pressure evenly to at least the semiconductor chip and the insulating resin film after the semi-curing are provided. The semiconductor chip is fixed to each wiring board by curing the insulating resin film while applying pressure by the pressurizing means and heating. -Chip mounting apparatus,
Or a semiconductor device manufactured by the flip-chip mounting method according to claim 22 or 27,
Alternatively, the problem is solved by a semiconductor device manufactured by the flip chip mounting apparatus according to claim 31 or 34.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a flip chip mounting method and apparatus according to embodiments of the present invention will be described with reference to the drawings.
[0009]
FIG. 1 shows a flip chip mounting process according to the present embodiment. In FIG. 1A, bumps 2 are formed on the external connection terminals of the IC 1. This may be formed by, for example, ultrasonic bonding of metal wires, or may be formed by plating or printing. The substrate 3 is a single-sided, double-sided or multilayer board, and terminals 4 corresponding to the bumps 2 of the IC 1 are formed on the surface. An anisotropic conductive film 5 is previously formed on the substrate 3 (FIG. 1B). This is because the epoxy resin contains conductive particles, and has an effect of absorbing a variation in process conditions and obtaining stable conduction.
As the anisotropic conductive film (also referred to as ACF) 5, for example, a film-like one may be attached, or a paste-like one may be formed by coating or printing. In addition, when affixing ACF5, it is preferable to give a slight heat pressurization to this. For example, in the case of an ACF having a thickness of 40 μm and a 10.0 mm square for a 9.6 mm square IC, it is preferable to apply a load of 10 kgf by heating at 80 ° C. for 5 seconds.
Next, as shown in FIG. 1C, the IC 1 is vacuum-sucked by the IC positioning device 10 and transported to the position immediately above the substrate 3 so that the anisotropic conductive film 5 and the circuit surface of the IC 1 are in close contact with each other. . At this time, the bumps 2 of the IC 1 and the terminals 4 of the substrate 3 are aligned so as to accurately overlap. The positioning device 10 has a performance sufficient to realize this. For example, if IC1 has a size of 9.6 mm square and a thickness of 100 μm, in this case, a load of 1 kgf (9.8 N) is applied for 3 seconds together with positioning. As a result, accurate positioning can be performed more reliably. Then 4Kgf / cm 2 (4.3Kg / cm 2 Or 39.2 × 10 Four It is heated for 2 seconds at a temperature of 175 ° C. with a load of Pa). This is the state of FIG. 1D. This provides a semi-cured state of AFC. In the present embodiment, the degree of cure or the reaction rate is measured as follows.
The reaction rate is calculated by comparing how much it decreases after curing for a certain time with respect to the amount of epoxy before curing of ACF.
1. ACF (before curing) is measured.
2. Measure ACF after curing for a certain time (taken from the crimping part (lower part of IC) when taking a sample).
<Calculation of reaction rate>
The absorbance of the methyl group (—CH 3) and the epoxy group is calculated from the absorption spectrum chart as shown in FIG.
The absorption wavelength of the methyl group is 2922 cm-1, and the epoxy group is 914 cm-1.
<Calculation method>
Epoxy residual ratio (X) = (a / b) / (A / B) × 100 (%)
Reaction rate = 100-X (%)
A: Epoxy group absorption strength before crimping (before curing)
B: Absorption strength of methyl group before crimping (before curing)
a: Epoxy group absorption strength after crimping (after curing)
b: Methyl group absorption strength after pressure bonding (after curing)
According to the embodiment of the present invention, the above-described reaction rate is set to a semi-cured state in the range of 15 to 30%. Note that the absorption strength of the methyl group hardly changes as shown by A and B in FIG. 3 before and after curing. That is, b = B. Therefore, X can be determined by the ratio of absorption intensity before and after curing of the epoxy group.
After the anisotropic conductive film 5 is in a semi-cured state, the positioning device 10 is separated from the IC 1 and carried out outward. Next, as shown in FIG. 2A, the isotropic pressure device 12 according to the present invention is conveyed directly above the semiconductor device H ′, and the case 14 is pressure-set on the stage 17 via the seal member 16. Inside the case 14, a bag-like object 22 made of a flexible material is airtightly fixed to the mounting plate 18. The mounting plate 18 is fixed to the inner wall of the case 14 (not shown). A pipe 28 is fixed in an airtight manner in an opening formed in the central portion of the mounting plate 18 and communicates with the hydraulic chamber 29. High pressure oil is supplied into the hydraulic chamber 29 via a pipe 28. As a result, the bag-like product 22 expands as shown in the figure, and isotropically uniform pressure is applied to the IC 1 and the AFC 5 through the bag-like product 22 as indicated by arrows. On the other hand, it is heated at a predetermined temperature by a heater 32 provided in the stage 17. The ACF 5 is fully cured after a predetermined time. Although the heater 32 is heated at a predetermined temperature (for example, about 180 ° C.), the oil supplied via the pipe 28 may be heated to a predetermined temperature in the hydraulic chamber 29 instead.
Further, an exhaust device (not shown) is connected to the inside of the case 14 via a pipe 26, and the space 20 between the case 14 and the bag-like object 22 is kept in a vacuum state. Thereby, the film | membrane of the bag-like object 22 is exactly pressed on IC1 and ACF5. Therefore, a more uniform and isotropic pressure (for example, about 20 kg / cm) is applied to IC1 and AFC5. 2 Or 19.6 × 10 Four Pa) is added. Since the ACF 5 is in a semi-cured state as shown in FIG. 1D, no positional deviation occurs when the main curing is performed by the above operation.
As described above, the terminal 4 of the substrate 3 is deformed so as to sink several μm or more into the substrate, and stable electrical conduction can be obtained. Alternatively, since the pressure can be uniformly applied to the protruding AFC 5, the amount of protrusion can be significantly reduced as compared with the conventional case, and the cured state can also be controlled. Furthermore, by placing in a vacuum state, voids in the anisotropic conductive film 5 can be reduced by applying more uniform pressure. As a result, even if the resin g is sealed as shown in FIG. 2B, there is almost no adverse effect caused by the gap.
The above-mentioned reaction rate (also referred to as the degree of curing in the present application) of 15 to 30% is a curing condition range in which voids are not generated and positional displacement does not occur. If the reaction is promoted too much in the state of FIG. 1D, deterioration of reliability appears due to generation of voids or residual protrusions.
[0010]
FIG. 4 shows a flip chip mounting apparatus according to a second embodiment of the present invention. The pressure vessel 30 is filled with pressurized oil 34 supplied through a pipe 39. A heater 32 is provided on the bottom wall portion 30a of the pressure vessel 30, and a semiconductor device HA in which the ACF 5 is in a semi-cured state as described above is disposed thereon. A flexible sheet 38 is placed thereon. An opening is formed in the bottom wall 30a of the pressure vessel 30 and a pipe 36 is connected thereto in an airtight manner, through which the lower space of the sheet 38 is evacuated, and the sheet 38 is tightly fitted to the outer peripheral surface of the semiconductor device HA and the pressure vessel 30. It adsorbs to the bottom wall 30a. Therefore, the oil pressure of the oil 34 is applied to the outer peripheral surface of the semiconductor device HA in an equal pressure manner. Therefore, the same effect as the first embodiment can be obtained.
[0011]
FIG. 5 shows a flip chip mounting apparatus according to a third embodiment of the present invention. A substrate 40 is disposed on the stage 48, and semiconductor chips ICA, ICB, and ICC having different heights or thicknesses are flip-chip mounted thereon in the same manner as described above. The bag-like object 42 made of a flexible material is airtightly attached to the attachment plate 44. This is fixed to the case 46, and the space 52 between the inner wall of the case 46 and the bag-like object 42 is exhausted in the same manner as in the first embodiment. That is, the semiconductor chips ICA, ICB, ICC and ACF5 1 5 2 5 Three The surface (both in a semi-cured state) is in contact with vacuum. Then, when pressurized oil 54 is supplied into the bag-like product 42, it expands as shown in the figure, and the semiconductor chips ICA, ICB, ICC and ACF5 1 5 2 5 Three The pressure oil 54 is applied isotropically and evenly through the membrane member. Accordingly, the bumps of the semiconductor chips ICA, ICB, and ICC can be brought into contact with the electrodes (terminals) 4 that have been submerged in the substrate 40 substantially in the same amount regardless of the different thicknesses to obtain stable conductivity. Other effects are the same as those of the first embodiment. In addition, since the semiconductor chip can be fixed to a plurality of substrates at a time, the time per substrate can be greatly shortened and the production efficiency can be improved as compared with the conventional one-by-one processing. .
[0012]
FIG. 6 shows a fourth embodiment of the present invention, and two substrates 62 and 64 are placed on the stage 60. Semiconductor chips ICD, ICE, and ICF are flip-chip mounted on each. ACF5 1 ~ 5 Three Are both semi-cured. Since other configurations are the same as those of the third embodiment, the same reference numerals are used and detailed description thereof is omitted. In the present embodiment, although the semiconductor chips ICD, ICE, and ICF with different thicknesses are mounted on the substrates 62 and 64 with different thicknesses, the electrodes of the substrates with which the semiconductor chips ICD, ICE, and ICF abut The amount of sinking 4 into the substrate is almost the same, and a stable conductive state can be obtained. Other effects are the same as in the above embodiment.
[0013]
7 and 8 show a fifth embodiment of the present invention. In the figure, a lower die 71 is fixed to an upper end of a drive piston B protruding from the hydraulic cylinder A, and a packing 73 is provided thereon. Is attached. Further, an upper mold 72 is fixed to the upper wall body D so as to be opposed to this, and an annular side mold 75 is disposed opposite to the upper mold 72, and the vertical movement is guided by four guide bolts 74. Yes. The above components are clearly shown in cross section in FIG. In FIG. 8, the massive elastic member G is elastically disposed between the annular side mold 75 and the upper mold 72. This material includes natural rubbers such as SBR, BR, IR, and CR, olefin rubbers such as IIR, EPM, and EPDM, acrylonitrile butadiene rubber, silicone rubber, fluoro rubber, chlorosulfonated polyethylene, chlorinated polyethylene, and chlorinated butyl rubber. Examples thereof include special synthetic rubbers such as multi-flow rubbers, urethane rubbers, acrylic rubbers, epichlorohydrin rubbers, polypropylene oxides and ethylene vinyl acetate copolymers, and flexible elastic materials having rubber elasticity such as thermoplastic elastomers.
[0014]
In FIG. 8, the substrate 3 is placed on the placement surface 71a of the lower mold 71, and the semiconductor chip IC conveyed by the positioning device is placed thereon as in the above embodiment. ACF5 is in a semi-cured state. When the cylinder A is driven and the piston B is raised, the lower die 71 comes close to the upper die 72, and finally the semiconductor device HD composed of the substrate 3 and the semiconductor chip IC is buried in the massive elastic member G. Pressed in shape. The upper die 72 and the lower die 71 have a built-in heater, and the elastic member G has increased flexibility due to this heating, so that the semiconductor device HD is easily embedded in the massive elastic member G. , Isotropically and evenly pressed. The elastic member G has its outer peripheral surface regulated by the side die 75 and its upper surface restricted by the bottom surface of the upper die 72, and as a result, the semiconductor device placed on the placement surface 71 a of the lower die 71. The entire HD is isotropically pressurized uniformly. In addition, a vacuum hole h is formed in the lower mold 71, and a vacuum is formed around the semiconductor device HD through the hole. Therefore, the same effects as those of the above embodiment are achieved.
[0015]
FIG. 9 shows a mounting view of the semiconductor device on the mounting surface 71a, which was experimentally tested using the apparatus of FIGS. 7 and 8. On the mounting surface 71a of 144 mm square, there are almost four corners and the center. A rectangular wiring board 80 was provided, and an IC was flip-chip mounted on them in the same manner as in the above-described embodiment. The intervening ACF is in a semi-cured state. Table 1 shows the results obtained by pressurizing the flexible elastic member G using the apparatus shown in FIGS. According to this, the subsidence amount of the electrode (terminal) in each substrate 80 has an average value of 17.1 μm and a standard deviation σ of 1.2, and it can be seen that the subsidence is sufficiently uniform. Therefore, it can be seen that the electrical continuity between the bump and the electrode terminal is kept stable. In addition, since the ACF was pressed after being in a semi-cured state, there was no displacement of the IC relative to the substrate.
[0016]
[Table 1]
Figure 0004710205
[0017]
Furthermore, using the apparatus shown in FIGS. 7 and 8, an experiment was conducted in which semiconductor chips having thicknesses of 100 μm and 300 μm were flip-chip mounted on one substrate and simultaneously pressed, but each sinking amount was 100 μm thick The thickness was 16.3 μm, and the thickness was 15.8 μm with a thickness of 300 μm. Good results were obtained.
7 and 8 has a configuration similar to that disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-79611.
[0018]
As mentioned above, although each embodiment of this invention was described, of course, this invention is not limited to these, A various deformation | transformation is possible based on the technical idea of this invention.
[0019]
For example, in the above embodiment, oil is used as the pressure medium, but the present invention is not limited to this, and other fluids such as water and air may be used.
[0020]
In the second embodiment, the pressure vessel 30 is filled with oil, the substrate 3 is placed on the bottom wall 30a of the pressure vessel 30, and a semiconductor chip is obtained by flip-chip mounting thereon. The isotropic and uniform pressure is applied so as to cover the flexible membrane 38 over the entire HA, but the whole is housed in a flexible bag-like material like a retort food, and the pressure container shown in FIG. You may make it heat and pressurize in the form which floats in the approximate center part of 30.
[0021]
Although the so-called flip chip mounting has been described in the above embodiments, the present invention is not limited to the scope of this technical term. For one wiring board, the semiconductor element was simply transported as in the above embodiment, and both were performed in a static state. However, the present invention is not limited to this, and the wiring board formed in a film shape is rolled. TAB of the so-called wireless bonding method (flip chip mounting also belongs to this method), which is wound one by one and fed out one by one to pressurize and heat the semiconductor element at a predetermined position to take electrical conduction The present invention can also be applied to a tape automated bonding) mounting technique.
[0022]
Further, although the ACF film is used in the above embodiment, an insulating resin may be used instead. Also in this case, of course, after heating in the state shown in FIG. 1D and being in a semi-cured state, heating and isotropic pressurization are performed to obtain a fully cured state.
[0023]
In the above embodiment, a sphere made of an insulating material containing a conductive material plated as an ACF is used, but a carbon fiber, a metal, or the like may be used instead. Good.
[0024]
In the above embodiments, the surfaces of the IC and the substrate are in contact with vacuum, but may be air. However, in the vacuum, the bag-like film material closely contacts the surface of the IC and the substrate with a lower fluid pressure.
[0025]
The effects of the embodiment and the modification of the present invention described above are summarized as follows.
1. The following effects can be obtained by the isotropic pressurization method according to the present invention without causing any positional deviation between the IC and the substrate and, if any, by the isotropic pressing method according to the present invention.
2. In the step of electrically connecting and fixing the terminals of the substrate and the bumps of the IC, an anisotropic conductive film or resin is applied by applying a uniform pressure to the region including the upper portion of the IC and its peripheral portion in the same orientation. It became possible to control the curing conditions of the protruding part. As a result, an effect of improving reliability can be obtained.
3. In the step of electrically connecting and fixing the terminals of the substrate and the bumps of the IC, an anisotropic conductive film or resin is applied by applying a uniform pressure to the region including the upper portion of the IC and its peripheral portion in the same orientation. It has become possible to reduce voids generated in the inside. As a result, an effect of improving reliability can be obtained.
4). By maintaining the surroundings in a vacuum state in the above process, the voids generated in the anisotropic conductive film or resin can be drastically reduced. As a result, an effect of improving reliability can be obtained.
5. In the above process, a plurality of ICs can be processed simultaneously. As a result, the effect of significantly reducing the manufacturing time of the mounting process and thereby reducing the cost can be obtained. For example, if it takes 40 seconds to mount one IC, the manufacturing time is half when two are pressurized simultaneously, and the manufacturing time is one third when three are simultaneously applied.
6). In the above process, a plurality of substrates can be processed simultaneously. As a result, the effect of significantly reducing the manufacturing time of the mounting process and thereby reducing the cost can be obtained. For example, when two substrates on which two ICs are mounted are processed simultaneously, the effect is 1/4 of the conventional method.
7). By applying a uniform pressure to a plurality of chips, ICs of different sizes and shapes can be processed simultaneously.
8). By applying a uniform pressure to a plurality of chips, ICs having different thicknesses can be processed simultaneously.
9. It has become possible to reduce the distance between the ICs by simultaneously curing the anisotropic conductive film or resin on a plurality of chips. According to the conventional method, in consideration of the protruding portion, the gap is 0.5 mm to 1 mm or more, but it can theoretically be 0 mm.
It should be noted that the degree of curing of AFC after semi-curing is almost unchanged even after being left for one week, and the same effects as described above can be obtained without immediately performing main curing, which is advantageous in production management.
[0026]
【The invention's effect】
As described above, according to the flip chip mounting method and apparatus and the semiconductor device of the present invention, a highly reliable semiconductor device can be manufactured at low cost with high productivity.
[Brief description of the drawings]
FIG. 1 shows a manufacturing process of a semiconductor device according to an embodiment of the present invention, wherein A is a side view of an IC, B is a side view showing a state in which an anisotropic conductive film is attached on a terminal of a wiring board, C is a side view showing a state in which the IC is positioned and mounted on the wiring board by the positioning device.
2 is a diagram illustrating a process following FIG. 1. FIG. 2A is a side view showing a state in which an apparatus for applying an isotropic and uniform pressure is applied to a semiconductor device, and FIG. 2B is a diagram illustrating the semiconductor device obtained in FIG. 2 is a cross-sectional view of a semiconductor device obtained by further molding a resin.
FIG. 3 is an infrared absorption spectrum chart for measuring a reaction rate in a semi-cured state. A is an infrared absorption spectrum of an uncured epoxy resin and B is a semi-cured epoxy resin.
FIG. 4 is a cross-sectional view of a flip chip mounting apparatus according to a second embodiment of the present invention.
FIG. 5 is an enlarged cross-sectional view of a main part of a flip chip mounting apparatus according to a third embodiment of the present invention.
FIG. 6 is an enlarged cross-sectional view of a main part of a flip chip mounting apparatus according to a fourth embodiment of the present invention.
FIG. 7 is a side view of a flip chip mounting apparatus according to a fifth embodiment of the present invention.
FIG. 8 is an enlarged sectional view of a main part of the apparatus.
FIG. 9 is a schematic diagram showing a method for pressurizing a semiconductor device using the apparatus of FIGS. 7 and 8;
FIG. 10 is a cross-sectional view of a semiconductor device manufactured by a conventional method.
11 is a cross-sectional view showing a state where the semiconductor device of FIG. 10 is molded with resin.
12A and 12B are process diagrams showing a conventional flip-chip mounting method, in which A is a side view of a semiconductor chip, B is a side view showing a state where ACF is attached to an electrode of a wiring board, and C is a semiconductor chip of FIG. 12A. FIG. 12D is a side view showing a state in which the semiconductor device obtained in FIG. 12C is sealed with resin.
13 is an enlarged cross-sectional view of the semiconductor device obtained in FIG. 12C.
FIG. 14 is a side view showing a state in which two ICs are pressurized by a single mounting device in a conventional example.
[Explanation of symbols]
1 ... IC, 2 ... Bump, 3 ... Substrate, 4 ... Electrode, 5 ... Anisotropic conductive film, 5 1 5 2 5 Three ...... Anisotropic conductive film, 12 ... Isotropic pressure device, 20 ... Vacuum space, 22 ... Bag-like material, 30 ... Pressure vessel, 34 ... Pressurized oil, 38 ... Flexible film, 42 …… Bag-like material, 60 …… Substrate, G …… Block elastic member, H, H ′, HA, HB, HC, HD …… Semiconductor device, ICA, ICB, ICC, ICD, ICE, ICF …… Semiconductor Chip.

Claims (4)

配線基板の上に異方性導電膜を形成し、
前記異方性導電膜を形成した配線基板に対し、半導体チップを位置決め配設し、
前記異方性導電膜を加熱して硬化度１５％以上３０％以下の範囲内で半硬化させ、
前記半導体チップが配設された前記配線基板をステージに載置し、
下方が開放されたケースを前記半導体チップが配設された前記配線基板を収容するように前記ステージに圧設し、
前記ケースの内部に取り付けられた袋状物に所定の温度に加熱された油を加圧供給して前記袋状物を膨張させ、かつ前記ケースと前記袋状物の間の空間を真空状態にすることにより、前記半導体チップ、前記配線基板の一部、前記半導体チップの周囲にはみ出る前記異方性導電膜に前記袋状物の膜を密着させ、
前記密着した袋状物の膜を介して前記袋状物内の加熱され加圧された油により前記半導体チップ、前記配線基板の一部、前記半導体チップの周囲にはみ出る異方性導電膜に均等な圧力が加えられ、かつ加熱されることにより前記異方性導電膜を硬化させて、前記配線基板に１個又は複数個の前記半導体チップを固定する
フリップチップ実装方法。Forming an anisotropic conductive film on the wiring substrate;
A semiconductor chip is positioned and arranged with respect to the wiring substrate on which the anisotropic conductive film is formed ,
The anisotropic conductive film is heated and semi-cured within a range of 15% to 30% curing,
Placing the wiring board on which the semiconductor chip is disposed on a stage;
A case opened at the bottom is press-fitted to the stage so as to accommodate the wiring board on which the semiconductor chip is disposed,
The bag-like product attached to the inside of the case is pressurized and supplied with oil heated to a predetermined temperature to expand the bag-like product, and the space between the case and the bag-like product is evacuated. By adhering the bag-like material film to the anisotropic conductive film that protrudes around the semiconductor chip, a part of the wiring substrate, and the semiconductor chip,
Equivalent to an anisotropic conductive film that protrudes around the semiconductor chip, a part of the wiring substrate, and the periphery of the semiconductor chip by heated and pressurized oil in the bag through the closely-attached bag-like film A flip chip mounting method in which one or a plurality of the semiconductor chips are fixed to the wiring board by curing the anisotropic conductive film by applying a certain pressure and heating . 請求項１に記載のフリップチップ実装方法であって、
前記複数個の半導体チップのいずれかは、他と高さが異なる
フリップチップ実装方法。The flip chip mounting method according to claim 1 ,
One of the plurality of semiconductor chips has a different height from the other flip chip mounting method. 複数枚の配線基板の上に異方性導電膜を形成し、
前記異方性導電膜を形成した複数枚の配線基板の各々に対し、１個または複数個の半導体チップを位置決め配設し、
前記異方性導電膜を加熱して硬化度１５％以上３０％以下の範囲内で半硬化させ、
前記半導体チップが配設された前記複数枚の配線基板をステージに載置し、
下方が開放されたケースを前記半導体チップが配設された前記複数枚の配線基板を収容するように前記ステージに圧設し、
前記ケースの内部に取り付けられた袋状物に所定の温度に加熱された油を加圧供給して前記袋状物を膨張させ、かつ前記ケースと前記袋状物の間の空間を真空状態にすることにより、各々の前記半導体チップ、前記配線基板の一部、前記半導体チップの周囲にはみ出る前記異方性導電膜に前記袋状物の膜を密着させ、
前記密着した袋状物の膜を介して前記袋状物内の加熱され加圧された油により前記半導体チップ、前記配線基板の一部、前記半導体チップの周囲にはみ出る異方性導電膜に均等な圧力が加えられ、かつ加熱されることにより前記異方性導電膜を硬化させて、各前記配線基板に前記半導体チップを固定する
フリップチップ実装方法。An anisotropic conductive film is formed on a plurality of wiring boards,
One or a plurality of semiconductor chips are positioned and arranged for each of a plurality of wiring boards on which the anisotropic conductive film is formed ,
The anisotropic conductive film is heated and semi-cured within a range of 15% to 30% curing,
Placing the plurality of wiring boards on which the semiconductor chips are disposed on a stage;
A case with a lower opening is press-fitted on the stage so as to accommodate the plurality of wiring boards on which the semiconductor chips are disposed,
The bag-like product attached to the inside of the case is pressurized and supplied with oil heated to a predetermined temperature to expand the bag-like product, and the space between the case and the bag-like product is evacuated. By making each of the semiconductor chips, a part of the wiring substrate, the anisotropic conductive film that protrudes around the semiconductor chip, the bag-like film is closely attached,
Equivalent to an anisotropic conductive film that protrudes around the semiconductor chip, a part of the wiring substrate, and the periphery of the semiconductor chip by heated and pressurized oil in the bag-like material through the film of the closely attached bag-like material A flip-chip mounting method in which the anisotropic conductive film is cured by applying a certain pressure and being heated, and the semiconductor chip is fixed to each wiring board. 配線基板の上に絶縁性樹脂膜を形成し、
前記絶縁性樹脂膜を形成した配線基板に対し、半導体チップを位置決め配設し、
前記絶縁性樹脂膜を加熱して硬化度１５％以上３０％以下の範囲内で半硬化させ、
前記半導体チップが配設された前記配線基板をステージに載置し、
下方が開放されたケースを前記半導体チップが配設された前記配線基板を収容するように前記ステージに圧設し、
前記ケースの内部に取り付けられた袋状物に所定の温度に加熱された油を加圧供給して前記袋状物を膨張させ、かつ前記ケースと前記袋状物の間の空間を真空状態にすることにより、前記半導体チップ、前記配線基板の一部、前記半導体チップの周囲にはみ出る前記絶縁性樹脂膜に前記袋状物の膜を密着させ、
前記密着した袋状物の膜を介して前記袋状物内の加熱され加圧された油により前記半導体チップ、前記配線基板の一部、前記半導体チップの周囲にはみ出る絶縁性樹脂膜に均等な圧力が加えられ、かつ加熱されることにより前記絶縁性樹脂膜を硬化させて、前記配線基板に１個又は複数個の前記半導体チップを固定する
フリップチップ実装方法。An insulating resin film is formed on the wiring board,
A semiconductor chip is positioned and arranged on the wiring board on which the insulating resin film is formed ,
The insulating resin film is heated and semi-cured within a range of 15% to 30% curing,
Placing the wiring board on which the semiconductor chip is disposed on a stage;
A case opened at the bottom is press-fitted to the stage so as to accommodate the wiring board on which the semiconductor chip is disposed,
The bag-like product attached to the inside of the case is pressurized and supplied with oil heated to a predetermined temperature to expand the bag-like product, and the space between the case and the bag-like product is evacuated. By adhering the bag-like material film to the insulating resin film that protrudes around the semiconductor chip, a part of the wiring board, and the semiconductor chip,
The insulating resin film that protrudes around the semiconductor chip, a part of the wiring substrate, and the periphery of the semiconductor chip by the heated and pressurized oil in the bag-like substance through the closely-attached bag-like film A flip chip mounting method in which one or a plurality of the semiconductor chips are fixed to the wiring board by curing the insulating resin film by applying pressure and heating .
JP2001269826A 2001-09-06 2001-09-06 Flip chip mounting method Expired - Fee Related JP4710205B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001269826A JP4710205B2 (en) 2001-09-06 2001-09-06 Flip chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001269826A JP4710205B2 (en) 2001-09-06 2001-09-06 Flip chip mounting method

Publications (3)

Publication Number Publication Date
JP2003077953A JP2003077953A (en) 2003-03-14
JP2003077953A5 JP2003077953A5 (en) 2008-10-02
JP4710205B2 true JP4710205B2 (en) 2011-06-29

Family

ID=19095572

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001269826A Expired - Fee Related JP4710205B2 (en) 2001-09-06 2001-09-06 Flip chip mounting method

Country Status (1)

Country Link
JP (1) JP4710205B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11688716B2 (en) 2020-05-12 2023-06-27 Samsung Electronics Co., Ltd. Semiconductor chip mounting tape and method of manufacturing semiconductor package using the tape

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003063140A1 (en) * 2002-01-26 2003-07-31 Sae Magnetics (H. K.) Ltd. Method and apparatus for the prevention of electrostatic discharge (esd) by a hard drive magnetic head involving the utilization of anisotropic conductive paste (acp) in the securement to a head-gimbal assembly (hga)
EP2264748A3 (en) 2005-02-02 2012-09-05 Sony Chemical & Information Device Corporation Electric component mounting apparatus
JP4925669B2 (en) * 2006-01-13 2012-05-09 ソニーケミカル＆インフォメーションデバイス株式会社 Crimping apparatus and mounting method
KR101299773B1 (en) * 2006-09-15 2013-08-23 린텍 가부시키가이샤 Process for producing semiconductor device
JP2010034423A (en) * 2008-07-30 2010-02-12 Fujitsu Ltd Pressure-heating apparatus and method
JP5842322B2 (en) * 2010-10-15 2016-01-13 住友ベークライト株式会社 Resin composition and method for manufacturing electronic device
JP2013214619A (en) * 2012-04-02 2013-10-17 Sekisui Chem Co Ltd Semiconductor device manufacturing method
TWM450049U (en) * 2012-11-20 2013-04-01 Ableprint Technology Co Ltd Semiconductor package heat carrying device having extended communication channel structure
JP6172654B2 (en) * 2013-03-14 2017-08-02 アルファーデザイン株式会社 Component pressing device and heating system using the component pressing device
US10147702B2 (en) * 2016-10-24 2018-12-04 Palo Alto Research Center Incorporated Method for simultaneously bonding multiple chips of different heights on flexible substrates using anisotropic conductive film or paste
EP3428954B1 (en) * 2017-07-14 2021-05-19 Infineon Technologies AG Method for establishing a connection between two joining partners
EP3916840A4 (en) * 2019-01-23 2022-10-12 Musashi Energy Solutions Co., Ltd. Electrode production system and electrode production method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01199440A (en) * 1988-02-04 1989-08-10 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH02122531A (en) * 1988-11-01 1990-05-10 Matsushita Electric Ind Co Ltd Device for mounting electronic component
JPH1050930A (en) * 1996-08-06 1998-02-20 Hitachi Chem Co Ltd Multichip mounting method
JPH10107048A (en) * 1996-08-06 1998-04-24 Hitachi Chem Co Ltd Multichip mounting method, adhesive-applied chip set, and manufacture of adhesive-applied chip
JPH10294422A (en) * 1997-04-18 1998-11-04 Hitachi Chem Co Ltd Mounting method for electronic component
JPH10294563A (en) * 1997-04-18 1998-11-04 Hitachi Chem Co Ltd Multi-chip mounting method
JP2000286298A (en) * 1999-01-29 2000-10-13 Matsushita Electric Ind Co Ltd Method for mounting electronic component and device thereof
JP2002016108A (en) * 2000-06-30 2002-01-18 Toshiba Corp Semiconductor device and its manufacturing device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01199440A (en) * 1988-02-04 1989-08-10 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH02122531A (en) * 1988-11-01 1990-05-10 Matsushita Electric Ind Co Ltd Device for mounting electronic component
JPH1050930A (en) * 1996-08-06 1998-02-20 Hitachi Chem Co Ltd Multichip mounting method
JPH10107048A (en) * 1996-08-06 1998-04-24 Hitachi Chem Co Ltd Multichip mounting method, adhesive-applied chip set, and manufacture of adhesive-applied chip
JPH10294422A (en) * 1997-04-18 1998-11-04 Hitachi Chem Co Ltd Mounting method for electronic component
JPH10294563A (en) * 1997-04-18 1998-11-04 Hitachi Chem Co Ltd Multi-chip mounting method
JP2000286298A (en) * 1999-01-29 2000-10-13 Matsushita Electric Ind Co Ltd Method for mounting electronic component and device thereof
JP2002016108A (en) * 2000-06-30 2002-01-18 Toshiba Corp Semiconductor device and its manufacturing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11688716B2 (en) 2020-05-12 2023-06-27 Samsung Electronics Co., Ltd. Semiconductor chip mounting tape and method of manufacturing semiconductor package using the tape

Also Published As

Publication number Publication date
JP2003077953A (en) 2003-03-14

Similar Documents

Publication Publication Date Title
JP4513235B2 (en) Flip chip mounting device
JP4710205B2 (en) Flip chip mounting method
US7971351B2 (en) Method of manufacturing a semiconductor device
US6521480B1 (en) Method for making a semiconductor chip package
KR100384314B1 (en) Method and device for mounting electronic component on circuit board
US11394362B2 (en) Electronic component housing package, electronic apparatus, and electronic module
US7290580B2 (en) Reinforcement combining apparatus and method of combining reinforcement
US8107224B2 (en) Thin solid electrolytic capacitor having high resistance to thermal stress
JP2008544554A (en) Flip chip die assembly using thin flexible substrate
US20090258460A1 (en) Manufacturing method of semiconductor device
WO2010070806A1 (en) Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus
JP2001313314A (en) Semiconductor device using bump, its manufacturing method, and method for forming bump
US5605547A (en) Method and apparatus for mounting a component to a substrate using an anisotropic adhesive, a compressive cover film, and a conveyor
KR20030012808A (en) Method for fabricating semiconductor-mounting body and apparatus for fabricating semiconductor-mounting body
JP2003115510A (en) Method for manufacturing semiconductor mounting body and manufacturing equipment of semiconductor mounting body
US8822836B2 (en) Bonding sheet, electronic circuit device and its manufacturing method
US8875977B2 (en) Element pressing apparatus and heating system using element pressing apparatus
JP3381781B2 (en) Method of manufacturing electronic component connection body and manufacturing apparatus therefor
JPH11340278A (en) Resin sheet for mounting semiconductor device, flip chip mounting method and circuit board
US11712823B2 (en) Molding die for compression molding with resin leakage prevention member
JP3564659B2 (en) Bonding method and thermocompression bonding device using fine particles
TWI550728B (en) Package structure and manufacturing method thereof
JP2001185580A (en) Method for mounting electronic component to circuit board
KR101631293B1 (en) Method for substrate bonding of IC chip
JP2003273259A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20071027

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080814

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080814

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101207

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110201

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110222

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110307

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140401

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees