KR101631293B1

KR101631293B1 - Method for substrate bonding of IC chip

Info

Publication number: KR101631293B1
Application number: KR1020150167569A
Authority: KR
Inventors: 정종구; 양태훈
Original assignee: 정종구; 양태훈
Priority date: 2015-11-27
Filing date: 2015-11-27
Publication date: 2016-06-16

Abstract

An embodiment of the present invention includes a process of loading an integrated circuit chip having an anisotropic conductive film on the entirety of a bonding surface on which a patterned connection terminal pattern is formed, into a chamber; Loading a circuit board on which a line pattern is formed into a chamber; Aligning the connection terminal pattern of the integrated circuit chip so as to match the line pattern of the circuit board; And bonding the bonding surface with the anisotropic conductive film to a circuit board having a line pattern aligned with the connection terminal pattern.

Description

[0001] The present invention relates to a substrate bonding method for an integrated circuit chip,

The present invention relates to a substrate bonding method of an integrated circuit chip, and a method of bonding an integrated circuit chip to a circuit board such as an FPCB.

The transition of the material for the semiconductor package tends to be consistent with the functional requirements of the semiconductor package due to the high integration of the integrated circuit chips for each generation. Recently, as electronic systems have become more sophisticated, large-capacity and miniaturized, lightweight and compact packages have been constantly being developed to efficiently utilize semiconductor packaging technology or PCB area.

Specifically, since the integrated circuit chip itself can not receive or transmit an electric signal by receiving electricity from the outside, the integrated circuit chip needs to package the chip in order to send various electrical signals to the outside. In recent years, various structures have been manufactured using various members such as a connection terminal pattern, a printed circuit board, and a circuit film in consideration of chip size reduction, heat releasing ability and electrical performance improvement, reliability improvement, manufacturing cost,

Particularly, the connection terminal pattern is a structure used to connect a completed integrated circuit chip to a PCB, a socket, etc., and serves as a connection, a heat dissipation, and an external protection. Therefore, the quality required as the material for the connection terminal pattern is very complicated, and it is demanded that the quality of the connection terminal pattern, the quality of the integrated circuit chip, and the quality of the raw material itself are sufficiently satisfied. That is, basically, physical properties such as electrical conductivity, strength, thermal conductivity and thermal expansion coefficient are basically required. In addition, it is strongly demanded that the material of the connection terminal pattern becomes thinner, so that it is not deformed or discolored due to heat load during the assembling process, and the die bonding property, the line adhesion property and the bonding strength of lead are excellent. These characteristics are increasingly demanded as the degree of integration of semiconductor ICs increases.

It is necessary to increase the number of input and output terminals, which are electrical leads between the integrated circuit chip and the external circuit board, in accordance with the trend toward higher integration of such integrated circuit chips. To this end, a semiconductor package of a multi-row connection terminal pattern having leads having an arrangement of two or more rows separately connecting a chip and an external circuit has been attracting attention.

The process of manufacturing a semiconductor package of such a multi-row connection terminal pattern is generally performed by introducing a metallic carrier material into a conventional multi-row I / O (Input / Output) Pad to form a pattern that is plated using a photosensitive photoresist (liquid or solid phase) (Au / Ni / Cu / Ni / Au) for wire bonding or soldering, and then the photoresist is removed using an alkaline stripper. Then, the integrated circuit chip is mounted through wire bonding in the assembling process, molding is performed using an epoxy molding compound (EMC), and the metallic carrier material finally bonded to the lower substrate is completely removed by etching .

On the other hand, a general integrated circuit chip on which wafer fabrication is completed has connection terminal patterns formed on the active surface of an on-chip semiconductor substrate, serving as input / output terminals of an electric signal, And the active surface excluding the connection terminal patterns has a structure in which a final protective film such as a nitride film is covered

FIG. 1 is a cross-sectional view showing a state before bonding between an integrated circuit chip and a circuit board, and FIG. 2 is a sectional view showing a state in which a connection terminal pattern of an integrated circuit chip and a line pattern of a circuit board are bonded to each other.

The edge pad type semiconductor chip 1 has a structure in which a peripheral region for forming a chip pad is secured at the edge of the FPCB substrate 2 and a cell region is formed inside the edge region.

As shown in Fig. 2, when the semiconductor chip 1 and the FPCB substrate 2 are joined to each other and the connection terminal pattern 1a and the line pattern 2a are bonded to each other, there is a problem that bonding property is deteriorated. Furthermore, there is a problem in that the conductivity between the connection terminal pattern and the line pattern 21 also deteriorates after the connection is made.

Korean Patent Laid-Open No. 10-2003-0008616

SUMMARY OF THE INVENTION The present invention provides a method of bonding an integrated circuit chip to a circuit board such as an FPCB. It is also an object of the present invention to provide means for achieving more efficient bonding and higher conductivity when bonding an integrated circuit chip.

In the process of bonding, the integrated circuit chip and the circuit board are brought into close contact with predetermined pressure, and when the pressure is applied, the temperature in the chamber where the integrated circuit chip and the circuit board are located can be maintained at a predetermined temperature or higher.

The connection terminal pattern may have a structure in which a plurality of patterns are arranged in a line.

And the magnitude of the pressure is determined in inverse proportion to an interval between patterns constituting the connection terminal pattern.

And the temperature is determined in inverse proportion to an interval between patterns constituting the connection terminal pattern.

The connection terminal pattern may be characterized in that the width of each pattern is 70 mu m or more and the interval between the patterns is 20 mu m or more.

The anisotropic conductive film is an ACF (Anisotropic Conductive Film) film, and the total area of the anisotropic conductive film has a larger area than that of the integrated circuit chip.

According to the embodiments of the present invention, it is possible to achieve more efficient bonding and high conductivity at the time of bonding the integrated circuit chip.

1 is a cross-sectional view showing a state before bonding between an integrated circuit chip and a circuit board.
2 is a cross-sectional view showing a state in which a connection terminal pattern of an integrated circuit chip and a line pattern of a circuit board are bonded to each other.
3 is a view showing a substrate bonding apparatus for bonding an integrated circuit chip and a circuit board according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating a substrate process of an integrated circuit chip according to an embodiment of the present invention. FIG.
5 is a plan view of an integrated circuit chip according to an embodiment of the present invention.
FIG. 6 is a view showing a state where an anisotropic conductive film is attached to the entire bonding surface of an integrated circuit chip according to an embodiment of the present invention. FIG.
FIG. 7 is a cross-sectional view of the integrated circuit chip in the direction of AA ', showing a process of attaching an anisotropic conductive film to an integrated circuit according to an embodiment of the present invention;
8 is a view showing a state in which an ACF film, which is an anisotropic conductive film, is made conductive by heat and pressure.
FIG. 9 is a drawing showing a bonding process according to an embodiment of the present invention. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to achieve them, will be apparent from the following detailed description of embodiments thereof taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. And the present invention is only defined by the scope of the claims. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

3 is a view illustrating a substrate bonding apparatus for bonding an integrated circuit chip and a circuit board according to an embodiment of the present invention.

The substrate bonding apparatus of the present invention may include a chamber 100, a substrate support 110, a chip transferring unit 120, a pressing unit 130, a heater unit (not shown), and a control unit (not shown).

The chamber 100 has a main body having an open top and a top lead that is openably and closably provided on the top of the main body. When the top lead is coupled to the upper portion of the main body to close the main body, for example, a space for bonding processing to the integrated circuit chip 10 and the circuit board 20 is formed inside the chamber 100. A through hole is formed in the bottom surface of the main body to receive a shaft shaft 111 of a substrate support 110, which will be described later. A gate valve (not shown) is formed on the side wall of the main body to carry the circuit board 20 into the chamber 100 or carry it out. Thus, the circuit board 20 can be loaded on the support plate 112 of the substrate support 110 via the gate valve, loaded on a robot arm or a blade in an external transformer chamber.

The substrate support 110 includes a support plate 112 and a shaft shaft 111 for supporting the circuit board 20. The support plate 112 is provided in the shape of a disk in a horizontal direction inside the chamber 100 and the shaft shaft 111 is vertically connected to the bottom surface of the support plate 112. The shaft shaft 111 is connected to driving means (not shown) such as an external motor through the through-hole to elevate the support plate 112. Here, the circuit board 20 may be an FPCB (flexible printed circuit board) substrate having a flexible characteristic.

In addition, a heater unit (not shown) is built in the lower side or inside of the support plate 112 to heat the circuit board 20 to a predetermined process temperature. For example, it can be heated and maintained in the range of 80 to 250 degrees. The heater unit (not shown) may be provided at various positions in the chamber 100 as well.

The chip transferring unit 120 is a transferring means for transferring the integrated circuit chip 10 and aligning the same with the line pattern 21 of the substrate circuit so that the integrated circuit chip 10 is attached to the vacuum chuck attached by vacuum And can be loaded and positioned on the upper side of the circuit board 20 by the transfer means. Here, the anisotropic conductive film 30 is placed on the junction surface where the connection terminal pattern 11 of the integrated circuit chip 10 is provided, and is positioned above the circuit board 20 by the transfer means. Although the chip transferring unit 120 is illustrated as being pressed upward and downward in the drawing, the chip transferring unit 120 can be moved left and right, and the integrated circuit chip 20 can be transferred and loaded from the outside through a separate gate valve.

The pressing portion 130 is a means for pressurizing the integrated circuit chip 10 and the circuit board 20 which have been aligned by pressing the chip transferring portion 120 downward and the integrated circuit chip 10 and the circuit board 20 The chip transferring unit 120 may be pressed downward or the substrate supporting unit 110 may be pressed upward.

The control section (not shown) controls the connection terminal pattern 11 and the circuit board to be positioned in the chamber 100 so that the connection terminal pattern 11 is aligned with the line pattern 21 of the circuit board 20 . The bonding surface on which the anisotropic conductive film 30 is adhered is bonded to the circuit board 20 having the line pattern 21 aligned with the connection terminal pattern 11, The substrate 20 is brought into close contact with a preset pressure. Further, when the joining is performed, the heater unit is controlled so that the temperature in the chamber 100 is equal to or higher than the set temperature. The thin film manufacturing method will be described below with reference to FIG.

5 is a plan view of an integrated circuit chip according to an embodiment of the present invention. FIG. 6 is a cross-sectional view of an embodiment of the present invention. FIG. 7 is a view showing a state where an anisotropic conductive film is attached to an integrated circuit according to an embodiment of the present invention. FIG. 8 is a view showing a state in which an ACF film, which is an anisotropic conductive film, is made conductive by heat and pressure, and FIG. 9 is a view illustrating a bonding process according to an embodiment of the present invention .

First, the integrated circuit chip 10 to which the anisotropic conductive film 30 is attached is loaded on the entirety of the bonding surface on which the patterned connection terminal pattern 11 is formed (S410).

Here, the integrated circuit chip 10 has a rectangular parallelepiped plate shape as shown in Fig. Alternatively, the integrated circuit chip 10 may have various shapes instead of a rectangular parallelepiped plate shape.

The integrated circuit chip 10 has a first surface and a second surface opposed to the first surface, and on the first surface and / or the second surface of the integrated circuit chip 10, an accommodating portion IC space) is disposed. The IC space is a recess formed in a concave shape from the first surface and / or the second surface of the integrated circuit chip 10.

One end of the connection terminal patterns 11 shown in FIG. 5 is disposed along the periphery of the accommodating portion of the substrate body, and the other end opposite to the one end of each connection terminal pattern 11 is connected to the connection terminal pattern 11 It is electrically connected to each input / output terminal along the long side. The connection terminal pattern 11 has a structure in which a plurality of patterns are arranged in a line. The connection terminal patterns 11 may be arranged along the edge of the integrated circuit chip 10. The connection terminal pattern has conductivity.

The insulating member 10a covers the IC space. The insulating member 10a may be a flexible synthetic resin sheet having a thin thickness. Alternatively, the insulating member may be a synthetic resin plate having a relatively high strength. That is, the insulating member is formed on the upper and lower surfaces opposite to the bottom surface of the substrate body formed by the receiving portion.

The connection terminal pattern 11 is a pattern of connection terminals connected to the input / output terminals of the IC provided in the IC space. The connection terminal pattern 11 is composed of a tin plate 11b having conductivity and a plated film 11a as shown in Fig. The connection terminal pattern 11 corresponds to the end of each line pattern 21 formed on the first surface of the circuit board 20 body.

Each connection terminal pattern 11 is electrically connected to one end of the pattern line 21 of the circuit board 20 and electrically connected to the connection terminal pattern 11 of the integrated circuit chip 10 and the pattern line (21) can be electrically connected to each other by the anisotropic conductive film (30).

7 (a), the anisotropic conductive film 30 is attached to the entire bonding surface of the integrated circuit chip 10 on which the patterned connection terminal pattern 11 is formed. As shown in Fig. 7 the integrated circuit chip 10 to which the anisotropic conductive film 30 is attached is provided as shown in Fig. At this time, the total area of the anisotropic conductive film 30 has a larger area than the bonding surface of the integrated circuit chip 10. As will be described later, after the bonding between the integrated circuit chip 10 and the circuit board 20, the edge region protruded without contact with the integrated circuit chip 10 and the circuit board 20 forms the edge of the integrated circuit chip 10 So that the bonding force for bonding the integrated circuit chip 10 to the circuit board 20 can be improved.

The anisotropic conductive film 30 is preferably formed of an ACF (Anisotropic Conductive Film) film. The ACF film is an anisotropic conductive film in which fine conductive particles are mixed with an adhesive resin to form a film state and electricity is conducted in only one direction. The fine conductive particles can be implemented with Ni, carbon, and solder balls. That is, as shown in FIG. 8, when the ACF film with the fine conductive particles embedded therein is heated / pressed, a part of the electricity is conducted by the fine conductive particles of the object touching the upper surface of the ACF film and the lower surface of the ACF film.

On the other hand, after the process (S410) of loading the integrated circuit chip 10 having the anisotropic conductive film 30 attached thereto on the entirety of the bonding surface on which the patterned connection terminal pattern 11 is formed is loaded in the chamber 100, (S420) loading the circuit board 20 on which the circuit board 21 is formed into the chamber 100. Here, the circuit board 20 may be a flexible FPCB board, and the line pattern 21 corresponds to a pattern of lines having conductivity on the FPCB substrate.

When the integrated circuit chip 10 and the circuit board 20 are loaded into the chamber 100, the integrated circuit chip 10 is moved or the circuit board 20 is moved, And aligning the connection terminal pattern 11 of the integrated circuit chip 10 so as to coincide with the line pattern 21 of the circuit board 20 while moving the circuit board 20 and the circuit board 20 simultaneously. For example, the first connection terminal pattern of the integrated circuit chip 10 is aligned with the first line pattern of the circuit board 20, and the Nth connection terminal pattern of the integrated circuit chip 10 is connected to the circuit board 20, Align with the N-th line pattern of FIG. Such an alignment can be realized by recognizing the identifier (for example, a '+' character) displayed on the circuit board 20 as a vision camera in the chamber 100 and aligning the correspondence between preset patterns.

After the alignment process S430 is performed, a step S440 of joining the bonding surfaces to which the anisotropic conductive film 30 is attached to the circuit board 20 having the line patterns 21 aligned with the connection terminal patterns 11 I have. The integrated circuit chip 10 and the circuit board 20 can be bonded to each other by the adhesive component of the adhesive resin constituting the body of the anisotropic conductive film 30. [

The integrated circuit chip 10 and the circuit board 20 are brought into close contact with each other at a predetermined pressure between the integrated circuit chip 10 and the circuit board 20 in the process of bonding the integrated circuit chip 10 and the circuit board 20, Is maintained at a temperature equal to or higher than a preset temperature.

Therefore, the pattern bonding of the integrated circuit chip 10 and the circuit board 20 can be performed as shown in Fig. 9 (b). The patterned ACF film is pressed and pressed so that the fine conductive particles are electrically conductive to the connection terminal pattern 11 of the integrated circuit chip 10 and the line pattern 21 of the circuit board 20 . The area other than the uncompressed pattern is not electrically conductive due to the non-conductive adhesive resin.

The connection terminal pattern 11 has a structure in which a plurality of patterns are arranged in a line, and the magnitude of the pressure can be determined in inverse proportion to the interval between patterns constituting the connection terminal pattern 11. [ It is preferable that the smaller the distance between the connection terminal patterns 11 is, the smaller the pressure is. The higher the pressure in the chamber 100 in a state where the interval between the connection terminal patterns 11 is narrow, the greater the probability that the area of the conductive film without the connection terminal pattern 11 is squeezed, and the greater the probability of having conductivity.

Likewise, the temperature can be determined in inverse proportion to the interval between the patterns constituting the connection terminal pattern 11. It is preferable to lower the temperature in the chamber 100 as the interval between the connection terminal patterns 11 becomes narrower. When the temperature in the chamber 100 is increased in a state where the interval between the connection terminal patterns 11 is narrow, the region of the anisotropic conductive film 30 free of the connection terminal pattern 11 is melted and the probability of having conductivity becomes high .

Therefore, in the present invention, in attaching and bonding the ACF film as the anisotropic conductive film 30 to the integrated circuit chip 10, it is preferable that the connection terminal pattern 11 has a width of each pattern of 70 mu m or more, Or more. When the width of each pattern of the connection terminal pattern 11 is less than 70 mu m, the conductivity may be weakened at the time of pattern bonding using the ACF film. When the width is less than 20 mu m between the patterns, This is because not only the area between the patterns but also the area between the patterns may have conductivity.

The embodiments of the present invention described above are selected and presented in order to facilitate the understanding of those skilled in the art from a variety of possible examples. The technical idea of the present invention is not necessarily limited to or limited to these embodiments Various changes, modifications, and other equivalent embodiments are possible without departing from the spirit of the present invention.

S410: Integrated circuit chip loading process
S420: Circuit board loading process
S430: pattern alignment process
S440: bonding bonding process

Claims

A process in which an integrated circuit chip to which an anisotropic conductive film is adhered is loaded on a whole of a bonding surface on which patterned connection terminal patterns are formed;
Loading a circuit board on which a line pattern is formed into a chamber;
Aligning the connection terminal pattern of the integrated circuit chip so as to match the line pattern of the circuit board; And
And joining the bonding surfaces to which the anisotropic conductive film is attached to a circuit board having a line pattern aligned with the connection terminal pattern
The method comprising the steps of: applying a predetermined pressure between the integrated circuit chip and the circuit board in the process of bonding the integrated circuit chip and the circuit board; maintaining the temperature in the chamber where the integrated circuit chip and the circuit board are located,
Wherein the connection terminal pattern has a structure in which a plurality of patterns are arranged in a line,
Wherein a size and a temperature of the pressure are determined in inverse proportion to an interval between the patterns constituting the connection terminal pattern.

delete

The connector according to claim 1,
Wherein the width of each pattern is 70 占 퐉 or more and the distance between the patterns is 20 占 퐉 or more.

The method according to claim 1,
Wherein the anisotropic conductive film is an ACF (Anisotropic Conductive Film) film, and the total area of the anisotropic conductive film has a larger area than that of the integrated circuit chip.