JP4620368B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, a manufacturing method of a semiconductor equipment, particularly comprising a channel connection region.

In SiC (silicon carbide) field effect transistors (MOSFETs) for power applications, it is effective to shorten the channel length in order to reduce the on-resistance. Here, the SiC field effect transistor is formed in an n ⁻ type drift region formed on the SiC substrate, a p type base region formed in a surface layer region of the n ⁻ type drift region, and the p type base region. N ⁺ source region. The channel length is defined by the length of the region sandwiched between the source region and the drift region in the surface layer portion of the base region below the gate electrode. In the conventional manufacturing method, after forming the source region in the drift region, the base region is formed in a separate process. Therefore, the channel length needs to be designed to be longer than the minimum value by the mask shift between the mask for forming the source region and the mask for forming the base region.

  In the SiC field effect transistor disclosed in Patent Document 1, a source region and a low-resistance channel connection region are formed in a surface layer portion of an epitaxial layer formed on a SiC substrate. A region sandwiched between the source region and the channel connection region is defined as a channel region. The source region and the channel connection region are simultaneously formed by ion-implanting n-type impurities using a mask having openings in the source region and the channel connection region. Therefore, the channel length is defined by a mask that forms the source region and the channel connection region at the same time, and the mask deviation from the mask for forming the base region is irrelevant. As a result, the channel length can be minimized to the mask processing accuracy. By minimizing the channel length, a SiC field effect transistor with low on-resistance is realized.

JP 2003-318397 A

However, the impurity concentration in the source region usually needs to be as high as 10 ¹⁹ cm ⁻³ . When the source region and the channel connection region are formed at the same time, the impurity concentration of the channel connection region becomes the same high concentration as that of the source region. Since the channel connection region has a high concentration, when a high voltage is applied to the drain electrode, the depletion layer does not spread under the gate oxide film, and a high electric field of 4 MV / cm or more is applied to the gate oxide film. When an electric field of 4 MV / cm or more is applied to the gate oxide film, a tunnel current is generated and the gate oxide film is destroyed. As described above, the breakdown voltage of the semiconductor device is limited by the breakdown voltage of the gate oxide film, and there is a problem that it decreases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method capable of manufacturing a field effect transistor with a minimized channel length without a problem of a decrease in breakdown voltage of a gate oxide film. .

A method for manufacturing a semiconductor device according to the present invention includes a wide band gap semiconductor substrate having a wider band gap than silicon, a semiconductor layer formed on a main surface of the semiconductor substrate, and a first layer formed on a surface layer portion of the semiconductor layer. A conductive-type current output region; and a first-conductivity-type channel connection region formed in the surface layer portion of the semiconductor layer apart from the current output region, and sandwiched between the current output region and the channel connection region A region of the semiconductor layer is defined as a channel region, and is formed on the surface layer portion of the semiconductor layer including the current output region so as to extend to the channel connection region, and has a second conductivity deeper than the depth of the current output region. Type impurity region, a gate electrode formed on the channel region via a gate oxide film, a current output electrode connected to the current output region, and the semiconductor substrate Further comprising a current input electrode formed on the back surface, the impurity concentration of the channel connection region is a method for manufacturing the semiconductor device with low than the impurity concentration of the current output area. The method for manufacturing a semiconductor device according to the present invention includes: (a) a first opening having an opening corresponding to the channel connection region and an opening corresponding to the current output region on the semiconductor layer; Forming a first mask having two openings; (b) forming a third mask so as to close the second opening and not close the first opening; ) Forming the channel connection region by ion implantation using the first mask and the third mask; and (d) closing the first opening and closing the second opening. And (e) forming the current output region by ion implantation using the first mask and the second mask. And

In the method of manufacturing a semiconductor device according to the present invention, after the channel connection region is formed, the channel connection region portion of the mask is closed to prevent impurities from being implanted into the channel connection region when the current output region is formed. ing. Therefore, the impurity concentration in the channel connection region can be set to an optimum value lower than that in the current output region. Further, when a high voltage is applied to the current input electrode in the OFF state of the semiconductor device, since the impurity concentration in the channel connection region is low, the extension of the depletion layer is larger than when the impurity concentration in the channel connection region is high. Therefore, the voltage applied to the gate oxide film can be reduced. Furthermore, as a result of ion implantation in the current output region and the channel connection region being performed in different steps, the impurity concentrations in the power output region and the channel connection region can be set to optimum values completely independently.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a power-use semiconductor device according to Embodiment 1 of the present invention. High concentration n-type (hereinafter simply referred to as n ⁺ ) SiC substrate (semiconductor substrate) 1 is epitaxially grown on a low concentration n-type (hereinafter simply referred to as n ⁻ ) drift region (semiconductor layer) ) 2 is formed. Here, the SiC substrate 1 is a wide band gap semiconductor substrate having a wider band gap than silicon.

A channel connection region 4 that is an n-type (first conductivity type) impurity layer is formed in a predetermined region of the surface layer portion of the drift region 2. An n ⁺ type source region (current output region) 3 is formed in a predetermined region of the surface layer portion of the drift region 2. A channel region 11 is formed between the channel connection region 4 and the source region 3. Here, the impurity concentration of the channel connection region 4 is formed lower than the impurity concentration of the source region 3. The surface layer portion of the channel region 11 is an n-type impurity layer for adjusting the gate voltage as will be described later. The impurity concentration of the channel connection region 4 is formed higher than the impurity concentration of this impurity layer.

  A base region (impurity region) 5 is formed to extend to the channel connection region 4 in the surface layer portion of the drift region 2 including the source region 3. The depth of the base region 5 is formed deeper than the depth of the source region 3. The base region 5 is a p-type (second conductivity type) impurity layer. A gate oxide film 6 is formed on the drift region 2. A gate electrode 7 is formed on the channel region 11 via a gate oxide film 6. An interlayer insulating film 8 is formed so as to cover the gate electrode 7. The interlayer oxide film 8 and the gate oxide film 6 are provided with contact holes 12 for making contact with the source region 3. The source electrode 9 is formed in the contact hole 12 and on the interlayer insulating film 8 so as to be in contact with the source region 3. A drain electrode (current input electrode) 10 is formed on the back surface of the SiC substrate 1.

Next, with reference to FIGS. 2 to 6, a method for manufacturing the SiC field effect semiconductor device according to the present embodiment will be described. First, referring to FIG. 2, an n ⁻ type drift region 2 is formed on an n ⁺ type SiC substrate 1 by an epitaxial growth method according to a known technique. The impurity concentration of the drift region 2 is preferably 10 ¹⁴ to 10 ¹⁸ cm ⁻³ , more preferably 5 × 10 ^{15 to} 1.5 × 10 ¹⁶ cm ⁻³ . The thickness of the drift region 2 is preferably 1 to 100 μm, more preferably 10 to 15 μm.

The basis of the thickness and impurity concentration of the drift region 2 will be described. FIG. 7 shows the breakdown voltage Vb (vertical axis) of the semiconductor device realized with respect to the impurity concentration N (horizontal axis) of the drift region 2 and the breakdown voltage Vb when a voltage is applied between the source and drain. The required drift region thickness d (vertical axis) is shown. Without special contrivance, the impurity concentration of the drift region 2 that is usually obtained is 10 ¹⁴ to 10 ¹⁸ cm ⁻³ . Further, assuming that the voltage range in which the characteristics of the SiC field effect transistor can be utilized is 600 to 2000 V, the impurity concentration of the drift region 2 is set to 5 × 10 ^{15 to} 1.5 × 10 ¹⁶ cm ⁻ as a preferable numerical range from FIG. ^{3. The} film thickness is selected to be 10-15 μm.

In the process shown in FIG. 2, a mask material 21 is formed at a predetermined position on the drift region 2 by photolithography. The base region 5 is formed by ion-implanting p-type impurity ions such as aluminum ions using the mask material 21. The impurity concentration of the base region 5 is preferably 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ , more preferably 7 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ . The depth of the base region 5 is preferably 0.3 to 3 μm, more preferably 0.5 to 1 μm. Further, the base region 5 is prepared by determining the implantation amount and the implantation energy so that the impurity concentration near the surface is preferably about 10 ¹⁶ cm ⁻³ or less.

The impurity concentration of the base region 5 is determined so that a depletion layer generated at the interface between the drift region 2 and the base region 5 does not penetrate the base region 5 when a voltage (600 to 2000 V) is applied. It has been found from calculations and experiments that an impurity concentration of about 2 × 10 ¹³ cm ⁻² is necessary for the depletion layer not to penetrate the base region 5. In the present embodiment, the impurity concentration is selected from 7 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ and the thickness is selected from 0.5 to 1 μm in consideration of the thickness of the source region and the like. Further, the impurity concentration in the vicinity of the surface of the base region 5 needs to be lowered so as not to cause a problem in the impurity concentration control (doping control) of the channel region 11. Therefore, it is set to about 10 ¹⁶ cm ⁻³ or less.

Next, in a step shown in FIG. 3, a mask material 22 (first mask) is formed. The mask material 22 has a shape having an opening (first opening) corresponding to the source region 3 and an opening (second opening) corresponding to the channel connection region 4. Further, as the mask material 22, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) is formed by a CVD method, or a metal film such as an aluminum film (Al) is formed by a sputtering method, It is formed into a desired shape using a photoengraving technique.

The distance between the opening corresponding to the source region 3 and the opening corresponding to the channel connection region 4 is 0.2 μm when a MOSFET having a breakdown voltage of 1 kV or more is formed. This interval becomes the channel length of the semiconductor device of the first embodiment. Here, from the viewpoint of reducing the ON resistance, the channel length should be as short as possible. However, punch-through tends to occur when the channel length is shortened. When a MOSFET having a breakdown voltage of 1 kV or more is formed, the optimum impurity concentration of the base region 5 is about 5 × 10 ¹⁷ cm ⁻³ . In this case, when a voltage of 1 kV is applied between the source and the drain, the depletion layer width under the channel region 11 is about 0.2 μm. Therefore, the channel length needs to be at least 0.2 μm or more.

Then, for example, nitrogen ions are ion-implanted using the mask material 22 to form the channel connection region 4 that is an n-type impurity layer. The impurity concentration of the channel connection region 4 is preferably 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ , more preferably 1 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ . The channel connection region 4 is formed by determining the implantation amount and the implantation energy so that the depth of the channel connection region 4 is preferably 0.1 to 1 μm, more preferably 0.2 to 0.4 μm. At this time, ions are also implanted into the source region 3 at the same time, but there is no problem because the impurity concentration of the n ⁺ -type source region 3 is higher by one digit or more.

Here, the range of the impurity concentration of the channel connection region 4 will be described. FIG. 8 shows the relationship between the impurity concentration under the gate oxide film 6 (horizontal axis) and the maximum electric field value in the gate oxide film when a source-drain voltage is applied without applying a voltage to the gate. FIG. Here, the voltage between the source and the drain is assumed to be 600 V to 2000 V as a voltage range in which the SiC field effect transistor is used by making use of the characteristics in the power device field. 8 that the maximum electric field value applied to the gate oxide film 6 can be reduced to 4 MV / cm or less by setting the impurity concentration to 2 × 10 ¹⁷ cm ⁻³ or less. The lower limit of the impurity concentration is set to be at least higher than the impurity concentration of the channel region 11 described later. Otherwise, even if a gate voltage for forming a channel is applied to the channel region 11, no current flows through the portion of the channel connection region 4 extending to the base region 5.

Next, in the process shown in FIG. 4, a mask material 23 (second mask) is formed by a photoengraving technique so as to close the opening of the mask material 22 corresponding to the channel connection region 4. . In the current exposure apparatus, it is easy to set the gap between the masks to 0.2 μm or less. Therefore, even if the distance between the openings of the mask material 22 is 0.2 μm, the mask material 23 corresponds to the channel connection region 4. It is possible to close only the opening. Using the mask material 23 and the mask material 22, for example, nitrogen ions are implanted to form the n ⁺ -type source region 3. The impurity concentration of the source region 3 is preferably 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , more preferably 5 × 10 ^{18 to} 3 × 10 ¹⁹ cm ⁻³ . The depth of the source region 3 is preferably 0.1 to 1 [mu] m, more preferably 0.2 to 0.4 [mu] m.

Here, the impurity concentration of the source region 3 is preferably as high as possible from the viewpoint of obtaining good ohmic contact with the electrode. However, crystal defects are generally generated by ion implantation of impurity ions at a high concentration. In order to prevent the occurrence of crystal defects, the maximum value is about 10 ¹⁹ cm ⁻³ as the impurity concentration. Therefore, considering the impurity concentration of 5 × 10 ^{18 to} 3 × 10 ¹⁹ cm ⁻³ and the thickness of the surface portion removed in the manufacturing process after ion implantation, the film thickness is selected to be 0.2 to 0.4 μm. It is out.

  Next, in the process shown in FIG. 5, a mask material 24 is formed by photolithography. The mask material 24 is formed so as to open the channel connection region 4 and the channel region 11. For example, nitrogen ions are ion-implanted using the mask material 24. This ion implantation is for controlling a gate voltage at which a channel is formed in the channel region 11 and the semiconductor device is turned on. Here, if the injection amount is too large, it becomes a normally-on field effect transistor that is turned on even when the gate voltage is 0 V, and cannot be used. On the other hand, when the injection amount is too small, the gate voltage for turning on becomes too high.

In the present embodiment, the impurity concentration of the channel region 11 is preferably 5 × 10 ^{15 to} 5 × 10 ¹⁷ cm ⁻³ , more preferably 1 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ . It is formed at a concentration lower than the impurity concentration. The depth of the channel region 11 is preferably 0.1 to 1 [mu] m, more preferably 0.2 to 0.4 [mu] m, and the implantation amount and energy are determined. FIG. 9 shows the relationship between the thickness d (horizontal axis) and the impurity concentration N (vertical axis) of the channel region 11 where no current flows between the source and drain (normally off) when no voltage is applied to the gate. FIG. Here, FIG. 9 assumes that the interface between the gate oxide film 6 and the channel region 11 is in an ideal state (interface state, no fixed charge). In the present embodiment, in consideration of the influence of the interface state and the fixed charge, the impurity concentration is set to be lower than the impurity concentration of the channel connection region 4 out of 1 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^−3. The thickness is selected to be 0.2 to 0.4 μm.

  Next, in the step shown in FIG. 6, a gate oxide film 6 is formed on the drift region 2 by a thermal oxidation method or the like. Then, a gate electrode 7 made of, for example, polysilicon is formed on the gate oxide film 6. The gate electrode 7 is formed so as to face at least the channel region 11 and the channel formation region 4. Next, an interlayer insulating film 8 made of, for example, a CVD oxide film is formed so as to cover the gate electrode 7 and the gate oxide film 6. Then, a contact hole 12 is opened so as to make contact with the source region 3. At this time, the interlayer insulating film 8 and the gate oxide film 6 are opened so as to be in contact with the gate electrode 7 and the base region 5 (not shown).

  A wiring and an external output pad (not shown) are formed on the interlayer insulating film 8 by, for example, aluminum wiring so that a voltage can be applied to the source region 3 and the gate electrode 7. At this time, the source region 3 and the base region 5 are connected by aluminum wiring so as to have the same potential. Alternatively, an opening of the interlayer insulating film 8 is provided in an adjacent portion of the source region 3 and the base region 5 and connected by the same electrode. On the back surface of the SiC substrate 1, for example, nickel and gold are formed to form the drain electrode 10, and the structure as shown in FIG. 1 is formed.

  In this embodiment, an example in which p-type or n-type impurity layers are formed by ion implantation in the order of mask materials 21, 22, 23, and 24 has been described. However, the order of ion implantation may be different. .

  Next, the operation of the semiconductor device according to the present embodiment will be described. First, the channel region 11 is depleted by the built-in potential with the base region 5. Therefore, even when a high voltage is applied between the source electrode 9 and the drain electrode 10, when no voltage is applied to the gate electrode 7, a channel is not formed, so electrons do not flow and the state is OFF. When a positive voltage is applied to the gate electrode 7, the channel region 11 becomes an electron accumulation layer, and electrons flow from the source region 3 through the channel region 11 -channel connection region 4 -drift region 2 -SiC substrate 1 -drain electrode 10. Thus, the semiconductor device is turned on.

  As described above, after the channel connection region 4 is formed, the opening of the channel connection region 4 portion of the mask material 22 is closed to prevent impurities from being implanted into the channel connection region 4 when the source region 3 is formed. ing. Therefore, the impurity concentration of the channel connection region 4 can be set to an optimum value lower than that of the source region 3. When a high voltage is applied to the drain electrode 10 in a state where the semiconductor device is OFF, the impurity concentration of the channel connection region 4 is low, so that the depletion layer extends more than when the impurity concentration of the channel connection region 4 is high. Therefore, the voltage applied to the gate oxide film 6 can be reduced.

In the present embodiment, the impurity concentration of the channel connection region 4 is in the range of 1 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ . As a result, even when a high electric field is applied to the drain electrode 10, the electric field applied to the gate oxide film 6 can be weakened to 4 MV / cm or less. As a result, generation of a tunnel current can be suppressed, so that a high voltage can be applied to the drain electrode.

  Note that when the conductor device is in the ON state, the gate voltage is applied to the gate electrode 4, so the voltage between the gate electrode 4 and the drain electrode 10 is low. Since the voltage applied to the gate oxide film 6 is lowered, there is no problem that a high voltage is applied to the gate oxide film 6. Further, the present embodiment can be applied to other power devices such as an IGBT (Insulated Gate Bipolar Transistor).

Embodiment 2. FIG.
10 to 12 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present embodiment. In the process shown in FIG. 10, as in the process shown in FIG. 2 of the first embodiment, ion implantation is performed using the mask material 21 to form the base region 5.

In the process shown in FIG. 11, first, a mask material 22 is formed by photolithography. The mask material 22 has a shape in which portions corresponding to the source region 3 and the channel connection region 4 are opened. Further, as the mask material 22, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) is formed by a CVD method, or a metal film such as an aluminum film (Al) is formed by a sputtering method, It is formed into a desired shape using a photoengraving technique. After forming the mask material 22, a mask material 25 (third mask) is formed on the mask material 22 so as to close the opening of the source region 3. Then, ion implantation is performed only on the channel connection region 4 using the mask material 22 and the mask material 25. After forming the channel connection region 4 by ion implantation, only the mask material 25 is removed.

  In the step shown in FIG. 12, the mask material 23 is formed on the mask material 22 so as to close only the opening of the channel connection region 4. Then, ion implantation is performed only on the source region 3 using the mask material 22 and the mask material 23 to form the source region 3. Then, after removing the mask materials 22 and 23, the semiconductor device is completed in accordance with a normal process as in the first embodiment.

  Since it is configured as described above, this embodiment also has the same effect as that of the first embodiment. Further, in the present embodiment, ion implantation of the source region 3 and the channel connection region 4 is performed in different steps. As a result, the impurity concentrations of the source region 3 and the channel connection region 4 can be set to optimum values completely independently.

  The order of ion implantation is not limited to the above order. For example, the channel connection region 4 may be formed after the source region 3 is formed.

Embodiment 3 FIG.
FIG. 13 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment. In the present embodiment, an n-type SiC channel epitaxial layer (epitaxial layer) 31 formed on channel region 11 is further provided. The impurity concentration of the SiC channel epitaxial layer (hereinafter simply referred to as channel epilayer) 31 is 5 × 10 ¹⁵ to 2 × 10 ¹⁷ cm ⁻³ and the thickness is 0.1 to 2 μm.

  Next, a manufacturing method will be described. The manufacturing process is similarly performed up to the step shown in FIG. 5 of the first embodiment. Then, after the step shown in FIG. 5, an epitaxial growth film 30 is formed on the drift layer 2 by an epitaxial growth method (see FIG. 14). Then, the epitaxial growth film 30 is shaped using a photoengraving technique so as to cover the channel connection region 4 and the source region 11, and a channel epilayer 31 is formed. Thereafter, the gate oxide film 6, the gate electrode 7 and the like are formed according to the steps described in the first embodiment, and the semiconductor device is completed.

  Since it is configured as described above, this embodiment has the same effect as that of the first embodiment. Furthermore, in this embodiment, since electrons flow through the high-quality channel epi layer 31, the electron mobility can be improved and the ON resistance can be lowered. Further, since the gate voltage is determined by the concentration and thickness of the channel epi layer 31, an ion implantation step (see FIG. 5) for controlling the gate voltage can be omitted.

1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. It is a figure which shows the thickness of the drift area | region required when the proof pressure of the semiconductor device implement | achieved with respect to the impurity concentration of a drift area | region, and the proof pressure are applied. It is a figure which shows the relationship between the impurity concentration under a gate oxide film, and the maximum electric field value applied to a gate oxide film. It is a figure which shows the relationship between the thickness of a channel area | region and impurity concentration which will be in the state which does not flow between source-drain in the state which does not apply a voltage to a gate. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment.

Explanation of symbols

1 SiC substrate, 2 drift region, 3 source region, 4 channel connection region, 5 base region, 11 channel region, 31 channel epi layer.

Claims (2)

Wide band gap semiconductor substrate with a wider band gap than silicon,
A semiconductor layer formed on the main surface of the semiconductor substrate;
A current output region of a first conductivity type formed in a surface layer portion of the semiconductor layer;
A channel connection region of a first conductivity type formed in a surface layer portion of the semiconductor layer apart from the current output region;
A region of the semiconductor layer sandwiched between the current output region and the channel connection region is defined as a channel region,
An impurity region of a second conductivity type formed on the surface layer portion of the semiconductor layer including the current output region, extending to the channel connection region, and deeper than the depth of the current output region;
A gate electrode formed on the channel region via a gate oxide film;
A current output electrode connected to the current output region;
A current input electrode formed on the back surface of the semiconductor substrate;
Further comprising
An impurity concentration of the channel connection region is a manufacturing method of a semiconductor device lower than an impurity concentration of the current output region,
(A) forming a first mask having a first opening having a region corresponding to the channel connection region and a second opening having a region corresponding to the current output region on the semiconductor layer; When,
(B) forming a third mask so as to close the second opening and not close the first opening;
(C) forming the channel connection region by ion implantation using the first mask and the third mask;
(D) forming a second mask so as to close the first opening and not close the second opening;
(E) forming the current output region by ion implantation using the first mask and the second mask;
A method for manufacturing a semiconductor device, comprising: Wide band gap semiconductor substrate with a wider band gap than silicon,
A semiconductor layer formed on the main surface of the semiconductor substrate;
A current output region of a first conductivity type formed in a surface layer portion of the semiconductor layer;
A channel connection region of a first conductivity type formed in a surface layer portion of the semiconductor layer apart from the current output region;
A region of the semiconductor layer sandwiched between the current output region and the channel connection region is defined as a channel region,
An impurity region of a second conductivity type formed on the surface layer portion of the semiconductor layer including the current output region, extending to the channel connection region, and deeper than the depth of the current output region;
A gate electrode formed on the channel region via a gate oxide film;
A current output electrode connected to the current output region;
A current input electrode formed on the back surface of the semiconductor substrate;
An epitaxial layer of a first conductivity type formed on the channel region;
Further comprising
An impurity concentration of the channel connection region is a manufacturing method of a semiconductor device lower than an impurity concentration of the current output region,
(A) forming a first mask having a first opening having a region corresponding to the channel connection region and a second opening having a region corresponding to the current output region on the semiconductor layer; When,
(B) forming a third mask so as to close the second opening and not close the first opening;
(C) forming the channel connection region by ion implantation using the first mask and the third mask;
(D) forming a second mask so as to close the first opening and not close the second opening;
(E) forming the current output region by ion implantation using the first mask and the second mask;
(F) forming an epitaxial layer so as to cover the channel region after forming the channel connection region and the current output region;
A method for manufacturing a semiconductor device, comprising:

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