JP6468112B2 - Silicon carbide semiconductor device - Google Patents

Description

  The present disclosure relates to a silicon carbide semiconductor device.

  Japanese Patent Laying-Open No. 2013-340007 (Patent Document 1) discloses a silicon carbide epitaxial wafer characterized by no short step bunching.

JP 2013-340007 A

  An object of the present disclosure is to provide a silicon carbide semiconductor device with improved long-term reliability.

  A silicon carbide semiconductor device according to one embodiment of the present disclosure includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a main surface. The gate insulating film is provided on the main surface. The silicon carbide substrate has a first impurity region, a drift region having the same conductivity type as that of the first impurity region and physically separated from the first impurity region, a gate insulating film, and a first impurity region And a second impurity region configured to be electrically conductive between the first region and the drift region. The second impurity region has a lower lattice defect density than the first impurity region. The main surface extends in one direction along the main surface, the width in one direction is at least twice the width in the direction perpendicular to one direction, and the maximum depth from the main surface is 10 nm or less. Grooves are formed.

  According to the above, a silicon carbide semiconductor device with improved long-term reliability is provided.

It is a schematic sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows a part of area | region II in FIG. 1 is a schematic plan view showing a part of a silicon carbide substrate included in a silicon carbide semiconductor device according to an embodiment. 1 is a schematic plan view showing a part of a silicon carbide substrate included in a silicon carbide semiconductor device according to an embodiment. 3 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to the present embodiment. It is a flowchart which shows roughly the silicon carbide substrate preparation process which concerns on this embodiment. It is a schematic side view which shows the structure of an epitaxial growth apparatus. It is a schematic sectional drawing which shows the cross section along line segment VIII-VIII in FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the 11th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment.

[Description of Embodiment]
(1) Silicon carbide semiconductor device 1 according to one aspect of the present disclosure includes silicon carbide substrate 10 and gate insulating film 15. Silicon carbide substrate 10 has a main surface 10A. Gate insulating film 15 is provided on main surface 10A. Silicon carbide substrate 10 faces first impurity region 14, drift region 12 having the same conductivity type as first impurity region 14 and physically separated from first impurity region 14, and gate insulating film 15. And the second impurity region 2 configured to be electrically conductive between the first impurity region 14 and the drift region 12. The second impurity region 2 has a lattice defect density lower than that of the first impurity region 14. The main surface 10A extends in one direction D along the main surface 10A, and the width W2 in the one direction D is more than twice the width W3 in the direction perpendicular to the one direction D, and from the main surface 10A. A groove portion 20 having a maximum depth D2 of 10 nm or less is formed.

  When a silicon carbide layer is formed by epitaxial growth on a silicon carbide single crystal substrate, a minute pit portion 30 (see FIGS. 2 and 4) may be formed on the main surface of the silicon carbide layer. The pit portion is formed due to threading dislocation inherited from the silicon carbide single crystal substrate to the silicon carbide layer, and is a recess having a depth of about several tens of nm. The inventors have increased the variation in the thickness of the gate insulating film formed on the surface of the pit portion formed on the surface of the silicon carbide layer. It was found that long-term reliability was reduced.

  The present inventors have found that the formation of pit portions can be suppressed under specific epitaxial growth conditions. According to the growth conditions, while the pit portion is reduced, a large number of groove portions 20 (see FIGS. 2 and 3) that are shallower than the pit portion and extend in one direction are formed. However, since the groove portion is shallower than the pit portion, it has been found that the influence on the variation in the thickness of the gate insulating film is smaller than that of the pit portion.

  In silicon carbide semiconductor device 1 of (1) above, main surface 10A extends in one direction D along main surface 10A, and width W2 in one direction D is 2 of width W3 in the direction perpendicular to one direction D. Groove portion 20 is formed that is twice or more and has a maximum depth D2 from main surface 10A of 10 nm or less. According to silicon carbide semiconductor device 1 in which groove portion 20 is formed, variation in film thickness of gate insulating film 15 can be reduced as compared with a conventional silicon carbide semiconductor device in which a large number of pit portions are formed. Therefore, in the silicon carbide semiconductor device of the above (1), long-term reliability is improved as compared with the conventional silicon carbide semiconductor device. In addition, when the second impurity region 2 that functions as a channel is formed by the epitaxial growth method, the channel mobility is higher than when it is formed by ion implantation.

  The shape of the “groove” can be specified by observing the first main surface 10A using a predetermined defect inspection apparatus. For example, after removing the gate insulating film 15 from the first main surface 10A, dimensions such as the width and depth of the groove 20 formed in the first main surface 10A are measured by an AFM (Atomic Force Microscope). A sample subjected to AFM measurement is used as a standard sample, and a plurality of standard samples are prepared.

  As the defect inspection apparatus, for example, WASAVI series “SICA 6X” manufactured by Lasertec Corporation can be used (objective lens: × 10). The threshold value of the detection sensitivity of the defect inspection apparatus is determined using the standard sample. Thereby, the shape of the “groove part” formed in the sample to be measured can be quantitatively evaluated by using the defect inspection apparatus. Note that the gate insulating film can be removed by, for example, hydrofluoric acid diluted with pure water, or a mixed solution of ammonium fluoride and hydrofluoric acid using ammonium fluoride as a buffer solution. A typical concentration range of hydrofluoric acid is 1% or more and 55% or less.

  The lattice defect density of the second impurity region 2 and the first impurity region 14 can be measured by using, for example, TEM (Transmission Electron Microscope). For example, the lattice defect density of the second impurity region 2 and the first impurity region 14 is measured by observing the cross section of the second impurity region 2 and the first impurity region 14 with a TEM from the direction parallel to the first main surface 10A. can do.

(2) In silicon carbide semiconductor device 1 according to (1) above, the surface density of groove 20 in main surface 10A may be 10 / mm ² or more. In addition, the surface density of the groove part 20 can be measured using the said defect inspection apparatus.

  (3) In silicon carbide semiconductor device 1 according to (1) or (2) above, the conductivity type of second impurity region 2 is either n-type or p-type. When the conductivity type is n-type, second impurity region 2 may contain a nitrogen atom. When the conductivity type is p-type, second impurity region 2 may contain aluminum atoms.

  (4) In silicon carbide semiconductor device 1 according to any one of (1) to (3), the thickness of second impurity region 2 in the direction perpendicular to main surface 10A is not less than 0.1 μm and not more than 3 μm. May be.

(5) In silicon carbide semiconductor device 1 according to any of (1) to (4) above, the impurity concentration of second impurity region 2 may be 1 × 10 ¹⁶ cm ⁻³ or more.

(6) In silicon carbide semiconductor device 1 according to any of (1) to (5) above, the impurity concentration of drift region 12 may be less than 1 × 10 ¹⁶ cm ⁻³ .

  (7) In silicon carbide semiconductor device 1 according to any of (1) to (6) above, groove portion 20 includes first groove portion 21 and second groove portion 22 connected to first groove portion 21. May be included. The first groove portion 21 may be formed at one end portion of the groove portion 20 in the one direction D. The second groove 22 extends along the one direction D from the first groove 21 and reaches the other end opposite to the one end, and the depth D1 from the main surface 10A is the first depth D1. It may be smaller than the maximum depth of the groove.

[Details of the embodiment]
Embodiments will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

[Silicon carbide semiconductor device]
First, a configuration of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example of a silicon carbide semiconductor device according to the present embodiment will be described.

  MOSFET 1 according to the present embodiment mainly includes silicon carbide substrate 10, gate insulating film 15, gate electrode 27, source electrode 16, drain electrode 3, source pad electrode 19, and interlayer insulating film 4. Have. Silicon carbide substrate 10 mainly includes a silicon carbide single crystal substrate 11 and a silicon carbide layer 17 provided on silicon carbide single crystal substrate 11. Silicon carbide substrate 10 has a first main surface 10A and a second main surface 11B opposite to the first main surface 10A. Silicon carbide layer 17 constitutes first main surface 10A. Silicon carbide single crystal substrate 11 constitutes second main surface 11B. Silicon carbide single crystal substrate 11 has second main surface 11B and third main surface 11A opposite to second main surface 11B. Silicon carbide layer 17 mainly includes drift region 12, body region 13, source region 14, and contact region 18.

  Source region 14 includes an n-type impurity such as nitrogen (N) or phosphorus (P) and has an n-type conductivity type. Source region 14 constitutes a part of first main surface 10 </ b> A of silicon carbide layer 17, for example. Source region 14 may be separated from drift region 12 by body region 13. Each of the side surface and the bottom surface of the source region 14 is in contact with the body region 13. The concentration of the n-type impurity included in the source region 14 may be higher than the concentration of the n-type impurity included in the drift region 12.

Drift region 12 is an impurity region containing an n-type impurity such as nitrogen (N) or phosphorus (P) and having an n-type (first conductivity type) conductivity type. Drift region 12 has the same conductivity type as source region 14. The drift region 12 is physically separated from the source region 14. The concentration of the n-type impurity in the drift region 12 is, for example, less than 1 × 10 ¹⁶ cm ⁻³ , preferably less than 5 × 10 ¹⁵ cm ⁻³ , and more preferably less than 2 × 10 ¹⁵ cm ⁻³ . The lower limit of the concentration of the n-type impurity in the drift region 12 is, for example, 1 × 10 ¹³ cm ⁻³ .

  The drift region 12 is provided on the first main drift surface portion 12a on the third main surface 11A, and on the first drift region portion 12a, and is seen in a sectional view (viewed from a direction parallel to the first main surface 10A). And a second drift region portion 12b sandwiched between the body regions 13 in the visual field). The concentration of the n-type impurity in the first drift region portion 12a may be the same as or different from the concentration of the n-type impurity in the second drift region portion 12b.

  Body region 13 is an impurity region including a p-type impurity such as aluminum (Al) or boron (B) and having a p-type (second conductivity type) conductivity type. Body region 13 is in contact with both first drift region portion 12a and second drift region portion 12b. The body region 13 has a first body region portion 13a and a second body region portion 13b provided on the first body region portion 13a. First body region portion 13a is a region formed by, for example, epitaxial growth. Second body region portion 13b is a region formed by ion implantation, for example. The lattice defect density of the first body region portion 13a is lower than the lattice defect density of the second body region portion 13b. The first body region portion 13a is in contact with both the first drift region portion 12a and the second drift region portion 12b. The second body region portion 13b is in contact with the second drift region portion 12b.

  Second impurity region 2 is an impurity region containing an n-type impurity such as nitrogen (N) or phosphorus (P) and having an n-type (first conductivity type) conductivity type. The second impurity region 2 faces the gate insulating film 15. The second impurity region 2 is configured to be electrically conductive between the source region 14 and the drift region 12. That is, the second impurity region 2 is a region where a channel connecting the source region 14 and the drift region 12 is formed when a current flows between the source electrode 16 and the drain electrode 3. The source region 14 is formed by ion implantation, for example. The second impurity region 2 is formed by epitaxial growth. The second impurity region 2 has a lattice defect density lower than that of the source region 14.

  The conductivity type of the second impurity region 2 may be either n-type or p-type. When the conductivity type of the second impurity region 2 is the same as that of the drift region 12 and the source region 14, the second impurity region 2 becomes an accumulation channel. On the other hand, when the conductivity type of the second impurity region 2 is different from the conductivity types of the drift region 12 and the source region 14, the second impurity region 2 becomes an inverted channel. When the conductivity type is n-type, second impurity region 2 may contain a nitrogen atom. When the conductivity type is p-type, second impurity region 2 may contain aluminum atoms. Second impurity region 2 may be sandwiched between drift region 12 and gate insulating film 15 in a direction perpendicular to first main surface 10A. Similarly, the second impurity region 2 may be sandwiched between the body region 13 and the gate insulating film 15 in a direction perpendicular to the first main surface 10A. Second impurity region 2 may be sandwiched between body regions 13 in a direction parallel to first main surface 10A. Second impurity region 2 is in contact with source region 14, second body region portion 13 b, second drift region portion 12 b, and gate insulating film 15.

As shown in FIG. 1, the thickness T of the second impurity region 2 in the direction perpendicular to the first major surface 10A is, for example, not less than 0.1 μm and not more than 3 μm. Preferably, the thickness T is not less than 0.1 μm and not more than 1 μm. The thickness T may be smaller than the thickness of the source region 14. Second impurity region 2 constitutes a part of first main surface 10A. The concentration of the n-type impurity in the second impurity region 2 is, for example, 1 × 10 ¹⁶ cm ⁻³ or more, preferably 2 × 10 ¹⁶ cm ⁻³ or more, more preferably 5 × 10 ¹⁶ cm ⁻³ or more. is there. The upper limit of the concentration of the n-type impurity in the second impurity region 2 is, for example, 1 × 10 ¹⁹ cm ⁻³ .

  Contact region 18 includes a p-type impurity such as aluminum (Al) or boron (B) and has a p-type. Contact region 18 constitutes a part of first main surface 10A. The contact region 18 penetrates the source region 14 and connects the source electrode 16 and the body region 13. The concentration of the p-type impurity included in the contact region 18 may be higher than the concentration of the p-type impurity included in the body region 13.

  Gate insulating film 15 is provided on first main surface 10A. Gate insulating film 15 is in contact with second impurity region 2 and source region 14 on first main surface 10A. Gate insulating film 15 is an oxide film made of a material such as silicon dioxide. The thickness of the gate insulating film 15 is, for example, not less than 45 nm and not more than 65 nm. The gate electrode 27 is made of a conductor such as polysilicon doped with impurities and aluminum. The gate electrode 27 is provided on the gate insulating film 15 and is disposed so as to face the second impurity region 2 and the source region 14. Interlayer insulating film 4 is made of, for example, a material containing silicon dioxide, and is formed to surround gate electrode 27. The interlayer insulating film 4 electrically insulates the gate electrode 27 and the source electrode 16 from each other.

The source electrode 16 is provided on the first main surface 10A. Source electrode 16 is in contact with both source region 14 and contact region 18 on first main surface 10A. Preferably, the source electrode 16 is in ohmic contact with the source region 14. More preferably, the source electrode 16 is in ohmic contact with the contact region 18. The source electrode 16 is, for example, nickel silicon (Ni _x Si _y), titanium silicon (Ti _x Si _y), is composed of a material such as aluminum silicon (Al _x Si _y) or titanium aluminum silicon (Ti _x Al _y Si _z) ing. In the above composition formula, x, y, and z are numbers greater than zero.

  The source pad electrode 19 is formed so as to cover the source electrode 16 and the interlayer insulating film 4. The source pad electrode 19 is electrically connected to the source region 14 via the source electrode 16 made of, for example, a material containing aluminum (Al).

  Drain electrode 3 is formed in contact with second main surface 11B of silicon carbide single crystal substrate 11. Drain electrode 3 is made of a material that can be in ohmic contact with n-type silicon carbide, such as nickel silicon. The drain electrode 3 may be made of the same material as that of the source electrode 16. Drain electrode 3 is electrically connected to silicon carbide single crystal substrate 11.

[Silicon carbide substrate]
Next, the configuration of the silicon carbide substrate 10 included in the MOSFET 1 according to this embodiment will be described.

  FIG. 2 is an enlarged view of a part of region II in FIG. 3 and 4 partially show a planar structure of silicon carbide substrate 10 according to the present embodiment. The diagram on the left side of FIG. 2 shows a cross-sectional structure along the line segment II-II shown in FIG. The diagram on the right side of FIG. 2 shows a cross-sectional structure taken along line II-II shown in FIG. 2 to 4, the gate insulating film 15 and the drain electrode 3 are omitted.

  As shown in FIG. 2, silicon carbide substrate 10 according to the present embodiment has a silicon carbide single crystal substrate 11 and a silicon carbide layer 17. Silicon carbide single crystal substrate 11 is made of, for example, a silicon carbide single crystal. The silicon carbide single crystal has a hexagonal crystal structure, for example, and the polytype is 4H type. Silicon carbide single crystal substrate 11 has an n-type conductivity by including an n-type impurity such as nitrogen (N). Silicon carbide layer 17 is provided on silicon carbide single crystal substrate 11 and constitutes first main surface 10A.

  Silicon carbide single crystal substrate 11 has third main surface 11A and second main surface 11B opposite to third main surface 11A. Silicon carbide single crystal substrate 11 is in contact with silicon carbide layer 17 at third main surface 11A. The diameter of main surface 11A of silicon carbide single crystal substrate 11 is, for example, 100 mm or more (4 inches or more), preferably 150 mm or more (6 inches or more). As shown in FIG. 2, third main surface 11 </ b> A is a main surface on which silicon carbide layer 17 is formed. For example, third main surface 11A has an off angle of ± 4 ° or less with respect to the (0001) plane (hereinafter also referred to as “silicon (Si) plane”). The off direction of the off angle may be, for example, within a range of ± 5 ° or less with respect to the <11-20> direction, or within a range of ± 5 ° or less with respect to the <01-10> direction. Also good.

Drift region 12 is a silicon carbide layer formed on third main surface 11A of silicon carbide single crystal substrate 11 by, for example, a CVD (Chemical Vapor Deposition) method. More specifically, the drift region 12 is formed by a CVD method using silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and nitrogen (N ₂ ) or ammonia (NH ₃ ) as a dopant gas. Is an epitaxially grown film. The drift region 12 incorporates nitrogen (N) atoms generated by thermal decomposition of the nitrogen or ammonia, and the conductivity type of the drift region 12 is n-type. Preferably, the concentration of n-type impurities contained in drift region 12 is lower than the concentration of n-type impurities contained in silicon carbide single crystal substrate 11. As described above, since the third major surface 11A is off with respect to the (0001) plane, the drift region 12 is formed by step flow growth. Therefore, the drift region 12 is made of silicon carbide having a polytype of 4H as in the case of the silicon carbide single crystal substrate 11, and mixing of different polytypes is suppressed. The thickness of drift region 12 is, for example, about 5 μm or more and 150 μm or less.

  As shown in FIG. 3, a groove 20 is formed in the first main surface 10A. The groove 20 extends in one direction along the first main surface 10A in a plan view of the first main surface 10A (a visual field viewed along a direction perpendicular to the first main surface 10A). More specifically, the groove 20 extends along the step flow growth direction D along the off direction of the off angle with respect to the (0001) plane. That is, the groove 20 extends along a direction that is within a range of ± 5 ° or less with respect to the <11-20> direction or a direction that is within a range of ± 5 ° or less with respect to the <01-10> direction. ing.

  The width W2 in the one direction of the groove 20 is not less than twice the width W3 in the direction perpendicular to the one direction, and preferably not less than five times. The width W2 is not less than 15 μm and not more than 50 μm, preferably not less than 25 μm and not more than 35 μm. The width W3 is not less than 1 μm and not more than 5 μm, preferably not less than 2 μm and not more than 3 μm.

  As shown in FIG. 2, groove 20 is formed so as to extend from threading dislocation 40 existing in silicon carbide layer 17 along step flow growth direction D along the off direction of the off angle. More specifically, the groove portion 20 is connected to the first groove portion 21 formed on the threading dislocation 40 and the first groove portion 21, and is along the step flow growth direction D from the first groove portion 21. And a second groove portion 22 formed so as to extend.

  The first groove 21 is formed at one end (left end in FIG. 2) of the groove 20 in the step flow growth direction D. The first groove portion 21 has a maximum depth D2 from the first main surface 10A of 10 nm or less. The maximum depth D2 is the maximum depth in the entire groove 20 as shown in FIG. The width W1 of the first groove portion 21 is preferably 1 μm or less, and more preferably 0.5 μm or less.

  As shown in FIG. 2, the second groove portion 22 starts from the connection portion with the first groove portion 21 and reaches the other end portion (the right end portion in FIG. 2) opposite to the one end portion. It is formed to reach. In other words, the second groove portion 22 is formed so as to extend from the first groove portion 21 along the one direction D to reach the other end portion opposite to the one end portion. The second groove 22 is formed such that the depth D1 from the first main surface 10A is smaller than the maximum depth D2 of the first groove 21. More specifically, the second groove 22 extends along the step flow growth direction D while maintaining a depth shallower than the maximum depth D2 of the first groove 21. The depth D1 is preferably 3 nm or less, more preferably 2 nm or less, and even more preferably 1 nm or less. The width W4 of the second groove 22 is, for example, 20 μm or more, and preferably 25 μm or more.

The surface density of the groove 20 in the first main surface 10A is, for example, 10 / mm ² or more. The surface density may be 100 / mm ² or more. The upper limit of the surface density may be 1000 / mm ² . The surface density of the surface 2a (see FIG. 1) of the second impurity region 2 in contact with the gate insulating film 15 may be 10 / mm ² or more.

  As shown in FIG. 1, the gate insulating film 15 is provided in contact with the second impurity region 2 and the source region 14. The gate insulating film 15 may be provided on the groove 20 provided on the surface 10 </ b> A of the second impurity region 2. The gate insulating film 15 may be provided on the first trench portion 21. The gate insulating film 15 may be provided on the second groove portion 22 provided on the surface 10 </ b> A of the second impurity region 2, or may be provided on the pit portion 30. As shown in FIGS. 2 and 4, the pit portion 30 may be provided on the surface 10 </ b> A of the second impurity region 2. As shown in FIG. 2, pit portion 30 is derived from threading dislocation 40 extending from silicon carbide single crystal substrate 11 into silicon carbide layer 17. The maximum depth D3 of the pit portion 30 is larger than 10 nm, more specifically larger than 20 nm. As shown in FIG. 4, the pit portion 30 may have a triangular shape in plan view. The gate insulating film 15 may be provided so as to fill the first groove 21 and the second groove 22 included in the groove 20.

[Method of Manufacturing Silicon Carbide Semiconductor Device]
Next, a method for manufacturing MOSFET 1 according to this embodiment will be described.

  First, a silicon carbide substrate preparation step (S30: FIG. 5) is performed. For example, a step of preparing a silicon carbide single crystal substrate (S31: FIG. 6) is performed. For example, a silicon carbide single crystal substrate 11 is prepared by slicing a polytype 4H type silicon carbide ingot (not shown) crystal-grown using a sublimation recrystallization method to a predetermined thickness (see FIG. 9). Silicon carbide single crystal substrate 11 has third main surface 11A and second main surface 11B opposite to third main surface 11A. Third main surface 11A is a main surface on which silicon carbide layer 17 is formed. For example, third main surface 11A has an off angle of ± 4 ° or less with respect to the (0001) plane. The off direction of the off angle may be, for example, within a range of ± 5 ° or less with respect to the <11-20> direction or within a range of ± 5 ° or less with respect to the <01-10> direction. Also good.

  Next, the configuration of the epitaxial growth apparatus 41 will be described with reference to FIGS. FIG. 7 is a side view of the epitaxial growth apparatus 41. FIG. 8 is a cross-sectional view of epitaxial growth apparatus 41 taken along line VIII-VIII in FIG.

  As shown in FIGS. 7 and 8, the epitaxial growth apparatus 41 includes a heating element 46, a heat insulating material 45, a quartz tube 44, and an induction heating coil 43. The heating element 46 is made of, for example, a carbon material. As shown in FIG. 8, the heating element 46 has a semi-cylindrical hollow structure including a curved surface portion 46A and a flat portion 46B. Two heating elements 46 are provided and arranged so that the flat portions 46B face each other. A space surrounded by flat portion 46B is channel 1A, which is a space for processing silicon carbide single crystal substrate 11.

  The heat insulating material 45 is a member for insulating the channel 1 </ b> A from the outside of the epitaxial growth apparatus 41. The heat insulating material 45 is disposed so as to surround the outer periphery of the heating element 46. The quartz tube 44 is disposed so as to surround the outer peripheral portion of the heat insulating material 45. The induction heating coil 43 is wound around the outer periphery of the quartz tube 44.

  Next, a crystal growth process using the epitaxial growth apparatus 41 will be described. First, silicon carbide single crystal substrate 11 prepared in the step of preparing a silicon carbide single crystal substrate (S31: FIG. 6) is arranged in channel 1A of epitaxial growth apparatus 41. More specifically, silicon carbide single crystal substrate 11 is placed on a susceptor (not shown) provided on one heating element 46.

Next, a step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6) is performed. For example, the first n-type silicon carbide layer 12a is formed on third main surface 11A of silicon carbide single crystal substrate 11 using a source gas having a C / Si ratio of less than 1 (see FIG. 9). First, after replacing the gas in the channel 1A, the channel 1A is adjusted to a predetermined pressure, for example, 60 mbar to 100 mbar (6 kPa to 10 kPa) while flowing the carrier gas. The carrier gas may be, for example, hydrogen (H ₂ ) gas, argon (Ar) gas, helium (He) gas, or the like. The carrier gas flow rate may be, for example, about 50 slm to 200 slm. Here, the unit of flow rate “slm (Standard Liter Per Minute)” indicates “L / min” in the standard state (0 ° C., 101.3 kPa).

  Next, the heating element 46 is induction heated by supplying a predetermined alternating current to the induction heating coil 43. Thereby, the susceptor on which channel 1A and silicon carbide single crystal substrate 11 are placed is heated to a predetermined reaction temperature. At this time, the susceptor is heated to, for example, about 1500 ° C. to 1750 ° C.

Next, the source gas is supplied to the channel 1A. The source gas includes Si source gas and C source gas. Examples of the Si source gas include silane (SiH ₄ ) gas, disilane (Si ₂ H ₆ ) gas, dichlorosilane (SiH ₂ Cl ₂ ) gas, trichlorosilane (SiHCl ₃ ) gas, and silicon tetrachloride (SiCl ₄ ) gas. Is mentioned. That is, the Si source gas may be at least one selected from the group consisting of silane gas, disilane gas, dichlorosilane gas, trichlorosilane gas, and silicon tetrachloride gas.

Examples of the C source gas include methane (CH ₄ ) gas, ethane (C ₂ H ₆ ) gas, propane (C ₃ H ₈ ) gas, acetylene (C ₂ H ₂ ) gas, and the like. That is, the C source gas may be at least one selected from the group consisting of methane gas, ethane gas, propane gas, and acetylene gas.

  The source gas may contain a dopant gas. Examples of the dopant gas include nitrogen gas and ammonia gas.

  The source gas in the step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6) may be, for example, a mixed gas of silane gas and propane gas. In the step of forming the first epitaxial layer, the C / Si ratio of the source gas is adjusted to less than 1. As long as the C / Si ratio is less than 1, it may be, for example, 0.5 or more, 0.6 or more, or 0.7 or more. The C / Si ratio may be, for example, 0.95 or less, 0.9 or less, or 0.8 or less. The silane gas flow rate and the propane gas flow rate may be appropriately adjusted in a range of, for example, about 10 to 100 sccm so as to obtain a desired C / Si ratio. Here, the unit of flow rate “sccm (Standard Cubic Centimeter per Minute)” indicates “mL / min” in the standard state (0 ° C., 101.3 kPa).

  The film formation rate in the step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6) may be, for example, about 5 μm / h or more and 50 μm / h or less. The thickness of the first n-type silicon carbide layer 12a is, for example, not less than 1 μm and not more than 150 μm. The thickness of the first n-type silicon carbide layer 12a may be 5 μm or more, 10 μm or more, or 15 μm or more. The thickness of the first n-type silicon carbide layer 12a may be 100 μm or less, 75 μm or less, or 50 μm or less.

  Next, a step of epitaxially forming the first p-type silicon carbide layer (S33: FIG. 6) is performed. First p-type silicon carbide layer 13a is formed by epitaxial growth on first n-type silicon carbide layer 12a (see FIG. 10). During the epitaxial growth, the first p-type silicon carbide layer 13a is doped with a p-type impurity such as aluminum or boron. Next, mask layer 31 having an opening is formed on first p-type silicon carbide layer 13a. Using mask layer 31, a portion of first p-type silicon carbide layer 13a is etched, so that a portion of first n-type silicon carbide layer 12a is removed from first p-type silicon carbide layer 13a. Exposed (see FIG. 11). The first p-type silicon carbide layer 13a remaining without being etched is the first body region portion 13a.

  Next, a step of epitaxially forming the second n-type silicon carbide layer (S34: FIG. 6) is performed. Specifically, second n-type silicon carbide layer 12b is formed on first p-type silicon carbide layer 13a and first n-type silicon carbide layer 12a. Second n-type silicon carbide layer 12b is formed to fill the opening formed in first p-type silicon carbide layer 13a. The thickness of second n-type silicon carbide layer 12b is preferably equal to or greater than the thickness of first p-type silicon carbide layer 13a. Second n-type silicon carbide layer 12b is formed by epitaxial growth using a method similar to the method of forming first n-type silicon carbide layer 12a.

  Next, a step of performing chemical mechanical polishing on the second n-type silicon carbide layer (S35: FIG. 6) is performed. Specifically, the surface of second n-type silicon carbide layer 12b is planarized by CMP (Chemical Mechanical Polishing) (see FIG. 13). For example, until the thickness of the portion of second n-type silicon carbide layer 12b on first p-type silicon carbide layer 13a is approximately the same as the thickness of first p-type silicon carbide layer 13a, the second n CMP is performed on type silicon carbide layer 12b.

  Next, a step of ion-implanting the first p-type impurity (S36: FIG. 6) is performed. Mask layer 32 having an opening in a region where p-type impurities are ion-implanted is formed on second n-type silicon carbide layer 12b. Using mask layer 32, a p-type impurity such as aluminum or boron is ion-implanted into the surface of second n-type silicon carbide layer 12b (see FIG. 14). Thereby, the second body region portion 13b in contact with the first body region portion 13a is formed. Next, the mask layer 32 is removed.

  Next, a step of reconfiguring the surface of the second n-type silicon carbide layer (S37: FIG. 6) is performed. In the step of reconfiguring the surface, the susceptor in the step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6) and the step of epitaxially forming the second n-type silicon carbide layer (S34: FIG. 6) You may raise the temperature of a susceptor about 10-30 degreeC rather than temperature.

  In the step of restructuring the surface, a mixed gas containing a source gas having a C / Si ratio of less than 1 and hydrogen gas is used. The C / Si ratio of the source gas is such that C in the step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6) and the step of epitaxially forming the second n-type silicon carbide layer (S34: FIG. 6). / Si ratio may be lower. As long as the C / Si ratio is less than 1, it may be 0.5 or more, 0.6 or more, or 0.7 or more. The C / Si ratio may be, for example, 0.95 or less, 0.9 or less, or 0.8 or less. Here, the “C / Si ratio” indicates the ratio of the number of carbon (C) atoms to the number of silicon (Si) atoms in the raw material gas. “Restructuring the surface” means changing the surface properties of the first epitaxial layer by etching with hydrogen gas and epitaxial growth with a source gas. Through the reconfiguration step, the thickness of the first epitaxial layer may decrease, increase, or not substantially change.

  In the step of reconfiguring the surface, the step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6), the step of epitaxially forming the second n-type silicon carbide layer (S34: FIG. 6), and A source gas different from the source gas in the step of epitaxially forming the third n-type silicon carbide layer (S38: FIG. 6) may be used. Such an aspect is expected to increase the effect of suppressing the formation of the pit portion. For example, in the step of epitaxially forming the second n-type silicon carbide layer (S34: FIG. 6) and the step of epitaxially forming the third n-type silicon carbide layer described later (S38: FIG. 6), silane gas and propane gas are used. In the step of reconstituting the surface, an embodiment such as using dichlorosilane and acetylene is conceivable.

  In the step of reconfiguring the surface, a step of epitaxially forming a second n-type silicon carbide layer (S34: FIG. 6) and a step of epitaxially forming a third n-type silicon carbide layer described later (S38: FIG. 6) In comparison, the ratio of the raw material gas flow rate to the hydrogen gas flow rate may be reduced. This is expected to increase the effect of shallowing the pit portion.

  The hydrogen gas flow rate in the mixed gas may be about 100 slm or more and 150 slm or less, for example. The hydrogen gas flow rate may be about 120 slm, for example. The Si source gas flow rate in the mixed gas may be, for example, 1 sccm or more and 5 sccm or less. The lower limit of the Si source gas flow rate may be 2 sccm. The upper limit of the Si source gas flow rate may be 4 sccm. The C source gas flow rate in the mixed gas may be, for example, 0.3 sccm or more and 1.6 sccm or less. The lower limit of the C source gas flow rate may be 0.5 sccm or 0.7 sccm. The upper limit of the C source gas flow rate may be 1.4 sccm or 1.2 sccm.

  In the process of reconfiguring the surface, various conditions are set so that the ratio of the raw material gas flow rate to the hydrogen gas flow rate is reduced compared with normal epitaxial growth, and the etching with hydrogen gas and the epitaxial growth with the raw material gas are in an antagonistic state. It is desirable to adjust. For example, it is conceivable to adjust the hydrogen gas flow rate and the raw material gas flow rate so that the film formation rate is about 0 ± 0.5 μm / h. The film formation rate may be adjusted to about 0 ± 0.4 μm / h, may be adjusted to about 0 ± 0.3 μm / h, or may be adjusted to about 0 ± 0.2 μm / h. It may be adjusted to about 0 ± 0.1 μm / h. This is expected to increase the effect of shallowing the pit portion.

  The processing time in the process of reconstructing the surface is, for example, about 30 minutes to 10 hours. The treatment time may be 8 hours or less, 6 hours or less, 4 hours or less, or 2 hours or less.

  The threading dislocations described above include threading screw dislocations, threading edge dislocations, and mixed dislocations in which these dislocations are mixed. When each dislocation is expressed by Burgers vector b, threading screw dislocation (b = <0001>), threading edge dislocation (b = 1/3 <11-20>), mixed dislocation (b = <0001> +1/3 < 11-20>). It is considered that the pit portion that affects the variation in the film thickness of the gate insulating film is formed due to threading screw dislocation, threading edge dislocation, and mixed dislocation. The pits formed due to threading screw dislocations and mixed dislocations with relatively large distortion around the dislocations are deep.

  By reconstructing the surface of the second n-type silicon carbide layer 12b, an effect of shallowing the pit portion formed due to threading screw dislocation and mixed dislocation can be expected. Then, the C / Si ratio of the source gas is changed from a value less than 1 to a value greater than 1, and a third n-type silicon carbide layer 2 is grown as will be described later. Thereby, it is considered that the effect of shallowing the pit portion due to threading screw dislocation and mixed dislocation increases.

  Next, a step of epitaxially forming the third n-type silicon carbide layer (S38: FIG. 6) is performed. After reconfiguring the surface of second n-type silicon carbide layer 12b, third n-type silicon carbide layer 2 is formed on the surface. Third n-type silicon carbide layer 2 (see FIG. 2) is formed using a source gas having a C / Si ratio greater than 1. As long as the C / Si ratio is larger than 1, it may be, for example, 1.05 or more, 1.1 or more, 1.2 or more, 1.3 or more, or 1.4 or more. . Further, the C / Si ratio may be 2.0 or less, 1.8 or less, or 1.6 or less. Thereby, third n-type silicon carbide layer 2 is formed on second n-type silicon carbide layer 12b and second body region portion 13b (see FIG. 15).

  The source gas in the step of epitaxially forming the third n-type silicon carbide layer (S38: FIG. 6) is the same as the step of epitaxially forming the first n-type silicon carbide layer (S32: FIG. 6) and the second n-type carbonization. The raw material gas used in the step of epitaxially forming the silicon layer (S34: FIG. 6) may be the same or different. The source gas may be, for example, silane gas and propane gas. The silane gas flow rate and the propane gas flow rate may be appropriately adjusted in a range of, for example, about 10 to 100 sccm so as to obtain a desired C / Si ratio. The carrier gas flow rate may be, for example, about 50 slm to 200 slm.

  The film formation rate in the step of epitaxially forming the third n-type silicon carbide layer (S38: FIG. 6) may be, for example, about 5 μm / h or more and 50 μm / h or less. The thickness of the third n-type silicon carbide layer 2 is, for example, not less than 0.1 μm and not more than 3 μm, preferably not less than 0.1 μm and not more than 1 μm.

  The thickness of third n-type silicon carbide layer 2 may be smaller than the total thickness of first n-type silicon carbide layer 12a and second n-type silicon carbide layer 12b. For example, the ratio of the thickness of third n-type silicon carbide layer 2 to the total thickness of first n-type silicon carbide layer 12a and second n-type silicon carbide layer 12b is 0.01 or more and 0.9 It may be about the following. Here, the ratio of the same thickness means that the thickness of the third n-type silicon carbide layer 2 is changed to the first n-type silicon carbide layer 12a and the second n-type silicon carbide layer 12b that have undergone the process of restructuring the surface. The value divided by the total thickness is shown. The ratio of the same thickness may be 0.8 or less, 0.7 or less, 0.6 or less, 0.5 or less, 0.4 or less, 0.3 Or less, 0.2 or less, or 0.1 or less. This is expected to increase the effect of shallowing the pit portion.

  As described above, silicon carbide layer 17 including first n-type silicon carbide layer 12a, second n-type silicon carbide layer 12b, and third n-type silicon carbide layer 2 is formed as shown in FIG. In the silicon carbide layer 17, the first n-type silicon carbide layer 12a, the second n-type silicon carbide layer 12b, and the third n-type silicon carbide layer 2 may be integrated and cannot be distinguished.

  As shown in FIG. 3, groove portion 20 is formed in first main surface 10 </ b> A of silicon carbide layer 17. The groove 20 extends in one direction along the first main surface 10A in the plan view of the first main surface 10A. More specifically, the groove 20 extends along the step flow growth direction D along the off direction of the off angle with respect to the (0001) plane. That is, the groove 20 extends along a direction that is within a range of ± 5 ° or less with respect to the <11-20> direction or a direction that is within a range of ± 5 ° or less with respect to the <01-10> direction. ing.

  The width W2 in the one direction of the groove 20 is not less than twice the width W3 in the direction perpendicular to the one direction, and preferably not less than five times. The width W2 is not less than 15 μm and not more than 50 μm, preferably not less than 25 μm and not more than 35 μm. The width W3 is not less than 1 μm and not more than 5 μm, preferably not less than 2 μm and not more than 3 μm.

  As shown in FIG. 2, groove 20 is formed to extend along threading dislocation 40 existing in silicon carbide layer 17 along step flow growth direction D. More specifically, the groove portion 20 is connected to the first groove portion 21 formed on the threading dislocation 40 and the first groove portion 21, and is along the step flow growth direction D from the first groove portion 21. And a second groove portion 22 formed so as to extend.

  The first groove 21 is formed at one end (left end in FIG. 2) of the groove 20 in the step flow growth direction D. The first groove portion 21 has a maximum depth D2 from the first main surface 10A of 10 nm or less. This maximum depth D2 is the maximum depth in the entire groove 20 as shown in FIG. Further, the width W1 of the first groove portion 21 is preferably 1 μm or less, and more preferably 0.5 μm or less.

  As shown in FIG. 2, the second groove portion 22 starts from the connection portion with the first groove portion 21 and reaches the other end portion (the right end portion in FIG. 2) opposite to the one end portion. It is formed to reach. The second groove 22 is formed such that the depth D1 from the first main surface 10A is smaller than the maximum depth D2 of the first groove 21. More specifically, the second groove 22 extends along the step flow growth direction D while maintaining a constant depth shallower than the maximum depth D2 of the first groove 21. The depth D1 is preferably 3 nm or less, more preferably 2 nm or less, and even more preferably 1 nm or less. The width W4 of the second groove 22 is, for example, 20 μm or more, and preferably 25 μm or more.

  Next, a step of ion-implanting n-type impurities (S39: FIG. 6) is performed. For example, a mask layer 33 having an opening is formed on the region where the source region 14 is formed. An n-type impurity such as phosphorus is ion-implanted into the surface of third n-type silicon carbide layer 2 using mask layer 33. Thereby, the source region 14 having n-type conductivity is formed (see FIG. 16). The concentration of n-type impurity in source region 14 is higher than the concentration of n-type impurity in third n-type silicon carbide layer 2. Since the source region 14 is formed by ion implantation, the lattice defect density of the source region 14 is higher than the lattice defect density of the second impurity region 2.

  Next, a step of ion-implanting the second p-type impurity (S40: FIG. 6) is performed. For example, a mask layer (not shown) having an opening is formed on a region where the contact region 18 is to be formed. A p-type impurity such as aluminum is ion-implanted into the surface of the source region 14 using the mask layer. Thereby, a contact region 18 having a p-type conductivity is formed. The concentration of the p-type impurity in the contact region 18 may be higher than the concentration of the p-type impurity in the body region 13. Next, the mask layer is removed. Thus, silicon carbide substrate 10 having drift region 12, body region 13, source region 14, contact region 18, silicon carbide layer 17 including second impurity region 2, and silicon carbide single crystal substrate 11. Is prepared (see FIG. 17).

  Next, an activation annealing step (S50: FIG. 5) is performed. For example, silicon carbide layer 17 is heated to, for example, about 1800 ° C. in an argon atmosphere, so that n-type impurities and p-type impurities implanted into silicon carbide layer 17 are activated. Thereby, desired carriers are generated in body region 13, source region 14 and contact region 18 in silicon carbide layer 17.

Next, a gate insulating film formation step (S60: FIG. 5) is performed. For example, by thermally oxidizing silicon carbide substrate 10 in an atmosphere containing oxygen (O ₂ ), gate insulating film 15 made of a material containing silicon dioxide (SiO ₂ ) is formed on first main surface 10A ( (See FIG. 18). The gate insulating film 15 is formed in contact with the second impurity region 2, the source region 14, and the contact region 18. The first main surface 10A extends in one direction along the first main surface 10A, the width W2 in one direction is more than twice the width W3 in the direction perpendicular to the one direction, and the first main surface A groove 20 (see FIG. 2) having a maximum depth D2 from 10A of 10 nm or less is formed. That is, since the formation of the pit portion 30 is suppressed on the first main surface 10A (FIG. 2), the variation in the thickness of the gate insulating film 15 formed on the first main surface 10A is reduced.

Next, a nitrogen annealing step (S65: FIG. 5) is performed. For example, silicon carbide substrate 10 and gate insulating film 15 are heated at a temperature of 1100 ° C. or higher in an atmosphere containing nitrogen atoms. The atmosphere containing nitrogen is, for example, nitrogen monoxide (NO), dinitrogen monoxide (N ₂ O), nitrogen dioxide (NO ₂ ), ammonia, and the like. Preferably, silicon carbide substrate 10 on which gate insulating film 15 is formed is held in a gas containing nitrogen at a temperature of 1100 ° C. or higher and 1400 ° C. or lower for about 1 hour.

  Next, a gate electrode formation step (S70: FIG. 5) is performed. For example, the gate electrode 27 made of a conductive material containing doped polysilicon is formed on the gate insulating film 15 by LP (Low Pressure) CVD. The gate electrode 27 is formed on the gate insulating film 15 at a position facing the second impurity region 2 and the source region 14.

  Next, an interlayer insulating film forming step (S80: FIG. 5) is performed. For example, the interlayer insulating film 4 is formed on the gate insulating film 15 by the CVD method so as to cover the gate electrode 27. Interlayer insulating film 4 is made of, for example, a material containing silicon dioxide.

  Next, an ohmic electrode formation step (S90: FIG. 5) is performed. For example, the gate insulating film 15 and the interlayer insulating film 4 in the region where the source electrode 16 is formed are removed by etching. Thereby, a region where the source region 14 and the contact region 18 are exposed is formed (see FIG. 19). Next, a metal film containing, for example, Ti, Al, and Si is formed in the region so as to be in contact with both the source region 14 and the contact region 18. Next, at least a part of the metal film is silicided by heating the metal film. Thereby, the source electrode 16 in contact with both the source region 14 and the contact region 18 is formed on the first major surface 10A.

  Next, a pad electrode forming step (S100: FIG. 5) is performed. For example, a source pad electrode 19 made of a conductor containing aluminum is formed by vapor deposition so as to cover the source electrode 16 and the interlayer insulating film 4. Next, drain electrode 3 in contact with second main surface 11B of silicon carbide single crystal substrate 11 is formed. Next, silicon carbide substrate 10 is divided into a plurality of chips by, for example, a dicing blade. Thus, MOSFET 1 shown in FIG. 1 is completed.

  In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. In the present embodiment, the case where the silicon carbide semiconductor device is a planar MOSFET has been described. However, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor).

Next, the function and effect of the MOSFET according to the present embodiment will be described.
According to MOSFET 1 according to the present embodiment, main surface 10A extends in one direction D along main surface 10A, and width W2 in one direction D is twice the width W3 in the direction perpendicular to one direction D. The groove portion 20 is formed as described above, and the maximum depth D2 from the main surface 10A is 10 nm or less. That is, according to the MOSFET 1 according to the present embodiment, a larger number of the groove portions 20 are formed as compared with the pit portions 30 having a depth of several tens of nanometers by controlling the epitaxial growth conditions and the like of the silicon carbide layer 17. It has been done. Therefore, the MOSFET 1 according to this embodiment can reduce the variation in the film thickness of the gate insulating film 15 as compared with the conventional MOSFET in which a large number of the pit portions 30 are formed. As a result, the long-term reliability of the MOSFET 1 is improved. A second impurity region 2 that functions as a channel is formed by an epitaxial growth method. For this reason, the channel mobility is higher than when the second impurity region 2 is formed by ion implantation.

Further, according to MOSFET 1 according to the present embodiment, the surface density of groove 20 in main surface 10A is 10 / mm ² or more.

  Furthermore, according to MOSFET 1 according to the present embodiment, the conductivity type of second impurity region 2 is either n-type or p-type. When the conductivity type is n-type, the second impurity region 2 contains nitrogen atoms. When the conductivity type is p-type, second impurity region 2 contains aluminum atoms.

  Furthermore, according to MOSFET 1 according to the present embodiment, the thickness of second impurity region 2 in the direction perpendicular to main surface 10A is not less than 0.1 μm and not more than 3 μm.

Furthermore, according to MOSFET 1 according to the present embodiment, the impurity concentration of second impurity region 2 is 1 × 10 ¹⁶ cm ⁻³ or more.

Furthermore, according to MOSFET 1 according to the present embodiment, the impurity concentration of drift region 12 is less than 1 × 10 ¹⁶ cm ⁻³ .

  Furthermore, according to MOSFET 1 according to the present embodiment, groove portion 20 includes a first groove portion 21 and a second groove portion 22 connected to first groove portion 21. The first groove 21 is formed at one end of the groove 20 in one direction D, and the maximum depth D2 from the main surface 10A is 10 nm or less. The second groove portion 22 is formed so as to extend from the first groove portion 21 along the one direction D to reach the other end portion opposite to the one end portion, and has a depth D1 from the main surface 10A. Is smaller than the maximum depth of the first groove.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the embodiments described above but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.

1 Silicon carbide semiconductor device (MOSFET)
1A channel 2 second impurity region (third n-type silicon carbide layer)
2a Surface 3 Drain electrode 4 Interlayer insulating film 10 Silicon carbide substrate 10A First main surface (main surface, surface)
11 Silicon carbide single crystal substrate 11A Third main surface (main surface)
11B Second principal surface 12 Drift region 12a First drift region (first n-type silicon carbide layer)
12b Second drift region (second n-type silicon carbide layer)
13 body region 13a first body region (first p-type silicon carbide layer)
13b Second body region portion 14 First impurity region (source region)
15 Gate insulating film 16 Source electrode 17 Silicon carbide layer 18 Contact region 19 Source pad electrode 20 Groove part 21 First groove part 22 Second groove part 27 Gate electrode 30 Pit parts 31, 32, 33 Mask layer 40 Threading dislocation 41 Epitaxial growth apparatus 43 Induction heating coil 44 Quartz tube 45 Insulating material 46 Heating element 46A Curved part 46B Flat part D One direction (step flow growth direction)
D1, D2, D3 depth T thickness W1, W2, W3, W4 width

Claims (6)

A silicon carbide substrate having a main surface;
A gate insulating film provided on the main surface,
The silicon carbide substrate faces a first impurity region, a drift region having the same conductivity type as the first impurity region and physically separated from the first impurity region, the gate insulating film, and A second impurity region configured to be electrically conductive between the first impurity region and the drift region;
The second impurity region has a lower lattice defect density than the first impurity region;
The main surface extends in one direction along the main surface, the width in the one direction is at least twice the width in the direction perpendicular to the one direction, and the maximum depth from the main surface Is formed with a groove portion of 10 nm or less ,
The groove part includes a first groove part and a second groove part connected to the first groove part,
The first groove is formed at one end of the groove in the one direction,
The second groove extends from the first groove along the one direction to the other end opposite to the one end, and the depth from the main surface is the first A silicon carbide semiconductor device that is smaller than the maximum depth of the groove . The silicon carbide semiconductor device according to claim 1, wherein a surface density of the groove portion on the main surface is 10 / mm ² or more. The conductivity type of the second impurity region is either n-type or p-type,
When the conductivity type is n-type, the second impurity region includes a nitrogen atom,
The silicon carbide semiconductor device according to claim 1, wherein when the conductivity type is p-type, the second impurity region contains an aluminum atom.   4. The silicon carbide semiconductor device according to claim 1, wherein a thickness of said second impurity region in a direction perpendicular to said main surface is not less than 0.1 μm and not more than 3 μm. 5. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of the second impurity region is 1 × 10 ¹⁶ cm ⁻³ or more. 6. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of drift region is less than 1 × 10 ¹⁶ cm ⁻³ .

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