JP3763258B2 - Probe card and chip area sorting method using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a probe card for measuring electrical characteristics by mechanically contacting a probe to a pad of an LSI chip in a wafer state and a chip area sorting method using the same.
[0002]
[Prior art]
The probe card is used for a test in a wafer state before an assembly process of LSI manufacturing. The probe card has a probe to be brought into contact with each bonding pad in the LSI chip area to be measured. A test signal or a test pattern is input from this probe to the LSI chip.
[0003]
The probe card is connected to a tester and becomes a part of building a test system. The tester compares the output value from the LSI with an expected value via the probe card to determine the quality of the LSI, and measures analog values such as input / output signals, power supply voltage, and current. An LSI selected as a non-defective product through such a wafer probing test is sent to an assembly process.
[0004]
In recent years, the diameter of wafers has increased, and the number of chips acquired per wafer tends to increase. Accordingly, the time spent for the wafer probing test as described above is increased, and higher efficiency is desired.
[0005]
Therefore, a plurality of probe cards have been used so that a plurality of chips can be simultaneously tested as much as possible. In particular, a plurality of probe cards are used for a center pad type LSI chip or a type of LSI chip having a relatively small number of pads.
[0006]
[Problems to be solved by the invention]
The diversification of LSI chips is remarkable, and the number of data input / output is increasing. As a result, the number of pads per chip increases, and many pads are arranged at a narrow pitch around the chip. In this case, it becomes difficult to apply each probe of the probe card to each pad (or bump).
[0007]
A technique of making the extension source multilayer for each probe of the probe card is a generally known technique. Thereby, for example, even when the arrangement pitch of the contact areas (pads, bumps, etc.) is smaller than the probe wire diameter (base material diameter), the probes can contact each other.
[0008]
However, when the contact area (pads, bumps, etc.) is further narrowed in pitch, it is difficult to eliminate the concern about reliability only with the above technique. The configuration in which the probe is applied to all the contact areas to be measured tends to be in an unacceptable state of pressure difference and positional deviation of each probe in the measurement, and further increases the risk of short circuit between adjacent points.
[0009]
The present invention has been made in view of the above circumstances, and maintains high reliability while reducing the density of probe arrangements when the contact area (pad, bump, etc.) to be measured has a narrow pitch. It is an object of the present invention to provide a probe card that is easy to perform and a chip area sorting method using the same.
[0010]
[Means for Solving the Problems]
The probe card according to the present invention is a circuit substrate for transferring signals by arranging an array of a plurality of input terminals and an array of a plurality of output terminals having a narrower pitch than the input terminals on a wafer so as to face adjacent chip regions. In the circuit base material, each of the opposing connection regions provided corresponding to each of the chip regions, and each of the opposing connection regions, the output except for all the input terminals in the chip region and adjacent to each other. A plurality of electrical connection members extending to positions corresponding to the terminals and bringing the circuit base material and the wafer into contact with each other to contact each terminal in the chip region, and the electrical connection in one of the opposing connection regions The electrical connection member and the electrical connection member in another one of the opposed connection regions are arranged so as to complement each other of the output terminals to be contacted with each other. Characterized in that a relationship.
[0011]
According to the probe card according to the present invention, a plurality of chip regions in which an array of a plurality of input terminals and an array of a plurality of output terminals having a narrower pitch than the input terminals are adjacent to each other are to be measured. The measurement is divided into a plurality of times for the narrow pitch output terminals arranged in one chip area. If connections are shared, connections to adjacent terminals at a narrow pitch can be thinned out at that time. Thereby, even when the output terminals are arranged in a remarkably narrow pitch, a more stable connection of the electrical connection member is possible.
[0012]
In the chip area sorting method using the probe card according to the present invention, an array of a plurality of input terminals and a plurality of output terminals having a narrower pitch than the input terminals are opposed to a plurality of adjacent chip areas on the wafer. The probe card has an opposing connection region in which an electrical connection member is arranged on the periphery corresponding to each of the chip regions, and the electrical connection member is For each of the opposing connection regions, the electrical connection member and the opposing connection in one of the opposing connection regions extend to a position corresponding to the output terminal except for all the input terminals in the chip region and adjacent to each other. The electrical connection member in another one of the regions is an arrangement relationship that complements adjacent portions of the output terminals to be contacted with each other. Then, the movement control is performed so that the different opposing connection regions are brought close to and connected to the respective chip regions until the contact of the electrical connection member is satisfied with respect to all the terminals in the chip region. And
[0013]
According to the chip area sorting method using the probe card according to the present invention, the probe card has an opposing connection area in which electrical connection members are arranged on the periphery corresponding to each chip area. In addition, the electrical connection member extends to a position corresponding to the output terminals except for all the input terminals in the chip region and the portions adjacent to each other, and faces the electrical connection member in one of the opposing connection regions. The electrical connection member in another one of the connection regions has an arrangement relationship in which the adjacent output terminals to be contacted with each other are complemented. As a result, the electrical connection members provided in each opposing connection region share the role. By facing and approaching (connecting) each opposing connection region to the chip region, all the terminal portions in one chip region and the electrical connection member So that the contact is satisfied. This increases the accuracy with which the electrical connection member hits each of the narrow pitch output terminals in the chip region.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
1 (a) and 1 (b) show the main configuration of the probe card according to the first embodiment of the present invention, respectively (a) is an overview from the top, and (b) is an arbitrary view from the side. It is the schematic which shows the cross section.
[0015]
The circuit substrate 10 constituting the probe card bears transmission / reception of signals while facing a plurality of chip regions CHIP on the wafer WF. The circuit substrate 10 is attached to a prober connected to a test head (not shown), for example. The wafer WF and the chip area CHIP are indicated by broken lines.
[0016]
The chip region CHIP is provided with external terminals, here bump electrodes BMP. In this chip area CHIP, for example, an input terminal array DIN and an output terminal array DOUT are divided, and the output terminal array DOUT side has a narrower bump array than the input terminal array DIN.
[0017]
An opening 11 is provided in the circuit substrate 10. The opening 11 is provided with opposing connection regions 111 and 112 corresponding to the chip region CHIP. For each of the opposed connection regions 111 and 112, probes 101 and 102 extending from the peripheral edge of the opening 11 to the position of a predetermined external terminal (here, the bump electrode BMP) in the chip region CHIP are provided. As shown in FIG. 1B, the extension sources of the probes 101 and 102 have a portion that is a multilayer (here, two layers). The probes 101 and 102 are configured to be brought into contact with a predetermined bump electrode BMP in the measurement target chip region CHIP by bringing the circuit substrate 10 and the wafer WF close to each other.
[0018]
In this embodiment, the arrangement of the probe 101 in the opposed connection region 111 and the probe 102 in the opposed connection region 112 is different in a region corresponding to the output terminal arrangement DOUT in which the bump electrodes BMP are arranged at a narrow pitch. . As shown in FIG. 1A, the probes 101 and 102 are arranged to correspond to each other except for the bump electrodes BMP adjacent to each other in an area corresponding to the output terminal array DOUT of the chip area CHIP.
[0019]
That is, the probe 101 and the probe 102 are in an arrangement relationship that complements adjacent contacts in a region corresponding to the bump electrode BMP group on the output terminal side. For the bump electrodes BMP group on the input terminal array DIN side that do not have a relatively narrow pitch, all the bump probes are always in contact during measurement. That is, in the probes 101 and 102, the region corresponding to the input terminal array DIN side is the same array.
[0020]
Thus, the probe contact and electrical characteristic tests are satisfied for all the bump electrodes BMP groups in the chip region CHIP by making the opposing connection regions 111 and 112 face each other and approach each other for one chip region CHIP. That is, it is applied to the probe contact of the bump array of the output system which has a very narrow pitch and does not interfere even if the measurement is divided.
[0021]
According to the configuration of the above embodiment, the measurement location is shared by the probe 101 in the opposing connection region 111 and the probe 102 in the opposing connection region 112. This is effective when the terminal portions to be contacted have an extremely narrow pitch.
[0022]
That is, according to the present invention, it can be said that it is possible to provide a technique that does not necessarily require the layout of the probe so as to correspond one-to-one to the narrow pitch terminal arrangement. As a result, the probe card is unlikely to be in a state where the pressure difference and positional deviation of each probe cannot be tolerated in measurement, and can realize a configuration that can easily avoid dangers such as a short circuit between adjacent probes.
[0023]
FIG. 2 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration shown in FIG. Sorting is performed while sharing the connection to be measured with respect to a plurality of terminal portions (not shown) arranged for each chip region CHIP of the wafer WF.
[0024]
That is, different opposing connection regions 111 and 112 are moved so as to approach and connect to each chip region CHIP until the contact of the probe (101, 102) is satisfied with all the terminal portions (not shown) in one chip region CHIP. Control.
[0025]
In FIG. 2, each chip region CHIP has all the probes for the terminal portions of each chip region CHIP in the direction R in the order of the opposing connection region 112 → 111 and in the direction L in the order of measurement of the opposing connection region 111 → 112. The contact of (101, 102) is sequentially satisfied.
[0026]
According to the chip area sorting method using the probe card of the above embodiment, it is possible to give a margin to the connection to be measured by sharing the measurement. That is, the probe contact with high accuracy is realized for all the terminal portions in each chip region by facing and approaching (connecting) several facing connection regions (here, two of 111 and 112).
[0027]
Note that a plurality of sets of the opposing connection regions 111 and 112 may be provided. Thereby, improvement of the simultaneous side constant can be expected. In addition, other layouts of the opposing connection regions 111 and 112 are conceivable. In the above-described embodiment, the configuration of the probe card in which the opposing connection areas 111 and 112 are provided in one opening 11 is shown. However, the probe card is a probe card in which each of the opposing connection areas 111 and 112 is configured by a separate opening. May be.
[0028]
FIG. 3 is a schematic view showing a main configuration of a probe card according to the second embodiment of the present invention. Compared to the configuration of the first embodiment, each of the opposing connection regions is configured by a separate opening.
[0029]
In this embodiment, the opposing connection areas 311 and 312 provided on the circuit substrate 30 constituting the probe card are assumed to have the same relationship as the opposing connection areas 111 and 112 of the first embodiment, respectively. For each of the opposing connection regions 311 and 312, probes 301 and 302 are provided that extend from the periphery to the position of a predetermined external terminal (in this case, the bump electrode BMP) in the chip region CHIP. Although the extension source of the probes 301 and 302 is not shown, it may be a single layer or multiple layers, and can be variously considered.
[0030]
In addition, the terminal arrangement of the chip region CHIP to be measured is configured in the same manner as in the first embodiment. The probes 301 and 302 are configured to contact a predetermined bump electrode BMP in the chip region CHIP to be measured by causing the circuit substrate 30 and the wafer WF to face and approach each other.
[0031]
Also in this embodiment, the probe 301 in the opposing connection region 311 and the probe 302 in the opposing connection region 312 are arranged differently in the region corresponding to the output terminal arrangement DOUT in which the bump electrodes BMP are arranged at a narrow pitch. Have The probes 301 and 302 are regions corresponding to the output terminal array DOUT of the chip region CHIP, and are arranged to correspond to each other except for the bump electrodes BMP adjacent to each other.
[0032]
That is, the probe 301 and the probe 302 are in an arrangement relationship that complements adjacent contact with respect to a region corresponding to the bump electrode BMP group on the output terminal side. For the bump electrode BMP group on the input terminal array DIN side, all the bump probes are always in contact during measurement. That is, in the probes 301 and 302, the region corresponding to the input terminal array DIN side is the same array.
[0033]
Thereby, the contact and measurement of the probe are satisfied for all the bump electrodes BMP group in the chip region CHIP by making the opposing connection regions 311 and 312 face each other and approach each other for one chip region CHIP.
[0034]
According to the configuration of the above embodiment, the measurement location is shared by the probe 301 in the opposing connection region 311 and the probe 302 in the opposing connection region 312. This is effective when the terminal portions to be contacted have an extremely narrow pitch. That is, it can be said that it is possible to provide a technique that does not necessarily require a probe layout that makes a one-to-one correspondence with a narrow pitch terminal array. As a result, the probe card is unlikely to be in a state where the pressure difference and positional deviation of each probe cannot be allowed in measurement, and can realize a configuration that can easily avoid dangers such as a short circuit between adjacent probes. .
[0035]
FIG. 4 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration shown in FIG. Sorting is performed while sharing the connection to be measured with respect to a plurality of terminal portions (not shown) arranged for each chip region CHIP of the wafer WF.
[0036]
That is, the different opposing connection regions 311 and 312 are moved so as to approach and connect to each chip region CHIP until the contact of the probe (301, 302) is satisfied with respect to all terminal portions (not shown) in one chip region CHIP. Control.
[0037]
In FIG. 4, each chip region CHIP is sequentially measured for one column using either one of the opposing connection regions 311, 312 in both directions R and L, and the other opposing connection region ( 311 or 312) is sequentially measured so that one column overlaps. Thereby, the contact of all the probes (301, 302) is satisfied at the terminal portion of each chip region CHIP.
[0038]
Note that a plurality of sets of the opposed connection regions 311 and 312 may be provided. Thereby, improvement of the simultaneous side constant can be expected. In addition, other layouts of the opposed connection regions 311 and 312 are conceivable. In particular, when the opposing connection region is formed by individual openings in the circuit substrate, layout flexibility can be obtained by the probe thinning structure that is a feature of the present invention.
[0039]
FIGS. 5A to 5D are schematic diagrams showing a configuration example of the opposing connection region in the circuit base material to the chip region of the wafer, with respect to the probe card for the purpose of improving the simultaneous side constant, respectively. A probe array (not shown) is provided in each opposing connection region.
[0040]
In FIG. 5A, the opposing connection areas A1 and A2 are in a relationship in which probe arrangements (not shown) complement each other in locations corresponding to adjacent terminal portions to be contacted in the chip area in a specific area. The specific region includes a region where the terminal portions to be contacted in the corresponding chip region have a narrow pitch. Also, with the sharing of inspection measurement, it is important that the inspection measurement is not hindered even if the contact is thinned out.
[0041]
The inspection measurement for each chip area of the wafer is accomplished by sequentially sorting the two chip areas overlapping in the direction in which the opposing connection areas of the same probe array are arranged. To further increase the number of simultaneous measurements, the number of opposing connection areas A1 and A2 may be increased. In that case, the layout of each opposing connection area is not limited.
[0042]
In FIG. 5B, the opposed connection regions B1 and B2 are in a relationship in which a probe array (not shown) complements a portion corresponding to an adjacent terminal portion to be contacted in a chip region in a specific region. The specific region includes a region where the terminal portions to be contacted in the corresponding chip region have a narrow pitch. Also, with the sharing of inspection measurement, it is important that the inspection measurement is not hindered even if the contact is thinned out.
[0043]
The inspection measurement for each chip area of the wafer is accomplished by sequentially sorting the two chip areas overlapping in the direction in which the opposing connection areas of the same probe array are arranged. To further increase the number of simultaneous measurements, the set of opposing connection areas B1 and B2 may be increased. In that case, the layout of each opposing connection area is not limited.
[0044]
In FIG. 5C, the opposed connection regions C1 and C2 are in a relationship in which a probe array (not shown) complements a portion corresponding to an adjacent terminal portion to be contacted in the chip region in a specific region. The specific region includes a region where the terminal portions to be contacted in the corresponding chip region have a narrow pitch. Also, with the sharing of inspection measurement, it is important that the inspection measurement is not hindered even if the contact is thinned out.
[0045]
The inspection measurement for each chip area of the wafer is accomplished by sequentially sorting the two chip areas overlapping in the direction in which the opposing connection areas of the same probe array are arranged. To further increase the number of simultaneous measurements, the set of opposing connection areas C1 and C2 may be increased. In that case, the layout of each opposing connection area is not limited.
[0046]
FIG.5 (d) is a modification of FIG.5 (c). This is a configuration for the purpose of improving the simultaneous constant and is a configuration in the case where there is a difficulty in arranging the probes. Another set of opposing connection areas C1 and C2 is provided with one chip area separated. In this way, a margin can be obtained for the wiring of the probe. Control is also performed so as not to measure twice even in such a sort. Such a device can be easily considered for the set of opposed connection regions in FIGS. 5A and 5B.
[0047]
Furthermore, according to each said embodiment, although the structure which shares an electrical measurement with two opposing connection area | regions with respect to one chip area was shown, it is not restricted to this. You may implement | achieve the structure which shares an electrical measurement with two or more many opposing connection area | regions with respect to one chip area | region. Thereby, the margin regarding the precision of the probe arrangement | sequence in each opposing connection area | region can be enlarged. As a result, the probe card is unlikely to be in an unacceptable state of pressure difference or positional deviation between the probes in measurement, and the risk of short between adjacent points can be reduced.
[0048]
According to the probe card and chip area sorting method in each of the embodiments as described above, the probe card is suppressed to a level where the probe density is acceptable, and it is possible to secure as many simultaneous measurements as possible. Become. In addition, since the arrangement pitch of the probes can be reduced and the extension source can be prevented from being multi-layered, the maintenance can be facilitated, and a multi-cavity probe card configuration that can easily maintain high reliability can be realized. In addition to the control that is not measured twice in sorting, the time taken for the wafer probing test is further reduced by the large number of pieces, and high efficiency can be achieved.
[0049]
【The invention's effect】
As described above, according to the present invention, since the probe card shares the connection to be measured with respect to the plurality of terminal portions arranged in one chip region to be opposed, the accuracy of the probe arrangement, It is possible to reduce the configuration and burden associated with consideration for reliability.
[0050]
If a multi-cavity configuration is realized, the wafer probing test time can be reduced and the efficiency can be improved with reliability even when the wafer diameter is increased. As a result, it is possible to provide a chip area sorting method using a high-efficiency multi-piece probe card that can be easily repaired and maintained and easily maintain high reliability.
[Brief description of the drawings]
FIGS. 1A and 1B show the main configuration of a probe card according to a first embodiment of the present invention, respectively, FIG. 1A is an overview from the top, and FIG. It is the schematic which shows the arbitrary cross sections of.
2 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration shown in FIG.
FIG. 3 is a schematic view showing a main configuration of a probe card according to a second embodiment of the present invention.
4 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration of FIG. 3;
FIGS. 5A to 5D are schematic diagrams showing a configuration example of an opposing connection region in a circuit base material to a chip region of a wafer, with respect to a probe card for the purpose of improving a simultaneous constant, respectively. .
[Explanation of symbols]
10, 30 ... Circuit substrate (probe card)
11 ... Openings 111, 112, 311, 312, A1, A2, B1, B2, C1, C2 ... Opposing connection regions,
101, 102, 301, 302 ... probe BMP ... bump electrode WF ... wafer CHIP ... chip region DIN ... array of input terminals DOUT ... array of output terminals

Claims (2)

A circuit substrate for transferring signals by opposing an array of a plurality of input terminals on a wafer and an array of a plurality of output terminals having a narrower pitch than the input terminals to be adjacent to a plurality of chip regions,
Opposing connection regions provided corresponding to each of the chip regions in the circuit substrate,
For each of the opposing connection regions, the chip region is extended to a position corresponding to the output terminals except for all the input terminals in the chip region and adjacent to each other, and the circuit substrate and the wafer are brought closer to each other in the chip region. A plurality of electrical connection members that contact the terminals;
The electrical connection member in one of the opposing connection regions and the electrical connection member in another one of the opposing connection regions are in an arrangement relationship that complements mutually adjacent locations of the output terminals to be contacted. A probe card characterized by being. With respect to sorting into each chip area of the probe card responsible for sending and receiving signals by facing the plurality of adjacent chip areas and the arrangement of the plurality of output terminals narrower than the input terminals on the wafer,
The probe card has opposing connection areas in which electrical connection members are arranged on the periphery corresponding to each of the chip areas, and the electrical connection members relate to each of the opposing connection areas, and all of the input terminals in the chip area. And it extends to a position corresponding to the output terminal excluding a location adjacent to each other, the electrical connection member in one of the opposing connection regions and the electrical connection member in another one of the opposing connection regions, In an arrangement relationship that complements the adjacent portions of the output terminals to be contacted,
The movement control is performed so as to approach and connect the different opposing connection areas to each chip area until the contact of the electrical connection member is satisfied for all the terminals in the chip area,
A chip area sorting method using a probe card characterized by the above.

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