JP2002134571A - Probe card and chip region sorting method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a probe card that is easy to keep high reliability as reducing the density of a probe arrangement when contact regions (such as pads or bumps) under measurement are arranged with fine pitches, and a chip region sorting method using the same. SOLUTION: A circuit board 10 constituting a probe card is loaded on a prober connected to a test head not illustrated. In an opening 11 of the circuit board 10, opposed connection regions 111, 112 are arranged corresponding to a chip region CHIP. Probes 101 in the opposed connection region 111 and probes 102 in the opposed connection region 112 are different in the arrangement in the region corresponding to an output terminal arrangement DOUT in which bump electrodes BMP are arranged with fine pitches, and are arranged so as to correspond except for adjacent bump electrodes BMP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a probe card for measuring electrical characteristics by mechanically bringing a probe into contact with an LSI chip pad in a wafer state, and a chip area sorting method using the same.

[0002]

2. Description of the Related Art A probe card is used for a test in a wafer state before an assembling process of LSI manufacturing. The probe card has a probe that comes into contact with each of the bonding pads in the LSI chip area to be measured. A test signal or a test pattern is input from the probe to the LSI chip.

[0003] The probe card is connected to a tester and forms part of a test system. The tester compares the output value from the LSI with an expected value via a probe card to determine whether the function of the LSI is good or not, and measures input / output signals, analog values such as voltage and current of a power supply, and the like. An LSI that is selected as a non-defective product through such a wafer probing test is sent to an assembly process.

In recent years, the diameter of wafers has been increasing, and the number of chips obtained per wafer has been increasing. Along with this, the time spent on the wafer probing test as described above increases, and higher efficiency is desired.

In order to test a plurality of chips as simultaneously as possible, a plurality of probe cards have been used. In particular, a center pad type LSI chip or a type of LS having a relatively small number of pads
A plurality of probe cards are used for the I chip.

[0006]

The diversification of LSI chips is remarkable, and the number of data inputs / outputs is increasing. Accordingly, the number of pads per chip increases, and many pads are arranged around the chip at a narrow pitch. In this case, it becomes difficult to apply each probe of the probe card to each pad (or bump).

It is a generally known technique to make the extension source multi-layered for each probe of the probe card. Thereby, even when the arrangement pitch of the contact areas (pads, bumps, etc.) is smaller than the diameter of the probe wire (base material diameter), it is possible for each probe to make contact.

However, when the pitch of the contact area (pads, bumps, etc.) is further narrowed, it is difficult to eliminate the reliability concerns only with the above technique. The configuration in which the probe is applied to all of the contact areas of the measurement target is likely to be in a state where the pressure difference and the displacement of each probe in the measurement cannot be tolerated, and further increases the risk of short circuit between adjacent probes.

The present invention has been made in view of the above circumstances, and reduces the density of the probe array when the contact area (pad, bump, etc.) to be measured has a narrow pitch.
An object of the present invention is to provide a probe card that easily maintains high reliability and a chip area sorting method using the same.

[0010]

A probe card according to the present invention is a circuit substrate for transmitting and receiving signals by facing a plurality of chip regions on a wafer, wherein the circuit substrate includes:
The semiconductor device according to the present invention is characterized in that each of the plurality of terminal portions arranged in one of the chip regions has a respective opposing connection region which shares connection to be measured.

According to the probe card of the present invention, a plurality of terminals arranged in one chip area are measured several times. By sharing connections, adjacent connections can be thinned out at that time.

A probe card according to a more preferred embodiment of the present invention is a circuit substrate which is opposed to a plurality of chip regions on a wafer and is responsible for transmitting and receiving signals, and which corresponds to each of the chip regions in the circuit substrate. With respect to the opposing connection area provided as
A plurality of electrical connection members that extend to a predetermined position in the chip region and come into contact with a predetermined portion of the chip region by bringing the circuit substrate and the wafer close to each other; In the above structure, the semiconductor device is provided so as to correspond to a predetermined portion to be contacted in the chip region except for an adjacent portion.

[0013] According to the probe card of the present invention, the electrical connection member is provided in the specific region except for an adjacent portion among predetermined portions to be contacted in the chip region. As a result, more stable connection can be achieved even when the predetermined portions to be in contact with each other are arranged at an extremely narrow pitch.

In the probe card according to the present invention, the electrical connection member in one of the opposed connection areas and the electrical connection member in another of the opposed connection areas are:
In the specific region, the arrangement is such that the positions corresponding to adjacent predetermined portions to be contacted in the chip region are complementarily arranged. As a result, the density of the electrical connection members can be changed to a density that does not hinder.

[0015] A chip area sorting method using a probe card according to the present invention relates to sorting of a probe card, which is opposed to a plurality of chip areas on a wafer and is responsible for transmitting and receiving signals, into chip areas. It is characterized in that sorting is performed while sharing connections to be measured to a plurality of arranged terminals.

According to the chip area sorting method using the probe card according to the present invention, it is possible to provide a margin for the connection to be measured.

A chip area sorting method using a probe card according to a more preferred embodiment of the present invention relates to a method of sorting a probe card, which is opposed to a plurality of chip areas on a wafer and is responsible for transmitting and receiving signals, into chip areas. The probe card is provided with an opposing connection area where electric connection members are arranged on the periphery corresponding to each of the chip areas, and the probe in one of the opposing connection areas and the probe in another one of the opposing connection areas are provided. In the specific region, the electrical connection member has a positional relationship of complementing a portion corresponding to an adjacent predetermined portion to be contacted in the chip region, and the electrical connection member is electrically connected to all predetermined portions in the chip region. The movement is controlled so that the different opposing connection areas approach and connect to the respective chip areas until the contact of the connection member is satisfied. It is characterized in.

According to the chip area sorting method using the probe card according to the present invention, the electric connection members provided in each of the opposing connection areas play a role, and several opposing connection areas face each other and approach (connect). ) Ensures that all the electrical connection members in a given chip area are in contact with each other. As a result, the accuracy with which the electrical connection member contacts each of the predetermined portions to be contacted in the plurality of chip regions on the wafer is increased.

[0019]

1 (a) and 1 (b) show the configuration of a main part of a probe card according to a first embodiment of the present invention. FIG. 1 (a) is a schematic view from the top, and FIG. (b) is a schematic diagram showing an arbitrary cross section from the side.

Circuit substrate 10 constituting probe card
Is responsible for transmitting and receiving signals in opposition to a plurality of chip areas CHIP on the wafer WF. The circuit substrate 10 is mounted on, for example, a prober connected to a test head (not shown). The wafer WF and the chip area CHIP are indicated by broken lines.

External terminals, here bump electrodes BMP, are provided in the chip area CHIP. The chip area CHIP is divided into, for example, an input terminal array DIN and an output terminal array DOUT.
The arrangement of the output terminals on the DOUT side as compared with N is a bump arrangement with a narrower pitch.

The circuit board 10 is provided with an opening 11. The opening 11 is provided with opposing connection regions 111 and 112 corresponding to the chip region CHIP. For each of the facing connection regions 111 and 112, the opening 1
Probe tips 101 and 102 are provided extending from the peripheral edge of the chip 1 to a position of a predetermined external terminal (here, a bump electrode BMP) in the chip area CHIP. As shown in FIG. 1B, the extension sources of the probes 101 and 102 have a portion that becomes a multilayer (here, two layers). These probes 101 and 102
A predetermined bump electrode B in the chip area CHIP to be measured by bringing the circuit base 10 and the wafer WF close to each other.
It is configured to be in contact with MP.

In this embodiment, the opposing connection area 11
The probe 101 in No. 1 and the probe 102 in the opposing connection region 112 have different arrangements in a region corresponding to an array DOUT of output terminals in which the bump electrodes BMP are arranged at a narrow pitch. As shown in FIG. 1A, the probes 101 and 102 are arranged in an array DOU of output terminals of the chip area CHIP.
In the region corresponding to T, the bump electrodes BMP adjacent to each other
It is arranged to correspond except for.

That is, the probe 101 and the probe 102
With respect to a region corresponding to the bump electrode BMP group on the output terminal side, there is an arrangement relationship in which adjacent contacts are complemented. In addition,
Regarding the bump electrodes BMP group on the input terminal array DIN side where the pitch is not relatively narrow, all the bump probes are always in contact at the time of measurement. That is, in the probes 101 and 102, the regions corresponding to the input terminal array DIN side have the same array.

Thus, by making the opposing connection regions 111 and 112 face and approach each other in one chip region CHIP, the contact of the probe and the electrical characteristic test are satisfied for all the bump electrodes BMP group in the chip region CHIP. You. That is, the present invention is applied to a probe contact of an output-type bump arrangement having a very narrow pitch and having no problem even if measurement is divided.

According to the configuration of the above embodiment, the measurement location is shared by the probe 101 in the opposing connection area 111 and the probe 102 in the opposing connection area 112. This allows
This is effective when the terminals to be contacted have an extremely narrow pitch.

That is, according to the present invention, it can be said that there can be provided a technique which does not necessarily require a probe layout such that all terminal arrangements correspond to a narrow pitch terminal arrangement on a one-to-one basis.
As a result, in the probe card, it is possible to realize a configuration in which the pressure difference and the displacement of the respective probes are hardly allowed to be unacceptable in the measurement, and a danger such as a short circuit between adjacent probes is easily avoided.

FIG. 2 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration of FIG.
Sorting is performed while sharing connections to be measured to a plurality of terminal units (not shown) arranged for each chip area CHIP of the wafer WF.

That is, the probes (101, 102) are provided for all the terminal portions (not shown) in one chip area CHIP.
Different opposing connection areas 1 until the contact is satisfied
Movement control is performed so that 11, 11 approaches and connects to each chip area CHIP.

In FIG. 2, each chip area CHIP is
In the direction R, according to the order of the opposing connection regions 112 → 111, and in the direction L, according to the measurement order of the opposing connection regions 111 → 112.
All the probes (10
1,102) are sequentially satisfied.

According to the chip area sorting method using the probe card according to the above-described embodiment, the connection to be measured can be given a margin by sharing measurement. That is, by opposing and approaching (connecting) several opposing connection regions (here, two of 111 and 112), highly accurate contact of the probe with respect to all the terminals in each chip region is realized.

It should be noted that a plurality of sets of the opposing connection regions 111 and 112 may be provided. Thereby, the improvement of the simultaneous side constant can be expected. Other layouts of the opposing connection regions 111 and 112 are also conceivable. Further, in the above-described embodiment, the configuration of the probe card in which the opposing connection areas 111 and 112 are provided in one opening 11 has been described.
It may be a probe card in which each of 11, 11 is constituted by a separate opening.

FIG. 3 is a schematic view showing a configuration of a main part of a probe card according to a second embodiment of the present invention. Compared to the configuration of the first embodiment, each opposing connection region is formed by a separate opening.

In this embodiment, the opposing connection areas 311 and 3 provided on the circuit substrate 30 constituting the probe card
12 and the counter connection region 1 of the first embodiment, respectively.
It is assumed that they have the same relationship as 11, 112. With respect to each of the opposing connection regions 311 and 312, probes 301 and 302 extending from the peripheral portion thereof to positions of predetermined external terminals (here, bump electrodes BMP) in the chip region CHIP.
Is provided. Although the extension sources of the probes 301 and 302 are not shown, a single layer or a multilayer may be used, and various types are considered.

In addition, the terminal arrangement of the chip area CHIP to be measured is configured in the same manner as in the first embodiment. The probes 301 and 302 are configured so that the circuit substrate 30 and the wafer WF face and approach each other to contact a predetermined bump electrode BMP in the chip area CHIP to be measured.

Also in this embodiment, the opposing connection region 3
The probe 301 of FIG. 11 and the probe 302 of the opposing connection region 312 have different arrangements in a region corresponding to the array of output terminals DOUT in which the bump electrodes BMP are arranged at a narrow pitch. The probes 301 and 302 are arranged so as to correspond to each other except for the bump electrodes BMP adjacent to each other in a region corresponding to the output terminal array DOUT of the chip region CHIP.

That is, the probe 301 and the probe 302
With respect to a region corresponding to the bump electrode BMP group on the output terminal side, there is an arrangement relationship in which adjacent contacts are complemented. In addition,
With respect to the bump electrodes BMP group on the input terminal array DIN side, all the bump probes are always in contact at the time of measurement. That is, in the probes 301 and 302, the array of input terminals DI
The regions corresponding to the N side have the same arrangement.

Thus, the contact and measurement of the probe are satisfied for all the bump electrodes BMP in the chip area CHIP by making the opposing connection areas 311 and 312 face and approach each other in one chip area CHIP.

According to the configuration of the above embodiment, the measurement location is shared by the probe 301 in the opposing connection area 311 and the probe 302 in the opposing connection area 312. This allows
This is effective when the terminals to be contacted have an extremely narrow pitch. In other words, it can be said that a technique can be provided which does not necessarily require a probe layout that makes one-to-one correspondence with a narrow pitch terminal arrangement. As a result, the probe card is extremely unlikely to be in a state where the pressure difference between the probes and the positional deviation cannot be tolerated in the measurement, and
It is possible to realize a configuration that can easily avoid a danger such as a short circuit between adjacent circuits.

FIG. 4 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration of FIG.
Sorting is performed while sharing connections to be measured to a plurality of terminal units (not shown) arranged for each chip area CHIP of the wafer WF.

That is, the probe (301, 302) is provided for all the terminal portions (not shown) in one chip area CHIP.
Different opposing connection areas 3 until the contact is satisfied
Movement control is performed so that 11, 1112 approaches and connects to each chip area CHIP.

In FIG. 4, each chip area CHIP is
One row is sequentially measured first using one of the opposing connection areas 311 and 312 in both directions R and L, and when returning and sorting, 1 row is used using the other opposing connection area (either 311 or 312). The measurement is performed sequentially so that the columns overlap. This satisfies the contact of all the probes (301, 302) at the terminal of each chip area CHIP.

Note that a plurality of sets of the opposing connection regions 311 and 312 may be provided. Thereby, the improvement of the simultaneous side constant can be expected. Other layouts of the opposing connection regions 311 and 312 are also conceivable. In particular, when the opposing connection region is formed by the individual openings in the circuit substrate, the degree of freedom in layout can be obtained by the thinning structure of the probe, which is a feature of the present invention.

FIGS. 5 (a) to 5 (d) are schematic views showing examples of the structure of a connection area on a circuit substrate to a chip area of a wafer, with respect to a probe card for the purpose of improving the simultaneous constant. is there. A probe array (not shown) is provided in each of the facing connection regions.

In FIG. 5A, the opposing connection areas A1 and A2 are arranged in such a manner that a probe arrangement (not shown) complements a portion corresponding to an adjacent terminal portion to be contacted in a chip region in a specific region. It is in. The specific area is
There is a region where the terminal portions to be contacted in the corresponding chip region have a narrow pitch. In addition, with the sharing of inspection and measurement,
It is important that thinning out the contact does not interfere with the test measurement.

Inspection measurement for each chip region of the wafer is achieved by sorting sequentially while overlapping two chip regions in the direction in which the opposing connection regions of the same probe array are arranged.
To further increase the number of simultaneous measurements, the number of sets of the opposing connection areas A1 and A2 may be increased. At that time, the layout of each opposing connection area is not limited.

In FIG. 5B, the opposing connection regions B1 and B2 are arranged in such a manner that a probe arrangement (not shown) complements a portion corresponding to an adjacent terminal portion to be contacted in the chip region in a specific region. It is in. The specific area is
There is a region where the terminal portions to be contacted in the corresponding chip region have a narrow pitch. In addition, with the sharing of inspection and measurement,
It is important that thinning out the contact does not interfere with the test measurement.

Inspection measurement for each chip region of the wafer is achieved by sequentially sorting while overlapping two chip regions in the direction in which the opposing connection regions of the same probe arrangement are arranged.
To further increase the number of simultaneous measurements, the number of sets of the opposing connection areas B1 and B2 may be increased. At that time, the layout of each opposing connection area is not limited.

In FIG. 5 (c), the opposing connection areas C1 and C2 are arranged in such a manner that a probe arrangement (not shown) complements a portion corresponding to an adjacent terminal portion to be contacted in the chip region in a specific region. It is in. The specific area is
There is a region where the terminal portions to be contacted in the corresponding chip region have a narrow pitch. In addition, with the sharing of inspection and measurement,
It is important that thinning out the contact does not interfere with the test measurement.

Inspection measurement for each chip area of the wafer is sequentially sorted and overlapped by two chip areas in the direction in which opposing connection areas of the same probe arrangement are arranged.
To further increase the number of simultaneous measurements, the number of sets of the opposing connection areas C1 and C2 may be increased. At this time, the layout of each opposing connection area is not limited.

FIG. 5D is a modification of FIG. 5C. This is a configuration for the purpose of improving the simultaneous side constant and in a case where there is difficulty in arranging the probes. Opposing connection areas C1 and C
Two sets are separated from one chip area and another set is provided. By doing so, a margin is provided for the wiring of the probe. Control is performed so as not to be measured twice even in the sorting with such a configuration. 5 (a) and 5
Such a contrivance can be easily considered for the set of the opposing connection regions in FIG.

Furthermore, according to each of the above embodiments, the configuration has been described in which electrical measurement is shared by two opposing connection regions for one chip region, but the present invention is not limited to this. A configuration in which electrical measurement is shared by two or more large number of opposing connection regions for one chip region may be realized. Thereby, the margin regarding the accuracy of the probe arrangement in each of the opposing connection regions can be increased. As a result, the probe card is extremely unlikely to be in a state where the pressure difference and displacement between the probes cannot be tolerated in measurement, and can reduce the risk of short-circuit between adjacent probes.

According to the method of sorting the probe card and the chip area in each of the embodiments described above, the probe card can suppress the density of the probes to an acceptable level, and secure as many simultaneous measurements as possible. Is also possible. Further, since the reduction in the arrangement pitch of the probes and the increase in the number of layers at the expansion source are suppressed, the configuration of a multi-cavity probe card that facilitates maintenance and easily maintains high reliability can be realized. In addition, the time taken for the wafer probing test can be further reduced and the efficiency can be improved by the multi-cavity as well as the control that is not measured twice in the sorting.

[0054]

As described above, according to the present invention, the probe card is configured to share the connection to be measured to the plurality of terminals arranged in one opposed chip area. It is possible to reduce the configuration and the burden of considering the accuracy and reliability of the needle arrangement.

If a multi-cavity configuration is realized,
This also contributes to a reduction in the wafer probing test time and an increase in the efficiency with reliability even when the diameter of the wafer is increased. As a result, it is possible to provide a chip area sorting method using a high-efficiency multi-cavity probe card that is easy to repair and maintain and easily maintains high reliability.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) show a main part configuration of a probe card according to a first embodiment of the present invention, respectively.
(A) is an outline view from above, and (b) is a schematic view showing an arbitrary cross section from the side.

FIG. 2 is a schematic diagram showing an example of a chip area sorting method using the probe card having the configuration of FIG.

FIG. 3 is a schematic view illustrating a main configuration of a probe card according to a second embodiment of the present invention.

FIG. 4 is a schematic view showing an example of a chip area sorting method using the probe card having the configuration of FIG. 3;

FIGS. 5A to 5D are schematic diagrams each showing an example of a configuration of an opposing connection region in a circuit base material to a chip region of a wafer, with respect to a probe card aiming at improvement of a simultaneous-side constant. .

[Explanation of symbols]

10, 30: Circuit substrate (probe card) 11: Opening 111, 112, 311, 312, A1, A2, B1,
B2, C1, C2 ... facing connection areas, 101, 102, 301, 302 ... probes BMP ... bump electrodes WF ... wafers CHIP ... chip areas DIN ... array of input terminals DOUT ... array of output terminals

Continued on the front page F term (reference) 2G003 AA07 AA10 AG03 AG04 AG08 AG12 AG20 AH05 AH07 2G011 AA02 AA17 AC05 AC14 AE03 AF07 2G032 AF02 AL03 AL05 4M106 AA01 BA01 CA01 DD04 DD10 DD12 DD13 DD16 DD17 DD30

Claims (5)

[Claims] 1. A circuit substrate for transmitting and receiving signals by facing a plurality of chip regions on a wafer, wherein a plurality of terminals arranged in one of the chip regions are measured in the circuit substrate. A probe card having respective opposing connection areas sharing the connection. 2. A circuit substrate for transmitting and receiving signals by facing a plurality of chip regions on a wafer, comprising: a facing connection region provided for each of the chip regions on the circuit substrate; A plurality of electrical connection members extending to a predetermined position in the chip region for each of the connection regions, and bringing the circuit substrate and the wafer into contact with each other to contact a predetermined portion of the chip region; The probe card according to claim 1, wherein the members are arranged in the specific region so as to correspond to each other except for an adjacent portion among predetermined portions to be contacted in the chip region. 3. The electrical connection member in one of the opposed connection regions and the electrical connection member in another of the opposed connection regions are adjacent to each other in the chip region in the specific region. The probe card according to claim 2, wherein the probe card has an arrangement relationship that complements a portion corresponding to the predetermined portion. 4. A method according to claim 1, further comprising the step of: sorting a plurality of chip areas of the probe card facing the plurality of chip areas on the wafer to send and receive signals to a plurality of terminal portions arranged for each of the chip areas. A chip area sorting method using a probe card, wherein sorting is performed while sharing connections. 5. A method according to claim 1, wherein the probe card is arranged to face a plurality of chip areas on a wafer and transmit / receive a signal to the chip areas. The probe card has an electrical connection member at a periphery corresponding to each of the chip areas. An opposed connection region to be arranged is provided, and the probe in one of the opposed connection regions and the electrical connection member in another one of the opposed connection regions are in contact with the chip region in the specific region. The positions corresponding to adjacent predetermined portions to be complemented are arranged so as to complement each other, and the opposing connection regions that are different from each other until the contact of the electrical connection member is satisfied with respect to all the predetermined portions in the chip region. A chip area sorting method using a probe card, which is controlled so as to approach and connect to the chip area.