JP3153285B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor.

[0002]

2. Description of the Related Art A field effect transistor is widely used as a single unit or as an individual semiconductor element for forming a semiconductor integrated circuit.

The most common type of such a field-effect transistor is described in, for example, a document (“Ultra-high-speed MOS device”).
Baifukan (Showa 61) pp. 6 to 12). Hereinafter, the structure and operation of the conventional MOSFET will be described with reference to FIG. FIG. 15 is a cross-sectional view schematically showing a conventional MOSFET cut along the channel length direction.

[0004] This MOSFET has a silicon substrate 11
A field oxide film 13 for element isolation formed on a predetermined portion of the substrate 11, an active region 15 surrounded by the field oxide film 13, and a gate insulating film formed on a predetermined portion of the active region 15. Membrane 17
And the gate electrode 1 formed on the gate insulating film 17.
9 and diffusion layers 21 to be source / drain regions formed in active region portions on both sides of the gate electrode 19, respectively.
It is configured to include: And the gate electrode 1
9, an intermediate insulating film 2 on a substrate 11 having a diffusion layer 21 and the like.
3 is provided, and for example, an aluminum wiring 27 is connected to the diffusion layer 21 through a contact hole 25 provided in a portion of the intermediate insulating film 23 corresponding to the diffusion layer 21.

In this MOSFET, when the MOSFET is of an N-channel type, one diffusion layer 21 (diffusion layer serving as a source region) is set to a ground level potential and the other diffusion layer 21 (drain region) is set to a ground level. Diffusion layer)
Is electrically connected to a high-level potential, and when the potential of the gate electrode 17 is set to a potential equal to or higher than the threshold voltage _Vth , a channel is formed on the surface of the substrate portion below the gate electrode 17 and the current is increased. It flows from the drain region to the source region.

In order to achieve high integration and miniaturization of a semiconductor integrated circuit, miniaturization of a field effect transistor is very important.

[0007]

However, when the size of a field effect transistor is reduced, the gate length is shortened according to the principle of the proportional reduction rule, so that the electric field in the gate length direction becomes strong. There was a problem that occurs.

Further, when the gate length is shortened, the driving capability of the field effect transistor increases, but there is a problem that a so-called short channel effect occurs in which a leak current increases when the potential of the gate electrode is lower than a threshold value. there were.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a field effect transistor in which the above-mentioned problems associated with downsizing are less likely to occur than in the prior art.

[0010]

According to a first aspect of the present invention, there is provided a field effect transistor having a first window having a window exposing a substrate portion corresponding to an active region of the transistor. A plurality of grooves are provided in a substrate portion corresponding to the above-mentioned active region in parallel with each other along the channel length direction of the field-effect transistor. A second insulating film is provided on the surface of the substrate portion corresponding to the active region, and a gate electrode is provided on each of the inner walls of the plurality of grooves and on a predetermined portion of the second insulating film. A field effect transistor provided with a diffusion layer serving as a source / drain region in a portion other than the portion where the plurality of grooves are formed and the portion where the gate electrode is formed in the substrate portion corresponding to the active region of FIG. In register, characterized in that the depth of the groove closest to the drain region diffusion layer of the plurality of grooves described above, are deeper than the depth of the other groove.

According to the field effect transistor of the second invention, the semiconductor substrate is provided with the first insulating film having the window exposing the substrate portion corresponding to the active region of the transistor. In the substrate portion corresponding to the region, a plurality of grooves whose longitudinal direction is perpendicular to the channel length direction of the field effect transistor are provided along the channel length direction of the field effect transistor, and each inner wall of the plurality of grooves is provided. A second insulating film is provided on the surface of the substrate corresponding to the active region, and a gate electrode is provided on each of the inner walls of the plurality of grooves and on a predetermined portion of the second insulating film. A diffusion layer serving as a source / drain region is formed in a portion of the substrate portion corresponding to the active region, other than the portion where the plurality of grooves are formed and the portion where the gate electrode is formed. In the field effect transistor Aru only in, characterized in that the impurity concentration of the aforementioned semiconductor substrate, are Chigae between from the substrate surface to the bottom of the aforementioned groove.

Further, according to the field effect transistor of the third invention, the first insulating film having the window exposing the substrate portion corresponding to the active region of the transistor is provided on the semiconductor substrate. In the substrate portion corresponding to the region, a plurality of grooves whose longitudinal direction is perpendicular to the channel length direction of the field effect transistor are provided along the channel length direction of the field effect transistor, and each inner wall of the plurality of grooves is provided. A second insulating film is provided on the surface of the substrate corresponding to the active region, and a gate electrode is provided on each of the inner walls of the plurality of grooves and on a predetermined portion of the second insulating film. A diffusion layer serving as a source / drain region is formed in a portion of the substrate portion corresponding to the active region, other than the portion where the plurality of grooves are formed and the portion where the gate electrode is formed. In the field-effect transistor, the entire or part of the thickness of the second insulating film provided on the inner wall of the groove from the groove bottom to the substrate surface is set to the thickness of the second insulating film provided on the substrate surface. It is characterized by being different.

In practicing the first invention, it is preferable that the longitudinal direction of the above-mentioned groove is perpendicular to the above-mentioned channel length direction, and the length is the same as the channel width of the field effect transistor. is there.

[0014]

[0015]

According to the first to third aspects of the present invention, the potential of the gate electrode (hereinafter, also referred to as gate potential) is FE.
Since the leak current generated when the value is equal to or smaller than the threshold value of T flows along the groove (see FIG. 4A), a conventional planar FET having the same gate length (for example, FIG. 15). , "Conventional FET"). When the gate potential is equal to or higher than the threshold value and is relatively low, the drain current flows along the groove, so that the effective gate length is longer than that of the conventional FET. Therefore, the short channel effect is less likely to occur than in the conventional FET. Also,
When the gate potential is equal to or higher than the threshold value and becomes relatively high, the substrate portion between the trenches is depleted, and the channel is formed so as to pass through the substrate portion between the trenches (see FIG. 4B). It is almost the same as FET.

Further, in the case of the first invention in which the depth of the groove provided at the position closest to the drain region diffusion layer among the plurality of grooves is made deeper than the depths of the other grooves, in the case of the first invention, The channel is formed at a position farther from the gate oxide film than the conventional FET. Therefore, as the gate length is shortened due to miniaturization of the element and the electric field between the source and the drain is increased, electrons (hot carriers) having high energy near the drain are less likely to enter the gate oxide film than before (capture). Is difficult to do).

In the case of the second invention in which the impurity concentration of the semiconductor substrate is different from the surface of the substrate to the bottom of the groove, for example, the surface formed on a P-type substrate (including a P-well) may be used. N-channel MOSFE of channel type operation
Considering the example of T, the following operation is obtained.

In this case, as the impurity concentration of the substrate increases, the threshold voltage increases. Therefore, when the impurity concentration is higher in the substrate portion on the groove bottom side than in the substrate surface portion (that is, the threshold value is higher in the groove bottom portion) and when the gate potential is equal to or less than the threshold value in the groove bottom portion (the FET is in the off state). In (2), the leak current flows along the groove, so that the leak current is smaller than that of the conventional FET. Also, in this configuration, when the gate potential becomes equal to or higher than the threshold value at the bottom of the groove (the ON state of the FET), the channel is already formed at the substrate portion between the grooves because the channel is already formed. In comparison, the switching speed is faster. When the gate potential further increases, the substrate between the trenches is depleted, and the channel is formed so as to pass through the substrate between the trenches.
It is almost the same as T.

On the other hand, even when the impurity concentration is lower in the substrate portion on the groove bottom side than in the substrate surface portion, the size of the groove, the groove interval,
By adjusting the impurity concentration of the substrate, when the gate potential is equal to or lower than the threshold value of the surface portion of the substrate (off state), it is considered that a leak current flows along the groove, so that the leak current is smaller than that of the conventional FET. . Also, in this case, when the gate potential is equal to or higher than the threshold value of the substrate surface portion (on state), the channel is already formed in the substrate portion on the bottom side of the groove because the channel is already formed. The switching speed is faster than that of. Further, when the gate potential further increases, the substrate portion between the trenches is depleted and the channel is formed so as to pass through the substrate portion between the trenches.
The driving ability is almost the same as that of the conventional FET.

In a FET, the threshold voltage generally increases as the thickness of the gate insulating film increases. Therefore, the entire or a part of the thickness from the bottom of the second insulating film provided on the inner wall of the groove to the surface of the substrate is reduced. The third insulating film is different from the second insulating film in thickness.
In the case of the configuration of the present invention, the same operation as the case where the impurity concentration is changed can be obtained. In other words, when the thickness of the insulating film in the trench is larger than that of the substrate surface, the same effect can be obtained as when the impurity concentration is higher in the substrate portion on the groove bottom side than in the substrate surface portion, and vice versa. Has the same effect as when the impurity concentration is lower in the substrate portion on the groove bottom side than in the substrate surface portion.

As described above, the second type having the different impurity concentration is used.
The third invention in which the structure of the invention and the thickness of the second insulating film are partially different.
According to the configuration of the invention, the switching time can be shortened as compared with the case where it is not, and the effect that the gate potential that can change the channel path depending on the difference of the impurity or the thickness of the insulating film can be controlled can be obtained. .

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a field effect transistor (hereinafter sometimes abbreviated as "FET") of the present invention will be described with reference to the drawings. However, the drawings used in the following description schematically show the dimensions, shapes, and arrangements of the components so that the present invention can be understood. Further, in each of the drawings used for the description, the same components are denoted by the same reference numerals, and overlapping description is omitted.

1. First embodiment 1-1. Description of Structure FIG. 1 is a view for explaining the structure of an FET according to a first embodiment of the present invention, and is a cross-sectional view of the FET cut along the channel length direction (the following embodiments are described). The same applies to the structural explanatory diagrams.)

In the FET of the first embodiment, a window 35 exposing a substrate portion 33 corresponding to an active region of a transistor is formed in, for example, a silicon substrate 31 as a semiconductor substrate.
A first insulating film 35 having a is provided. This first
The insulating film 35 becomes a field oxide film for element isolation.

Further, in the FET of the first embodiment, the substrate portion 33 corresponding to the active region has a longitudinal direction in the channel length direction of the field effect transistor (in this case, FIG. 1).
(In the direction indicated by X), a plurality of grooves 37 having a rectangular cross-section having a length substantially the same as the channel width of the field-effect transistor and having a substantially rectangular cross section are provided along the channel length direction. (Three in the illustrated example) are provided side by side. The width W, depth D, and pitch P of the groove (refer to FIG. 1) and the number of grooves can be set to dimensions and numbers according to the design.
The intervals between the grooves 37 may not be equal depending on the design.

Further, a gate insulating film 39 as a second insulating film is provided on each of the inner walls of the plurality of grooves 37 and on the surface of the substrate portion 33 corresponding to the active region.

Further, a gate electrode 41 is provided on each of the inner walls of the plurality of grooves 37 and on a predetermined portion of the second insulating film 39. Further, the gate electrode 41 is provided on the substrate portion 33 corresponding to the active region. A diffusion layer 43 serving as a source / drain region is provided in a portion other than the portion where the plurality of grooves 37 are formed and the portion where the gate electrode 41 is formed.

An intermediate insulating film 45 is provided on the sample on which the gate electrode 41 and the diffusion layer 43 have been formed, and a contact hole 47 is provided in a predetermined portion of the intermediate insulating film 45 corresponding to the diffusion layer 43. , This contact hole 4
A wiring 49 (for example, an aluminum wiring) is connected to the diffusion layer 43 via the wiring 7.

1-2. Description of Manufacturing Method The FET of the first embodiment described with reference to FIG. 1 can be manufactured by, for example, a method described below.
2 (A) to 2 (C) and FIGS. 3 (A) to 3 (C) are manufacturing process diagrams for explanation thereof. Each drawing is a cross-sectional view at a position corresponding to FIG. 1 (the same applies to the following manufacturing process drawings).

First, a known LOCOS (Local oxidation of silicon) method is applied to the silicon substrate 31, for example.
Substrate portion 33 corresponding to active region of transistor
A first insulating film 35 having a window 35a for exposing is formed (FIG. 2A).

Next, a groove 3 of the substrate portion 33 is formed in the substrate portion 33 corresponding to the active area for forming the groove 37.
7 A resist pattern 5 for selectively exposing a region to be formed
1 (FIG. 2B).

Next, anisotropic etching is performed on the sample on which the resist pattern 51 has been formed by, for example, RIE (Reactive Ion Etching) to form a groove 37 (FIG. 2C).

Next, a second insulating film 39 is formed in each groove 37 and on the surface of the substrate portion 33 corresponding to the active region by, for example, a thermal oxidation method (FIG. 3A).

Next, a gate electrode material such as polysilicon is formed on the entire surface of the sample on which the second insulating film 39 has been formed, and then processed by a known photolithography technique and etching technique to form a plurality of grooves. A gate electrode 41 is formed on each of the inner walls 37 and on a predetermined portion of the second insulating film 39 (FIG. 3B).

Next, the gate electrode 41 and the first insulating film 3
5 is used as a mask during ion implantation to form source / drain diffusion layers 43 in a self-aligned manner (FIG. 3).
(C).

Thereafter, though not shown, by a known method,
The formation of the intermediate insulating film 45, the formation of the contact hole 47, and the formation of the wiring 49 are performed to obtain the FET of the first embodiment shown in FIG.

1-3. Description of Operation The FET of the first embodiment operates as described below. FIGS. 4A and 4B are diagrams for explanation thereof.

In the FET of the first embodiment, (a). When the potential of the gate electrode 41 is equal to or lower than the threshold value of the FET of the first embodiment, the leakage current is changed from one diffusion layer 43 which is a source region to another diffusion region which is a drain region as shown by 61 in FIG. It flows toward the layer 43 along the second insulating film 39 (gate insulating film) (along the substrate portion in contact with the groove 37). (B). When the gate potential is equal to or higher than the threshold value and is relatively low, the drain current flows along the substrate portion in contact with the trench 37, so that the effective gate length is longer than that of the conventional FET. (C). When the gate potential is equal to or higher than the threshold value and relatively high, the substrate portion between the grooves 37 (hereinafter, referred to as the substrate portion)
It may also be referred to as "a convex portion of the substrate". ) Is depleted, so that the drain current flows along the bottom of the groove 37 of the substrate 31 so as to pass through the convex portion of the substrate as indicated by 63 in FIG. 4B. For this reason, almost the same driving capability as that of the related art can be obtained.

1-4. Another Example of First Embodiment In the FET of the first embodiment described with reference to FIG.
Had a rectangular cross section. However, the cross-sectional shape of the groove is not limited to this, and may be any suitable shape according to the design of the FET. Here, a description will be given of an FET including a groove 37 having a mountain-shaped (in this case, triangular waveform) cross-sectional shape. FIGS. 5A and 6A are views for explaining the structure and operation of this FET.

The FET of the embodiment provided with the groove 37 having a mountain-shaped cross section also has the FE of the embodiment described with reference to FIG.
Similarly to the case of T, when the potential of the gate electrode 41 is equal to or less than the threshold value of the FET, the leak current flows through the portion along the groove 37 of the substrate 31 as shown by 65 in FIG.
When the potential of the gate electrode 41 is equal to or higher than the threshold of the FET and relatively low, the drain current flows along the path indicated by 65 in FIG. 5A. Since the protruding portion of the substrate is depleted, the drain current flows along the bottom portion of the groove 37 of the substrate 31 so as to pass through the protruding portion of the substrate as shown by 67 in FIG.

In the manufacture of this FET having the groove 37 having a mountain-shaped cross section, the manufacturing process of the FET shown in FIG. 1 having a groove having a rectangular cross section will be described with reference to FIG. By controlling the RIE gas pressure and the RF power in the above steps, the groove 37 having a mountain-shaped cross section can be formed. Steps other than the groove forming step may be the same as the steps of manufacturing the FET shown in FIG. 1 provided with a groove having a rectangular cross section.

2. Second Embodiment As a second embodiment, an example in which some of the plurality of grooves have different depths will be described. FIGS. 6A and 6B are explanatory diagrams of the structure and operation of the FET in the case where the depth of the central groove among the three grooves 37 is made larger than the depth of the other grooves as an example. FIGS. 7A and 7B show another example of the structure of the FET when the depth of the groove closest to the drain region among the three grooves 37 is greater than the depth of the other grooves. FIG.

In either case of FIG. 6 or FIG.
Similarly to the FET of the embodiment, the potential of the gate electrode 41 is FE
In the case where the leak current is equal to or less than the threshold value of T, the leak current flows through a path indicated by 65 in FIG. 6A or FIG. 7A, and when the potential of the gate electrode 41 is equal to or higher than the threshold value of the FET and relatively low. 6A or 7A, when the potential of the gate electrode 41 is higher than or equal to the threshold value of the FET and relatively high, the convex portion of the substrate is depleted. As shown by 67 in FIG. 6 (B) or FIG.
7 is formed along the bottom portion. Therefore, the formation position of the channel on the substrate changes depending on the magnitude of the gate potential, and the length of the current path can be changed. Further, in either case, the channel path can be made longer by increasing the depth of one groove as compared with the first embodiment. Therefore, in both cases where the gate potential is low and high,
It is considered that the short channel effect can be reduced as compared with the embodiment or the second embodiment. In particular, in the FET described with reference to FIG. 7, since the channel near the drain region is formed in a deep portion of the substrate,
Hot carry is less likely to be taken into the insulating film, and the driving capability is increased.

An example of the method of manufacturing the FET according to the second embodiment will be described with reference to the example of manufacturing the FET described with reference to FIG. 8 (A) to 8 (C) and FIGS. 9 (A) and 9 (B) are main part process drawings for explanation thereof.

First, a first insulating film 35 is formed on a silicon substrate 31 by the same LOCOS method as in the first embodiment (FIG. 8A).

Next, a silicon nitride film 71 is formed by a suitable film forming method on the entire surface of the silicon substrate 31 on which the first insulating film 35 has been formed, and then the silicon nitride film 71 is formed at the center of the three grooves. A resist pattern 73 exposing a region where a groove is to be formed is formed by a known photolithography technique (FIG. 8B).

Next, the sample on which the resist pattern 73 has been formed is anisotropically etched by, for example, RIE (reactive ion etching) to form a central groove 37a among the three grooves (FIG. 8 ( C)).

Next, a resist pattern 75 exposing regions of the silicon nitride film 71 where the right and left grooves of the three grooves are to be formed is formed by a known photolithography technique (FIG. 9A).

Next, the sample on which the resist pattern 75 has been formed is subjected to anisotropic etching by, for example, RIE (Reactive Ion Etching) to form grooves 37b and 37c at both ends of the three grooves (FIG. 9). 9 (B)). The etching time at this time is set shorter than the time when the central groove 37a is formed.

Thereafter, the formation of the second insulating film 39, the formation of the gate electrode 41, the formation of the diffusion layer 43, and the like are performed in the same manner as the method described with reference to FIGS. good.

It is needless to say that a shallow groove is formed first, and then a deep groove is formed.

Although the third embodiment shows an example in which one of the three grooves is deep, the way of changing the depth of the groove is not limited to this example, and any suitable one according to the design of the FET can be used. You can make it different.

3. Third Embodiment As a third embodiment, in the configuration of the first embodiment, the impurity concentration of the silicon substrate 31 is changed from the surface of the substrate 31 to the groove 3.
An example of an FET that is different up to the bottom of 7 will be described. FIGS. 10A and 10B show the FET of the third embodiment.
FIG. 4 is a diagram provided for describing the structure and operation of FIG.

[0054] In FET shown in FIG. 10 (A) and (B), the silicon substrate 31, the impurity concentration, the groove 37 in the depth direction central portion of the prospect to the groove bottom portion 31b from the substrate surface portion 31a It is set to be darker. However, it should be understood that the actual impurity concentration profile does not clearly have the boundary 81 (see FIG. 10) as shown.

When the FET of the third embodiment is considered to be an N-channel MOSFET operating on a surface channel type formed on a P-type silicon substrate (including a P-well), a portion where the substrate impurity concentration is high is compared with a portion where the substrate impurity concentration is low. In the FET of the third embodiment, the threshold voltage of the groove bottom side portion 31b of the substrate is higher than that of the substrate surface side portion 31a. For this reason, when the gate potential is equal to or lower than the threshold value at the groove bottom side portion 31b, the leak current is reduced as shown in FIG.
Since the current flows through the substrate along the groove as indicated by 65 in FIG. 3A, the current path is longer than that of the conventional FET, and the resistance of the path is increased by that amount, so that the leak current is smaller than before. Also,
If the gate potential is higher than or equal to the threshold value at the groove bottom side portion 31b and relatively low, the potential of the groove surface side portion 31a has already exceeded the threshold value before reaching this potential. Is formed. For this reason, the drain current flows here only by newly forming the inversion layer at the groove bottom side portion. Therefore, the switching time of the transistor is shortened. The current path in this case is shown in FIG.
This is a path along the groove as shown in FIG. Further, when the gate potential is equal to or higher than the threshold value at the groove bottom side portion 31b and relatively high, the substrate portion between the grooves (the convex portion of the substrate) is depleted, so that the drain current becomes 67 in FIG. As shown by the arrow, it flows along the bottom of the groove 37 of the substrate 31 in such a manner as to pass through the convex portion of the substrate. For this reason, almost the same driving capability as that of the related art can be obtained.

In the example shown in FIG. 10, the impurity concentration is changed substantially at the center in the depth direction of the groove. However, the position where the impurity concentration is changed is not limited to this position. it is obvious. In addition, the substrate surface side,
Even if the difference of each impurity concentration on the groove bottom side is reversed from the above embodiment, the magnitude relation of the threshold is opposite to that of the embodiment,
Similar effects can be obtained. It is preferable that the position where the impurity concentration is different be as close to the substrate surface as possible.

FIGS. 11A to 11C and FIGS. 12A to 12C show an example of the method of manufacturing the FET of the third embodiment.
Description will be made mainly with reference to (C). Here, an example in which an N-channel MOSFET is formed on a p-type silicon substrate will be described.

First, a first insulating film 35 is formed on a p-type silicon substrate 31 by the same LOCOS method as in the first embodiment (FIG. 11A).

Next, by using the first insulating film 35 as a mask, impurity ions (for example, boron B ⁺ or the like) 83 for controlling the threshold voltage of the FET are implanted into the active region 33 to form a deep first diffusion layer 31b. (FIG. 11)
(B)).

Next, impurity ions 83 are again implanted into the active region 33 under conditions weaker than the ion implantation conditions for forming the first diffusion layer 31b, thereby forming a shallow second diffusion layer 31a (FIG. 11C). )). Thereafter, the sample is heat-treated to activate the first diffusion layer 31b and the second diffusion layer 31a, respectively.

Next, the first and second diffusion layers 31a, 31b
A resist pattern 51 exposing a region where the groove is to be formed is formed on the formed active region 33 by a known photolithography technique (FIG. 12A).

Next, the groove 37 is formed on the sample on which the resist pattern 51 has been formed by performing anisotropic etching by, for example, RIE (reactive ion etching) (FIG. 12B).

Thereafter, the formation of the second insulating film 39, the formation of the gate electrode 41, the formation of the diffusion layer 43, and the like are performed in the same manner as the method described with reference to FIGS. good. Note that phosphorus (P) or arsenic (As) may be used as an impurity for forming the diffusion layer 41.

4. Fourth Embodiment As a fourth embodiment, in the configuration of the first embodiment, the groove 3
The thickness of the whole or a part of the second insulating film (gate insulating film 39) provided from the groove bottom to the substrate surface is different from the thickness of the second insulating film provided on the substrate surface. An example of the FET will be described. FIGS. 13A and 13B are views for explaining the structure and operation of the FET according to the fourth embodiment.

In the FET shown in FIGS. 13A and 13B, the thickness of the portion 39a in the groove 37 of the second insulating film 39 is made smaller than the thickness of the portion on the substrate surface. is there. The degree of this difference in film thickness may be determined according to the design of the FET.

Since the threshold voltage of an FET having a thin gate insulating film is lower than that of a FET having a thick gate insulating film, in the FET according to the fourth embodiment, the portion at the bottom of the groove of the substrate is more than the portion at the surface of the substrate. The threshold voltage decreases.

Therefore, in the FET of the fourth embodiment,
When the gate potential is equal to or lower than the threshold value on the substrate side portion, the leak current flows through the substrate portion along the groove as shown by 65 in FIG. Is increased, so that the leak current becomes smaller than before. If the gate potential is higher than or equal to the threshold value at the substrate surface side portion and relatively low, the potential at the groove bottom side portion is already higher than the threshold value, and the inversion layer is formed at this portion. For this reason, a drain current flows here only by newly forming an inversion layer on the substrate surface portion. When the gate potential is equal to or higher than the threshold value at the substrate surface side portion and is relatively high, the substrate portion between the trenches (the convex portion of the substrate) is depleted, and the drain current becomes 67 in FIG. As shown, the grooves 3 of the substrate 31 pass through the convex portions of the substrate.
7 flows along the bottom.

In the example shown in FIG. 13, the thickness of the second insulating film is different between the inside of the groove and the surface of the substrate. However, the thickness may be changed partway in the depth direction of the groove 37. . Groove 3
When the thickness of the portion 39a in 7 is larger than the thickness of the portion on the substrate surface, the same effects as described above can be obtained, although the magnitude relation of the threshold value is opposite to that of the embodiment.

FIGS. 2A to 2C and FIGS. 14A to 14C show an example of a method of manufacturing the FET of the fourth embodiment.
This will be mainly described.

First, as in the first embodiment, a first insulating film 35 is formed on a silicon substrate 31 by using the LOCOS method (FIG. 2A), and then a substrate portion 33 corresponding to an active region is formed. A resist pattern 51 for selectively exposing the region where the groove 37 is to be formed is formed (FIG. 2B), and thereafter, the groove 37 is formed by performing anisotropic etching by RIE (reactive ion etching). (Figure 2
(C)).

Next, a thin insulating film 39a of the second insulating film is formed in each groove 37 and on the surface of the substrate portion 33 corresponding to the active region by, for example, a thermal oxidation method (FIG. 14A). ).

Next, an oxidation-resistant material 91 such as a silicon nitride film is buried in the trench 37 (FIG. 14B). The burying of the oxidation-resistant material 91 into the groove 37 is performed, for example, by using the groove 3
7. A silicon nitride film is deposited on the entire surface of the formed sample in a thickness sufficient to fill the groove 37, a material such as a resist capable of flattening the surface is deposited on the silicon nitride film, and then the etching rate of the resist is increased. This can be performed by etching (etch back method) under etching conditions such that the etching rate of the silicon nitride film becomes equal to that of the silicon nitride film until the surface of the second insulating film on the surface of the substrate 31 is exposed.

Next, an insulating film is further formed on the second insulating film portion on the substrate surface by, for example, a thermal oxidation method. The second in the groove
Since the insulating film portion 39a is protected by the silicon nitride film 91, its thickness remains thin even in this thermal oxidation step, and an insulating film 39b having a larger thickness than that in the groove can be formed only on the substrate surface. (FIG. 14C).

Next, the silicon nitride film is selectively removed with a suitable etching solution such as hot phosphoric acid. After that, the formation of the gate electrode 41, the formation of the diffusion layer 43, and the like may be performed by a method similar to the method described with reference to FIGS.

[0075]

As is apparent from the above description, according to the first to third inventions, the driving capability is almost the same as that of the conventional FET, but the leakage current is small and the short channel effect (hot (Including deterioration of device characteristics due to carrier
An FET in which the occurrence of blemishes hardly occurs is obtained.

Further, in the case of the first invention in which the depth of the groove provided at the position closest to the drain region diffusion layer among the plurality of grooves is made deeper than the depth of the other grooves, in the case of the first invention, Channel is formed deep in the substrate,
The deterioration of device characteristics due to hot carriers can be further prevented, and the driving capability can be further increased.

Further, in the case of the second invention in which the impurity concentration of the semiconductor substrate is different from the surface of the substrate to the bottom of the groove, or the groove bottom of the second insulating film provided on the inner wall of the groove. In the case of the third aspect of the invention in which the thickness of the entire or a part of the substrate from the substrate to the surface of the substrate is different from the thickness of the second insulating film provided on the substrate surface, only the groove is provided (the configuration of FIG. 1). The switching speed can be improved as compared with the above, and the gate potential for switching the channel path can be controlled by changing the impurity concentration or the insulating film thickness.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing an FET according to a first embodiment.

FIGS. 2A to 2C are process diagrams showing an example of a method for manufacturing the FET of the first embodiment.

FIGS. 3A to 3C are process diagrams following FIG. 2 illustrating an example of a method for manufacturing the FET of the first embodiment.

FIGS. 4A and 4B are views for explaining the operation of the FET according to the first embodiment;

FIGS. 5A and 5B are diagrams for explaining another example of the FET of the first embodiment and the operation thereof.

FIGS. 6A and 6B are diagrams illustrating an example of an FET according to a second embodiment and an operation thereof;

FIGS. 7A and 7B are diagrams for explaining another example of the FET of the second embodiment and the operation thereof; FIGS.

FIGS. 8A to 8C are main part process diagrams showing an example of a method of manufacturing the FET of the second embodiment.

FIGS. 9A and 9B are main-portion process drawings following FIG. 8 illustrating an example of a method of manufacturing the FET of the second embodiment;

FIGS. 10A and 10B are diagrams for explaining the structure and operation of an FET according to a third embodiment;

FIGS. 11A to 11C are main part process charts showing an example of a method for manufacturing an FET according to a third embodiment;

FIGS. 12 (A) and (B) are main part process drawings showing an example of a method of manufacturing the FET of the third embodiment, following FIG. 11;

FIGS. 13A and 13B are diagrams for explaining the structure and operation of an FET according to a fourth embodiment;

FIGS. 14A to 14C are main-portion process diagrams illustrating an example of a method for manufacturing an FET according to a fourth embodiment;

FIG. 15 is a cross-sectional view for explaining a conventional field-effect transistor.

[Explanation of symbols]

31: Semiconductor substrate 31a: Substrate surface side portion (second diffusion layer with lower impurity concentration than 31b) 31a: Substrate bottom side portion (first diffusion layer with higher impurity concentration than 31a) 33: Active region 35: First insulating film (field oxide film) 35a: Window exposing the active region 37: Groove 37a: Groove at the center (groove whose depth is deeper than other grooves) 37b, 37c: Grooves at both ends 39: Second groove Insulating film (gate insulating film) 39a: Thin portion of second insulating film 39b: Thick portion of second insulating film 41: Gate electrode 43: Diffusion layer (for source / drain region) 45: Intermediate insulating film 49: Wiring 51: resist pattern 71: silicon nitride film 73: resist pattern 81: boundary 83: impurity ion 91: oxidation resistant material (for example, silicon nitride film)

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-50-6287 (JP, A) JP-A-54-99573 (JP, A) JP-A-2-162768 (JP, A) JP-A 51- 9687 (JP, A) JP-A-58-159344 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] A first insulating film having a window exposing a substrate portion corresponding to an active region of a transistor is provided on a semiconductor substrate, and a groove is formed in the substrate portion corresponding to the active region. A plurality of trenches are provided side by side along the channel length direction of the transistor; a second insulating film is provided on each of inner walls of the plurality of trenches and on a surface of a substrate portion corresponding to the active region; A gate electrode is provided on each of the inner walls and on a predetermined portion of the second insulating film, and a portion of the substrate corresponding to the active region other than a portion where the plurality of grooves are formed and a portion where the gate electrode is formed In a field-effect transistor provided with a diffusion layer serving as a source / drain region in a portion of the plurality of grooves, the depth of a groove closest to the drain region diffusion layer among the plurality of grooves is changed to another depth. Field effect transistor, characterized in that from the depth are deeply. 2. A semiconductor device, comprising: a first insulating film having a window exposing a substrate portion corresponding to an active region of a transistor; and a substrate portion corresponding to the active region having a longitudinal direction corresponding to the electric field. A plurality of grooves perpendicular to the channel length direction of the effect transistor are provided along the channel length direction of the field effect transistor, and a plurality of grooves are formed on the inner walls of the plurality of grooves and on the surface of the substrate portion corresponding to the active region. A gate electrode is provided on each of inner walls of the plurality of grooves and on a predetermined portion of the second insulating film, and the plurality of grooves are formed on a substrate portion corresponding to the active region. A field effect transistor provided with a diffusion layer serving as a source / drain region in a portion other than a portion where a gate electrode is formed and a portion where a semiconductor substrate is formed. The impurity concentration, field effect transistor, characterized in that are Chigae between from the substrate surface to the bottom of the groove. 3. A semiconductor device, comprising: a first insulating film having a window exposing a substrate portion corresponding to an active region of a transistor; A plurality of grooves perpendicular to the channel length direction of the effect transistor are provided along the channel length direction of the field effect transistor, and a plurality of grooves are formed on the inner walls of the plurality of grooves and on the surface of the substrate portion corresponding to the active region. A gate electrode is provided on each of inner walls of the plurality of grooves and on a predetermined portion of the second insulating film, and the plurality of grooves are formed on a substrate portion corresponding to the active region. In a field-effect transistor provided with a diffusion layer serving as a source / drain region in a portion other than the portion where the gate electrode is formed and the portion where the Field effect transistor, characterized in that digit the thickness of all or part of the groove bottom to the substrate surface of the second insulating film, are Chigae the thickness of the second insulating film provided on the substrate surface. 4. The field effect transistor according to claim 1, wherein a longitudinal direction of said groove is perpendicular to said channel length direction, and a length thereof is equal to a channel width of said field effect transistor. Field effect transistor.