JP3194162B2 - MOS FET manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS FET, and more particularly to a MOS FE having a low concentration drain (LDD) structure.
T manufacturing method.

[0002]

2. Description of the Related Art In a MOS FET having an LDD structure, generation of hot electrons due to a high electric field formed at an edge portion of a gate electrode is prevented, thereby reducing the life and reliability of the MOS FET. A conventional method for manufacturing a MOS FET having an LDD structure will be described with reference to FIG. As shown in FIG. 1A, after a field region 12 for electrical isolation between cells is formed on a P-type semiconductor substrate 11, it corresponds to each active region located between the next field region 12. Impurity ions for the electrical characteristics of the MOS FET are implanted into the surface of the P-type semiconductor substrate 11. Then, after a gate insulating film 13 is formed over the entire surface of the P-type semiconductor substrate 11 including the field region 12, a gate electrode 14 having a predetermined width is formed on the gate insulating film 13 in each active region. The exposed surface of the gate electrode 14 is oxidized to form a gate cap insulating film 15, and a semiconductor layer 16 for forming a gate sidewall over the entire surface is formed with a predetermined thickness.

[0003] Then, as shown in FIG.
6 is anisotropically etched by a reactive ion etching (RIE) method to form a gate sidewall semiconductor 17 on the side surface of the gate electrode 14. At this time, the gate cap insulating film 15 formed on the surface of the gate electrode 14 is used as an etching stopper. Using the gate cap insulating film 15 and the gate sidewall semiconductor 17 as a mask, N ⁺ type (here, + indicates high concentration) impurity ions are implanted into the surface of the P type semiconductor substrate 11 corresponding to the active region, and then diffused. N ⁺ type source / drain regions 18 and 18a are formed. Further, as shown in FIG.
7 is removed, and N ⁻ is deposited on the surface of the P-type semiconductor substrate 11 in the active region using the gate cap insulating film 15 as a mask.
N ^- type source / drain regions 19, 19
a is formed. Therefore, the source / drain regions
An LDD structure including a low concentration region and a high concentration region is formed.

[0004] A conventional MOS FE having an LDD structure.
The operation of T will be described below with reference to FIG.
Gate electrode 14, N ⁺ type drain region 18a and N ⁻
A gate bias voltage (V _G ) (approximately 3.3 V) and a drain voltage (V _D ) (approximately 3.3 V) are applied to the drain region 19 a, respectively, and a negative substrate voltage (V _S ) is applied to the P-type semiconductor substrate 11. ) Is applied, an inversion layer and a depletion region are formed as shown in the figure, and electrons generated from the N ⁻ type source region 19 collide with the lattice of the N ⁻ type drain region 19a, so that holes and electrons are generated. Generated. At this time,
The generated electrons are N ⁻ to which a positive voltage of about 3.3 V is applied.
Although holes are injected into the mold drain region 19a, holes move in three directions. That is, the holes are trapped by the gate electrode 14 and the gate insulating film 13 or moved to the P-type semiconductor substrate 11 as shown in FIG. The holes trapped by the gate electrode 14 affect the entire circuit, but do not significantly affect the operation of the MOS FET.
In addition, since the holes moved to the P-type semiconductor substrate 11 are reduced on the P-type semiconductor substrate 11, the operation of the MOS FET is not affected similarly.

[0005]

However, the holes trapped by the gate insulating film 13 are
Before the bias voltage (V _G ) of about 3.3 V set to is applied, the MOS FET is turned on. This ultimately degrades the MOS FET operating characteristics and lowers the reliability of the device. In addition, when holes are trapped in the gate insulating film 13, defects occur in the gate insulating film 13, so that the performance of the device is reduced or the life is shortened. The holes generated in this way are called hot carriers, and a problem caused by this is called a hot carrier effect.

Further, according to the prior art, there is a problem that the resistance is increased since the source / drain region is composed of the N ⁺ type region and the N ⁻ type region, and the thickness of the semiconductor on the gate side wall is accurately adjusted. Because it is difficult to adjust, a source / drain region having a predetermined width cannot be obtained. Therefore, a short channel effect occurred.

An object of the present invention is to provide a process for manufacturing a MOS FET in which the source / drain regions are formed as three regions having different concentrations from each other so that problems caused by generation of hot carriers and a short channel effect can be prevented. To offer.

[0008]

According to the present invention, a gate insulating film, a gate electrode, and a gate cap insulating film having the same width are formed on a semiconductor substrate of a first conductivity type. Forming; etching the insulating film and the semiconductor film to leave the insulating film and the semiconductor film on the side surface of the gate; removing the remaining portion to form a gate sidewall; and masking the gate sidewall and the gate cap insulating film. Forming a first concentration source / drain region by injecting a second conductivity type impurity into a semiconductor substrate; removing the semiconductor film in the gate sidewall and masking the remaining insulating film and gate cap insulating film Forming a second concentration source / drain region by injecting a second conductivity type impurity into the semiconductor substrate; removing the remaining insulating film; MOS FET manufacturing method comprising the step of injecting impurities of a second conductivity type forming a third source / drain region of a predetermined concentration is provided in the semiconductor substrate only Tokyappu insulating film as a mask.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for manufacturing a MOS FET according to the present invention will be described with reference to FIG. First, as shown in FIG. 1A, a gate insulating film 2, a gate electrode 3 and a gate cap insulating film 4 are sequentially formed on a P-type semiconductor substrate 1, and then, as shown in FIG. Unnecessary portions are removed using a process and a dry etching process. At this time, the material of the gate insulating film 2 is a silicon oxide film (SiO ₂ ), the material of the gate electrode 3 is polysilicon doped with impurities, and the material of the gate cap insulating film 4 is a silicon oxide film (SiO ₂ ). Is used. As shown in (C), an insulating film 5 and a semiconductor film 6 used as gate side walls are sequentially formed on the entire exposed surface by a chemical vapor deposition (CVD) method. As shown in FIG. 3D, a reactive ion etching (RIE) process is performed to anisotropically etch the insulating film 5 and the semiconductor film 6 and the insulating film 5a remaining on the side surfaces of the gate electrode 3 and the gate cap insulating film 4 is formed. And a semiconductor film 6a are formed to form a gate side wall 7. At this time, the etching stopper layer becomes the gate cap insulating film 4 and the gate insulating film 2. Using the gate cap insulating film 4 and the gate side wall 7 as a mask, high-concentration N ⁺ -type impurity ions are implanted into the surface of the P-type semiconductor substrate 1 and then diffused to form an N ⁺ -type source /
Drain regions 8, 8a are formed. Here, a silicon nitride film is used as the material of the insulating film 5, an undoped polysilicon is used as the material of the semiconductor film 6, and phosphorus (p) or arsenic (As) ions are used as the N ⁺ -type impurity ions. As shown in (E), only the remaining semiconductor film 6a located on the upper side of the gate side wall 7 is removed, and the remaining insulating film 5a and the gate cap insulating film 4 are used as a mask to form a relatively low concentration of N ^−. N ^- type source / drain regions 9 and 9a are formed by implanting impurity ions of N-type (N ⁺ > N ^- type) and then diffusing them. As shown in (F), the remaining insulating film 5a located on the lower side of the gate side wall 7 is removed,
N ⁻ type (N ⁺ > N ⁻ > N ⁻ ) impurity ions having a low concentration are implanted and then diffused to form N ⁻ type source / drain regions 10 and 10a. Here, phosphorus (p) or arsenic (As) ions, which are the same as the N ⁺ type impurity ions, are used as the N ⁻ type impurity ions and the N ⁻ type impurity ions.

The respective concentrations of the N ⁺ type impurity ions, the N ⁻ type impurity ions and the N ⁻ type impurity ions are appropriately adjusted according to the desired characteristics of the MOS FET. 3 sources /
In the drain region, the closer to the gate electrode 3, the lower the concentration, and the more a curved inclination curve is drawn. In this embodiment, an N-type MOS FET has been described as an example.
When the conductivity type of the substrate is changed and the conductivity type of impurity ions for forming source / drain regions is changed, a P-type MOS
It can also be applied to the manufacture of FETs. 2 to 7 show an N-type MOS FET according to the prior art and an N-type MOS of the present invention.
In the figure showing the data of the FET, the case of a 64K DRAM having a gate mask length of 0.5 μm is obtained as a model. With reference to these, the excellent effects of the present invention will be described.

FIG. 2A shows an MO manufactured according to the present invention.
FIG. 3 shows a cross section of an SFET (hereinafter, referred to as a new MOS FET), and shows an impurity doping profile along the line aa ′ in FIG. FIG.
(B) is a MOS FET manufactured by a conventional technique.
FIG. 8 shows a cross section of an MOS FET (hereinafter referred to as an old MOS FET), and shows an impurity doping profile along the line bb ′ in FIG. 2 (A) and 2 (B), cc 'indicates the length of the channel, and the length of the new MOS FET is closer to the set length of the gate mask than that of the old MOS FET. It can be understood that it has. That is, by the side diffusion process,
After the source / drain regions are formed, the length of the existing N-type channel region is 0.33 μm in the case of the new MOS FET.
m and 0.23 μm in the case of the old MOS FET. Therefore, the channel length in the case of the new MOS FET is 0.09 μm (about 2
0%).

FIG. 3A and FIG. 3B each show a new M
Drain induced barrier of OS FET and old MOS FET
a graph showing lowering (DIBL) values;
The DIBL value will be schematically described. The potential barrier existing between the source / drain regions is reduced by the drain voltage. As a result, leakage occurs between the source / drain regions while the gate voltage is lower than the threshold voltage.
The DIBL value indicates the degree of leakage as a voltage value. FIGS. 3A and 3B show the case where the drain voltage is 0.05 V and 3.3 V, respectively, and when the drain current ( _ID ) value is commonly 10 A / μm, It shows the difference. That is, the new MOS FET has a DIBL value of 64 mv,
The old MOS FET has a larger 126mv DI
It has a BL value. This DIBL value deters the operating characteristics of the MOSFET by increasing the turn-on of the MOS FET before the set gate bias voltage is completely applied. Therefore, the larger the DIBL value, the more M
The operating characteristics of the OS FET are degraded. In particular, the shorter the channel length, the greater the adverse effect. FIG. 4 (A)
And FIG. 4B show a new MOS FET and an old MO, respectively.
Estimated threshold voltage (V text) in S FET
FIG. 6 is a graph showing the relationship between the threshold voltage and the gate length. When the gate length is 2 μm or more, a threshold voltage value of about 0.913 V is held, but when the gate length is 2 μm or less, the threshold voltage value decreases in proportion to the gate length. You can see that. That is, after the length of the gate decreases, the threshold voltage also decreases due to the short channel effect. This phenomenon is exacerbated as the gate length decreases. However, the threshold voltage value must be constant regardless of the change in gate length.

According to FIGS. 6A and 6B, the threshold voltage (0.913 V) of an N-type MOS FET having a long channel region length (0.5 μm or more)
With the length of the channel region reduced to 0.5 μm, the new M
In OS FET, it becomes 0.636V, and old MOS F
It can be seen that the voltage is reduced to 0.533 V in ET. Therefore, it was confirmed that the new MOS FET has better threshold voltage characteristics than the old MOS FET.

FIGS. 5A and 5B each show a new MO.
In the SFET and the old MOS FET, the value of the current (that is, hole) flowing to the substrate is shown. As the drain voltage increases, electrons flowing from the source region to the drain region approach the drain region at a very high speed due to the strong electric field. At this time, electrons near the drain region collide with the lattice, and electrons and holes are generated in this region by impact ionization. Here, electrons flow into the drain region, but holes are trapped in the gate insulating film, flow into the gate electrode through the gate insulating film, or flow into the substrate. Of the three cases, this is the first case that causes degradation of the MOS FET characteristics.

However, since it is difficult to directly know the amount of holes trapped in the gate insulating film, the amount of current flowing to the substrate side is measured. That is, assuming that the amount of holes trapped in the gate insulating film is proportional to the amount of holes flowing to the substrate, the degree of degradation of the MOS FET due to hot carriers (holes) is measured by the amount of current flowing to the substrate.

MOS using such hot carriers
Methods for reducing the degradation of the FET can be roughly classified into three types. 1. Reduce the generation of ions due to impact ionization. 2. The generated holes are prevented from flowing to the gate insulating film. 3. It prevents holes flowing into the gate insulating film from being trapped in the gate insulating film.

The present invention reduces the generation of holes by reducing the intensity of the electric field near the drain region, and corresponds to the above-mentioned one item. FIG. 5 (A) and FIG.
According to (B), it can be seen that the current (Isub) flowing through the substrate is larger in the old MOS FET than in the new MOS FET. Old MOS FE
The maximum substrate current (Isub.max.) Of T is 4.93 × 10 ⁻⁶ A / μm when the gate voltage (V _G ) is 2.0 V, and the maximum substrate current (Isub.ma.
x. ) Is 9.13 × when the gate voltage (V _G ) is 1.8V.
10 ⁻⁷ A / μm. Therefore, the new MOS FET
Has a maximum substrate current value reduced by about 20% from the old MOS FET.

FIGS. 7A and 7B show a new MOS.
FIG. 4 is a profile diagram of a FET and an old MOS FET on a substrate surface. These potential profiles correspond to the case where the drain voltage (V _D ) is 0.5 V and 3.3 V, respectively, and are related to the DIBL value. That is, the larger the DIBL value is, the larger the descent width (d, d ') of the potential in the channel region becomes.
Before the OS FET is turned on, the magnitude of the leakage current increases. Therefore, before the voltage of the set gate bias is applied, the MOS FET is turned on and malfunctions. FIG. 7A and FIG.
According to (B), the new MOS FET is replaced by the old MOS FET
It can be seen that it has a lower potential drop width (d, d ').

[0019]

As described above, according to the present invention, the new MOSFET is replaced with the old MOSFET by the measurement in four cases.
It proved to be superior to FET.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a MOS FET according to the present invention.

FIG. 2 is a diagram showing doping profiles on the substrate surface of the MOS FET of the present invention and the conventional example.

FIG. 3 shows DI of a MOS FET according to the present invention and a conventional example.
It is a graph which shows a BL value.

FIG. 4 is a graph showing threshold voltages of MOS FETs according to the present invention and a conventional example.

FIG. 5 is a graph showing the amount of holes moving to a substrate during operation of a MOS FET according to the present invention and a conventional example.

FIG. 6 is a graph showing a relationship between a threshold voltage and a length of a gate electrode.

FIG. 7 is a profile diagram on a substrate surface of a MOS FET according to the present invention and a conventional example.

FIG. 8 shows a conventional MOS F having an LDD structure.
It is a manufacturing process sectional view of ET.

FIG. 9 is a diagram illustrating the operation of a conventional MOS FET having an LDD structure.

[Explanation of symbols]

1 P-type semiconductor substrate 2 gate insulating film 3 gate electrode 4 gate cap insulating film 5,5a insulating film 6,6a semiconductor film 7 gate side wall 8, 8a N ⁺ -type source / drain regions 9, 9a N ^- -type source / drain region 10, 10a N ^- type source / drain regions

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-197161 (JP, A) JP-A-62-188277 (JP, A) JP-A-63-124468 (JP, A) 259535 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] A step of forming a gate on a semiconductor substrate of a first conductivity type; a step of sequentially forming a thin insulating film and a semiconductor film on the entire exposed surface; and etching the insulating film and the semiconductor film. Leaving the insulating film and the semiconductor film only on the side surface of the gate and removing the remaining portion; using the remaining insulating film, semiconductor film, and gate on the side surface of the gate as a mask, the second conductivity type impurity is added to the semiconductor substrate. Forming a first source / drain region having a predetermined concentration by implanting a semiconductor film corresponding to an upper portion of the insulating film and the semiconductor film on the side surface of the gate, and masking the remaining insulating film and the gate. Implanting a second conductivity type impurity into the semiconductor substrate to form a second source / drain region having a predetermined concentration; and removing the thin insulating film remaining on the side surface of the gate. Was removed,
Forming a third source / drain region with a predetermined concentration by implanting a second conductivity type impurity into a semiconductor substrate using only the gate as a mask. 2. The impurity concentration of the first source / drain region, the second source / drain region, and the third source / drain region is: first source / drain region> second source / drain region> third source. 2. A MOS FET according to claim 1, wherein the order of the drain / drain regions is the same.
Production method.