JP2832976B2 - Adaptive coding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive encoding device that performs encoding adaptively to a dynamic range for each block including a plurality of pixels.

[Summary of the Invention]

According to the present invention, a circuit for performing encoding adapted to a dynamic range with respect to original data in a block having a predetermined number of pixels, encoded data and original data are supplied, and encoded data and a newly set quantization step Or a circuit for setting a quantization step or a dynamic range and a minimum value such that an error between a decoded value calculated from the dynamic range and the minimum value and the original data has a minimum sum of squares for all pixels in the block. And a circuit that encodes the original data in accordance with the dynamic range based on the set quantization step or dynamic range and the minimum value, so that encoding with less distortion can be performed.

[Conventional technology]

The applicant of the present application obtains a dynamic range, which is a difference between a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and determines this dynamic range. An adaptive coding apparatus that performs adaptive coding has been proposed. Also, Japanese Patent Application No. 60-232789
As described in the specification, there has been proposed an adaptive coding apparatus that performs coding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in a region included in each of a plurality of frames. Further, as described in Japanese Patent Application No. 60-268817, a variable length encoding method in which the number of bits changes according to the dynamic range so that the maximum distortion generated when performing quantization is constant. Has been proposed.

Coding (referred to as ADRC) adapted to the above-described dynamic range can be significantly reduced in the amount of data to be transmitted, and is therefore preferably applied to a digital VTR. In particular, the variable length ADRC can increase the compression ratio.

[Problems to be solved by the invention]

In the previously proposed ADRC, only the maximum value and the minimum value contribute to the quantization characteristic, and the levels of the other pixels do not contribute to the quantization characteristic. On the other hand, what determines the quality of the image quality is the amount of distortion of all pixels. Therefore, when the quantum characteristic is determined only by the maximum value and the minimum value, the amount of distortion (that is, the error between the original data and the restored data) becomes large, and the S / N of the restored image is poor.

Therefore, an object of the present invention is to provide an adaptive encoding device that can reduce the distortion amount of all pixels.

[Means for solving the problem]

According to the present invention, a circuit 7 for performing coding adapted to a dynamic range with respect to original data in a block having a predetermined number of pixels, coded data Q and original data x are supplied, and coded data Q and newly set data are supplied. The quantization step Δ ′ or the quantization step Δ ′, or the decoded value calculated from the dynamic range and the minimum value MIN ′, and the square sum of the error of the original data x are minimized for all the pixels in the block. A circuit 9 for setting a dynamic range and a minimum value MIN '; and a circuit 16 for encoding the original data x according to the dynamic range based on the set quantization step Δ' or the dynamic range and the minimum value MIN '. Is provided.

[Action]

Encoded data Q is obtained by encoding according to the dynamic range DR. The encoded data Q and the quantization step Δ
And a minimum value MIN, a restoration value obtained by decoding is obtained. A quantization step Δ ′ and a minimum value MIN ′ that minimize the error between the original data and the restored value are obtained. The original data x is encoded based on the newly set Δ ′ and MIN ′. Therefore, the sum of the distortion amounts can be reduced for all the pixels in the block, and the S / N of the restored image can be improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows one embodiment of the present invention, in which digital video data in which one sample is digitized to 8 bits is supplied to an input terminal indicated by 1. The video data is converted by the blocking circuit 2 from a scan line order to a block order. The block has a size of (4 lines × 4 pixels) as shown in FIG.
One block includes 16 pixel data items x1 to x16.

The output signal of the blocking circuit 2 is supplied to the maximum and minimum value detection circuit 3 and the delay circuit 4. The detection circuit 3 detects the maximum value MAX and the minimum value MIN of the block. The delay circuit 4 delays data for a time for detecting the maximum value MAX and the minimum value MIN. The calculation of (MAX−MIN) is performed in the subtraction circuit 5, and the dynamic range DR is obtained from the subtraction circuit 5.
The subtraction circuit 6 subtracts the minimum value MIN from the video data from the delay circuit 4 to obtain video data from which the minimum value has been removed from the subtraction circuit 6.

Output data of the subtraction circuit 6 is supplied to the quantization circuit 7. The quantization circuit 7 is also supplied with the quantization step Δ formed by the division circuit 8. The dividing circuit 8 forms the quantization step Δ by dividing the dynamic range DR into three equal parts. If the number of bits is smaller than the original number of bits (8 bits) from the quantization circuit 7, a 2-bit quantization code Q can be obtained. In the quantization circuit 7, the video data from which the minimum value MIN has been removed is divided by the quantization step Δ, and a value obtained by converting the quotient to an integer is used as the quantization code Q. The quantization circuit 7 can be constituted by a division circuit or a ROM.

FIG. 3 shows an example of the quantization characteristic. In FIG. 3, reference numerals 10, 11, 12, and 13 indicate the representative levels to be restored, respectively. In this example, the representative levels 10 and 13 of levels corresponding to the minimum value MIN and the maximum value MAX respectively exist. Done. Such quantization is called edge matching. FIG. 4 shows a case where 16 pixel data included in a certain block are converted into a 2-bit quantization code Q. Open circles indicate original data respectively corresponding to the quantization codes Q. For example, four original data having a level equal to or larger than the minimum value MIN and smaller than (MIN + 1 / 2Δ) are encoded into a quantization code of (00). The quantization code Q is restored to the representative levels I0 to I3 indicated by x, and therefore, the quantization characteristics of the quantization circuit 7 are indicated by broken lines. As can be seen from FIG. 4, the quantization code Q has a minimum value MIN and a maximum value M
Although the error regarding AX is 0, the error regarding other pixels cannot be said to be sufficiently small.

9 is the minimum value MI that can reduce the sum of errors of all pixels.
3 shows a correction circuit for forming N ′ and Δ ′. The original data and the quantization code Q are supplied to the input terminals 10 and 11 of the correction circuit 9, and the minimum value MIN ′ and the quantization step Δ are output from the output terminals 12 and 13, respectively. The quantization is performed by the minimum value MIN 'set by the correction circuit 9 and the quantization step Δ'.

Original data and minimum value passed through the delay circuit 14 to the subtraction circuit 15
MIN 'is supplied, and data from which the set minimum value MIN' has been removed is generated from the subtraction circuit 15. The output of the subtraction circuit 15 and the set quantization step Δ ′ are supplied to a quantization circuit 16 that performs the same quantization as the quantization circuit 7, and the quantization circuit 16
Generates a quantization code DT. The quantization step Δ ′, the minimum value MIN ′ and the quantization code DT are supplied to the framing circuit 17, and the transmission data is taken out from the output terminal 18. The framing circuit 17 includes a quantization step Δ ′,
The minimum value MIN 'and the quantization code DT are arranged byte-serial, and form transmission data to which a synchronization signal is added.
The framing circuit 17 encodes the transmission data with an error correction code.

An example of the correction circuit 9 is shown in FIG. The correction circuit 9 is a circuit for calculating a minimum value MIN ′ and a quantization step Δ ′ that can perform quantization suitable for all pixels by the least square method. The restoration value y obtained from the quantization code Q generated by the quantization circuit 7 is represented by the following equation.

Assuming that the error that each restored value y has with respect to the original data x is e, The quantization step Δ ′ and the minimum value MIN ′ that minimize the sum of squares of these errors can be obtained by the following equations and equations.

= Average value of original data x1 to x16 = Average value of quantization codes Q1 to Q16 ² = Average value of squares of quantization codes Q1 to Q16 () ² = Square value of average values of quantization codes Q13 to Q16 Correction circuit 9 Is a circuit for calculating the minimum value MIN ′ and the quantization step Δ ′ according to the above equation. Input terminals 10 and 11
, The original data x and the quantization code Q are supplied in synchronization. The multiplication circuit 21 calculates (Q × x), and the multiplication circuit 22 calculates
Q ² is calculated. The sum of 16 pixel data in one block is calculated by the accumulation circuit 23, and the output of the accumulation circuit 23 is constituted by a shift register capable of shifting 4 bits.
The divided signal is supplied to a division circuit 28, which is set to 16, and is obtained from the division circuit 28.

The output signal of the multiplying circuit 21 is supplied to the accumulating circuit 24, and the output signal of the accumulating circuit 24 is made 1/16 by the dividing circuit 29.
From 29 Is obtained. The quantization code Q is supplied to the accumulation circuit 25,
The output signal of the accumulating circuit 25 is made 1/16 by the dividing circuit 30 and is obtained from the dividing circuit 30. The output signal of the multiplication circuit 22 is supplied to the accumulation circuit 26, and the output signal of the accumulation circuit 26 is divided by the division circuit 31.
To 1/16, and ² is obtained from the division circuit 31. To the accumulation circuits 23, 24, 25, and 26, a clock signal of a block cycle is supplied from a terminal 27, and the accumulation result is obtained for each block.

The output signal of the division circuit 28 and the output and signal of the division circuit 30 are supplied to the multiplication circuit 32, and x is obtained from the multiplication circuit 32. The output signal of the multiplication circuit 32 and the output signal of the division circuit 29 are supplied to the subtraction circuit 33, and the expression and the term of the numerator of the fraction in the expression are obtained from the subtraction circuit 33.

The multiplying circuit 34 supplied with the output signal of the dividing circuit 30 obtains ( ² ). The output signal of the multiplication circuit 34 and the output signal of the division circuit 31 are supplied to the subtraction circuit 35, and the expression and the term of the denominator of the fraction in the expression are obtained from the subtraction circuit 35.

The output signals of the subtraction circuits 33 and 35 are supplied to a division circuit 36, from which a quantization step Δ 'is obtained. The newly set quantization step Δ ′ is output to the output terminal 13.

The quantization step Δ 'from the dividing circuit 36 and the signal from the dividing circuit 30 are supplied to a multiplying circuit 37. In the subtraction circuit 38, the output signal of the multiplication circuit 37 is subtracted from the division circuit 28, and the minimum value MIN 'is obtained from the subtraction circuit 38. The newly set minimum value MIN 'is taken out to the output terminal 12.

As described above, the minimum value newly set by the correction circuit 9
The original data x passed through the delay circuit 14 is ADRC encoded by MIN 'and the quantization step Δ'.

Although the quantization step is set in the embodiment of the present invention, a dynamic range may be set.

〔The invention's effect〕

According to the present invention, the sum of the errors for all the pixels in each block is determined to be the minimum value and the quantization step (or dynamic range), and the original data is quantized with these data, so that the S / N of the restored image can be improved. . In the example of FIG. 3, Δ represents a representative level when encoded with MIN ′ and Δ ′. As is apparent from FIG. 3, these representative levels can reduce the sum of errors from the original data as compared with the quantization characteristics indicated by the broken lines.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a schematic diagram showing an example of a block, FIG. 3 is a schematic diagram used for describing quantization characteristics, and FIG. 4 is an example of a correction circuit. It is a block diagram of. Explanation of main symbols in the drawing 1: input terminal, 3: maximum value / minimum value detection circuit, 7, 16: quantization circuit, 9: correction circuit, 18: output terminal.

Claims (1)

(57) [Claims] 1. A circuit for performing encoding adapted to a dynamic range with respect to original data in a block having a predetermined number of pixels, the encoded data and the original data being supplied, and newly set with the encoded data. Quantization step or dynamic range and minimum value such that the sum of squares of the error between the decoded value calculated from the quantization step or dynamic range and the minimum value and the original data is minimized for all pixels in the block. And a circuit for adaptively encoding the original data according to the dynamic range based on the set quantization step or the dynamic range and the minimum value. apparatus.