JPH0353778A - High efficiency coding device - Google Patents

Abstract

PURPOSE:To prevent generation of block distortion due to ringing or impulse noise or the like by detecting a mean value of picture element data included respectively in a maximum level range and a minimum level range, using the mean value as maximum and minimum values newly to apply quantization for edge matching. CONSTITUTION:Output signals of AND gates 10, 11 are fed respectively to averaging circuits 12, 13. A mean value MAX' of a picture element data belonging to a maximum level range of (MAX-MAX-DELTA) is obtained from the averaging circuit 12 and a mean value MIN' of a picture element data belonging to a minimum level range of (MIN-MIN-DELTA) is obtained from the averaging circuit 13. A mean value MIN' is subtracted from the mean value MAX' at a subtraction circuit 15 and a dynamic range DR' is obtained therefrom. Then data PD 1 after the elimination of the minimum value and a corrected DR' are fed to a quantizing circuit 18 to apply edge matching quantization. Thus, a difference between a decoding level and that of an adjacent block is less and generation of block distortion is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-efficiency encoding device for compressing the number of bits per pixel of image data such as digital television signals.

[Summary of the invention]

The present invention includes a circuit for determining the maximum value and minimum value of a plurality of pixel data included in a block consisting of N areas belonging to each of a two-dimensional block of digital image signals or N temporally continuous frames; A circuit for extracting pixels existing in a predetermined level range from each of the values and a minimum value, and a first average value of input image data included in the predetermined level range from the maximum value and an input included in the predetermined level range from the minimum value. a circuit for forming a second average value of the image data;
A circuit that calculates the dynamic range from the difference between the first average value and the second average value, and a circuit that calculates the amount of information generated in a predetermined period based on the dynamic range so that the amount of generated information falls within the predetermined amount of data. A circuit that controls a threshold value for setting the number of bits allocated to each block and sets the number of bits allocated to each block based on a comparison output between the threshold value and the dynamic range of each block, and a circuit that controls a threshold value for setting the number of bits allocated to each block, and It consists of a subtraction circuit that subtracts the average value of , and a circuit that quantizes the output of the subtraction circuit by edge matching according to the assigned number of bits, and can prevent the occurrence of block distortion due to ringing and impulse noise.
The amount of information generated by variable length ADRC can be correctly controlled.

[Conventional technology]

As video signal encoding methods, several high efficiency encoding methods are known in which the average number of bits per pixel or sampling frequency is reduced in order to narrow the transmission band.

The applicant of this application has determined a dynamic range defined by the maximum and minimum values of a plurality of pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and We have proposed a high-efficiency encoding device that performs adaptive encoding. Furthermore, as described in Japanese Patent Application No. 60-232789, a high-efficiency encoding device performs encoding adapted to a dynamic range with respect to a three-dimensional block formed from pixels in areas included in each of a plurality of frames. is proposed. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits is changed according to the dynamic range such that the maximum distortion caused when quantization is constant. is proposed.

FIG. 7 is used to explain the previously proposed encoding method (referred to as ADRC) adapted to the dynamic range. For example, the dynamic range DR (difference between maximum value MAX and minimum value MIN) is (8 lines x 8 pixels = 64
It is calculated for each two-dimensional block consisting of pixels). Also, the lowest level (minimum value) within the block is removed from the input pixel data. The pixel data after this minimum value has been removed is converted to a representative level. In this quantization, the detected main dynamo range DR is divided into four level ranges AO to A3 corresponding to a bit number smaller than the original quantization bit number, for example, 2 bits, and each pixel data in the block is divided into four level ranges AO to A3. This is a process of detecting the level range to which it belongs and generating a code signal indicating this level range.

In FIG. 7, the dynamic range DR of the block is divided into four level ranges AO to A3. Pixel data included in the minimum level range AO is encoded as (00), pixel data included in level range A1 is encoded as (01), and pixel data included in level range A2 is encoded as (00).
10), and pixel data included in the maximum level range A3 is encoded as (l1). Therefore, the 8-bit data of each pixel is compressed to 2 bits and transmitted. On the receiving side, the received code signal has a representative level of 7L/L.
Restored to O~L3. These representative levels LO to L3 are
This is the center level of each of the level ranges AO to A3.

The above-mentioned encoding method adapted to the dynamic range has a problem in that block distortion occurs due to ringing and impulsive noise. FIG. 8 is a diagram for explaining the occurrence of block distortion. In Figure 8, for ease of explanation,
Changes in data for a one-dimensional block, that is, a block shaped by a predetermined number of samples in the horizontal direction, are represented as analog waveforms, and the restored values on the receiving side are shown by broken lines.

As shown in FIG. 8, small-level ringing often occurs in the image output of a video camera near edges where the level changes sharply. In a block including this ringing, the peak value of the ringing is detected as the maximum value MAXI, and encoding is performed in accordance with the dynamic range DRl determined by the minimum value MINI. In the next block, since the ringing is concentrated, the maximum value decreases as shown by MAX2, and encoding is performed in accordance with the dynamic range DR2 determined by the minimum value MIN2 and the maximum value MAX2. Therefore, a difference in brightness level occurs between these two blocks, causing block distortion. Block distortion also occurs in the case of impulsive noise for the same reason. Although the difference in luminance level of the block distortion described above is small, it has a certain area, so there is a visually noticeable problem.

In order to solve the problem of the occurrence of block distortion due to ringing and impulsive noise described above, the applicant of the present application has developed an input method that is converted into a block structure as described in Japanese Patent Application No. 61-202118. We propose a method for preprocessing data. In other words, the average value MAX'' of the input data values included in the maximum level range (A3 in Figure 7) when the dynamic range is equally divided by the number of ADRC quantization bits, and the minimum level range (A3 in Figure 7). AO) is detected, and as shown in FIG. 9, these average values MAX' are detected.
and average value MIN'' are respectively restored levels L3 and LO.As shown in FIG. 7, the representative levels LO to L3 do not include the maximum value MAX and the minimum value MIN, and each level Quantization that takes the median value of the range is called non-edge matching, and as shown in Figure 9, the average value M
Quantization including AX' and MIN'' is called edge matching. ADRC, which preprocesses with the above-mentioned non-edge matching and quantizes with edge matching, is performed on blocks that include ringing in Figure 8. However, the maximum value is not the ringing peak, but is changed to the average value MAX', and the minimum value is similarly changed to MIN'.The modified dynamic range DR determined by MAX' and MIN'
Since edge matching is quantized within ', the difference between the restoration level and the restoration level of adjacent blocks is reduced,
Block distortion is prevented from occurring. The above-mentioned ADRC encoding adapted to the dynamic range can greatly compress the amount of data to be transmitted, and is suitable for use with digital VTRs.

In particular, variable length ADRC can increase the compression rate. However, with variable length ADRC, the amount of data to be transmitted varies depending on the image content, so when using a fixed rate transmission line such as a digital VTR that records a predetermined amount of data as one track, buffering processing is required. Needed. As a buffering method for variable-length ADRC, the applicant of the present application forms a cumulative dynamic range frequency distribution, as described in Japanese Patent Application No. 61-257586, and Then, a pre-prepared threshold value for determining the number of allocated bits is applied, the amount of data generated during a predetermined period, for example, one frame period, is determined, and the amount of data generated does not exceed the target value.
We are proposing something to control. [Problem to be solved by the invention] As mentioned above, ADRC performs preprocessing using non-edge matching quantization, and then performs quantization using edge matching.
However, when variable length ADRC is applied, even if the number of allocated bits is set based on the original dynamic range DR, the dynamic range DR' is transmitted to the receiving side, so there is a difference between the two. This caused a problem.
That is, in order to control the amount of generated information, a frequency distribution table for a predetermined period of the dynamic range DR, for example, one frame period, is formed, and this frequency distribution table is converted into a cumulative frequency distribution table. T1, T2, T3, T4 (
A threshold of TI<72<T3<74) is applied. (
When DR<Tl), the number of allocated bits n is set to O (that is, no quantization code is transmitted), and (Tl≦DR
<T2), it is set to (n-1), and (T2≦DR
<73), (n=2), and (T3≦DR
<74), (n=3), and (T4≦DR
), (n=4). As aforementioned,(
MAX'-MIN'-DR'), and quantization is performed based on this corrected dynamic range DR',
The dynamic range DR' is transmitted. Regarding the dynamic range of a certain block, (T2≦DR<T3)
If the relationship (T2≦DR'<T3) holds,
On the encoder side, it is set as (n=2), and on the decoder side, it is also set as (n-2), so no problem occurs. However, (DR>
DR''), when (Tl≦DR'<T2), the decoder side incorrectly judges that ., (n=1), causing a problem that the correct decoding operation is not performed. The purpose is to create a high-efficiency encoding device that matches the dynamic range used for quantization and transmission with the dynamic range used for buffering processing, and prevents mismatch between the encoder and decoder sides. [Means for Solving the Problems] This invention provides a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames. a maximum value/minimum value detection circuit 3 for determining the maximum value MAX and minimum value MIN of a plurality of pixel data; circuits 5, 6 for extracting pixels existing within a predetermined level range from each of the maximum value MAX and minimum value MIN;
7, 8, 9, lO, 11, the first average value MAX' of input image data included in a predetermined level range from the maximum value MAX, and the second average value MAX' of input image data included in a predetermined level range from the minimum value MEN. Average value M
circuits 12 and 13 that form a dynamic range DR′, a circuit 15 that calculates a dynamic range DR′ from the difference between the first average value MAX′ and the second average value MINO, and The amount of generated information is calculated, and thresholds Tl to T4 for setting the number n of allocated bits for each block are controlled so that the amount of generated information is within a predetermined amount of data.
- circuits 19, 20, 21 that set the number of allocated bits n for each block based on the comparison output between T4 and the dynamic range DR of each block, and a circuit 16 that subtracts a second average value MIN'' from the input image signal. and a circuit 18 that allocates the output of the subtraction circuit 16 and quantizes it by edge matching using the number of bits n. [Operation] Since the television signal has three-dimensional correlation in the horizontal direction, vertical direction, and time direction, in the stationary portion, the width of change in the level of pixel data included in the same block is small. Therefore, even if the data after removing the minimum level shared by pixel data in a block is quantized with a smaller number of quantization bits than the original number of quantization bits, almost no quantization distortion occurs. In addition, the average values MAX'' and MIN of pixel data respectively included in the maximum level range defined by the maximum value MAX and the value lower by a predetermined level from MAX, and the minimum level range defined by the value higher by a predetermined level from iMIN and MIN, respectively. ” and performs edge matching quantization using this average value as new maximum and minimum values, ringing,
Block distortion may occur due to impulse noise etc.
Iji is stopped.

The calculation of the amount of generated information and the setting of thresholds T1 to T4 for keeping the amount of generated information below a predetermined amount are done based on the dynamic range DR' used for edge matching processing, so the encoder side and This prevents inconsistencies between the decoder and the decoder. [Examples] Examples of the present invention will be described below with reference to the drawings. explain.

be done.

a. Sending side configuration b. Receiving side structure C. Buffering circuit d. Variations This description follows the following order: a. Structure of the Transmitting Side FIG. 1 shows the overall structure of the transmitting side (recording side) of the present invention. For example, a digital video signal in which one sample is quantized to 8 bits is input to the input terminal indicated by l (
A digital luminance signal) is input. This digital video signal is supplied to the blocking circuit 2. The blocking circuit 2 converts the input digital video signal into continuous signals in units of two-dimensional blocks, which are units of encoding. In this embodiment, one block has a size of (8 lines x 8 pixels=64 pixels) as shown in FIG. The output signal of the blocking circuit 2 is supplied to a maximum value/minimum value detection circuit 3 and a delay circuit 4. Maximum value,
The minimum value detection circuit 3 detects the minimum value M I N,
Detect the maximum value MAX. The delay circuit 4 delays the input data by the time required for the maximum and minimum values to be detected. Pixel data from the delay circuit 4 is supplied to a comparison circuit 5 and a comparison circuit 6. The maximum value MAX from the maximum value/minimum value detection circuit 3 is supplied to the subtraction circuit 7, and the minimum value MIN
is supplied to the adder circuit 8. These subtraction circuits 7 and addition circuits 8 are supplied with a value of one quantization step width (Δ-1/16DR) when non-edge matching quantization is performed with a fixed length of 4 bits from a bit shift circuit 9. The bit shift circuit 9 performs division by (1/16).
The plan is to shift the dynamic range DR by 4 bits. The m calculation circuit 7 obtains a threshold value of (MAX-Δ), and the addition circuit 8 obtains a threshold value of (MIN+Δ). The threshold values from these subtraction circuit 7 and addition circuit 8 are supplied to comparison circuits 5 and 6, respectively.

Note that the value Δ that defines this threshold value is not limited to the quantization step width, but may be a fixed value corresponding to the noise level. The output signal of the comparator circuit 5 is supplied to the AND gate lO,
The output signal of the comparison circuit 6 is supplied to an AND gate 11, and the input data from the delay circuit 4 is supplied to AND gates 10 and 11. The output signal of the comparator circuit 5 becomes high level when the input data is larger than the threshold value.
The pixel data of the input data included in the maximum level range of AX-Δ) is extracted. The output signal of the comparison circuit 6 becomes high level when the input data is smaller than the threshold value, and therefore, the output terminal of the AND gate 11 has (MIN-M
The pixel data of the input data included in the minimum level range of IN+Δ) is extracted. The output signal of AND gate 10 is supplied to averaging circuit l2, and the output signal of AND gate 11 is supplied to averaging circuit 13. These averaging circuits 12 and 13 calculate an average value for each block, and a block cycle reset signal is supplied from a terminal 14 to the averaging circuits 12 and 13. The averaging circuit 12 obtains the average value MAχ' of the pixel data belonging to the maximum level range of (MAX - MAX - Δ), and the averaging circuit 13
, the average value MIN' of the pixel data belonging to the minimum level range of CM I N MIN + Δ> can be obtained. The average value MIN' is subtracted from the average value MAX' by the subtraction circuit l5, and the dynamic range DR' is obtained from the subtraction circuit 15. The average value MIN' is also supplied to the subtraction circuit 16 and passed through the delay circuit l7. The average value MIN' is subtracted from the input data in the subtraction circuit 16, and the data P after the minimum value is removed is
DI takes shape. This data PDI and the corrected dynamometer range DR' are supplied to the quantization circuit l8. In this example, the number of bits allocated for quantization n
is 0 bit (does not transmit code signal), 1 bit, 2
It is a variable length ADRC that can be either bit, 3 bits, or 4 bits, and edge matching quantization is performed. The number of allocated bits n is determined in the bit number determining circuit 19 for each block, and in variable length ADRC in which data of the number of bits n is supplied to the quantization circuit 18, in a block with a small dynamic range DR', the number of allocated bits n For blocks with a large dynamic range DR', efficient encoding can be performed by increasing the number of allocated bits n. That is, the threshold value for determining the number of bits n is Tl~T4 (TI<72<73<
74), the code signal is not transmitted in the block of (DR' T1) and only the information of the dynamic range DR' is transmitted, and the block t27 of (Tl≦DR'<T2) is (n- 1), the block with (T2≦DR'<T3) is set as (n=2), the block with (73≦DR'<74) is set as (n-3), and the block with (DR'≧T4) ) is assumed to be (n-4). Such variable length ADR
In C, the amount of generated information can be controlled (so-called buffering) by changing the threshold values T1 to T4. Therefore, variable length ADRC can also be applied to transmission lines such as digital VTRs that require the amount of information generated per field or frame to be a predetermined value. In FIG. 1, 20 indicates a buffering circuit that determines threshold values T1 to T4 for setting the amount of generated information to a predetermined value. In the batsuring circuit 20, as described later,
A plurality of sets of threshold values (Tl, T2, T3, T4), for example, 32 sets, are prepared, and these sets of threshold values are determined by parameter code Pi (i=0.1, 2, . . . 31). distinguished. As the number i of the parameter code Pi increases, the amount of generated information decreases monotonically.
It is set. However, as the amount of generated information decreases, the quality of the restored image deteriorates.

The threshold values T1 to T4 from the buffering circuit 20 are supplied to the comparator circuit 21, and the dynamic range DR' via the delay circuit 22 is supplied to the comparator circuit 21. The delay circuit 22 delays DR' by the time required for the buffering circuit 20 to determine the set of threshold values. In the comparison circuit 21, the dynamic range DR' of the block is compared with each threshold value, and the comparison output is supplied to the bit number determining circuit 19, which determines the number n of allocated bits for the block. The quantization circuit l8 uses the dynamic range DR' and the allocated bit number n to determine the delay circuit 2.
The minimum value removed data PDI that has been passed through 3 is converted into a code signal DT by edge matching quantization. The quantization circuit l8 is comprised of, for example, a ROM.

The dynamic range DR' and the average value MIN' modified through the delay circuits 22 and 24 are sent to the frame forming circuit 2.
5, and a parameter code Pi indicating a set of a code signal DT and a threshold value is also supplied to a framing circuit 25. Transmission data converted into serial data is taken out to an output terminal 26 of the framing circuit 25.
In the framing circuit 25, an error correction code is encoded as necessary, and a synchronization signal is added.

b. Receiving side posture FIG. 3 shows the configuration on the receiving (or reproducing) side.

The received data from the input terminal 3l is sent to the frame decomposition circuit 3.
2. The frame decomposition circuit 32 separates the code signal DT and the additional codes DR", MIN', Pi, and performs error correction processing. The code signal DT is supplied to the decoding circuit 33, and the parameter code Pi and the dynamic The range DR' is supplied to the decoding circuit 33. The average value MEN' is also supplied to the adding circuit 34.
The output signal of the adder circuit 34 is supplied to the block decomposition circuit 35. The decoding circuit 33 performs processing opposite to that of the quantization circuit 18 on the transmitting side. That is,
The code signal DT is decoded to a representative level, this data and the 8-bit average value MIN' are added by the adder circuit 34, and the original pixel data is decoded.

The decoding circuit 33 performs decoding using the number n of allocated bits of the block indicated by the parameter code Pi. The output signal of the adder circuit 34 is supplied to a block decomposition circuit 35. The block decomposition circuit 35 is a circuit for converting the restored data in the order of the blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmitting side. A decoded video signal is obtained at the output terminal 36 of the block decomposition circuit 35. C. Buffering Circuit FIG. 4 shows an example of the buffering circuit 20. The buffering circuit 20 is provided with a memory (RAM) indicated by 4l for storing the frequency distribution table and the cumulative frequency distribution table, and an address is supplied to this memory 4l via a multiplexer 42. The dynamic range D is input from the input terminal 43 as one input of the multiplexer 42.
R'' is supplied, and the address from the address generation circuit 50 is supplied as the other input.
The output signal of the adder circuit 44 is input, and the output data of the memory 41 and the output of the multiplexer 45 are added together by the adder circuit 44 .

The output of the adder circuit 44 is supplied to a register 46, and the output of the register 46 is supplied to a multiplexer 45 and a comparison circuit 47. The multiplexer 45 is supplied with 0 and +1 in addition to the output of the register 46. When the amount of generated information is calculated, the amount of information At generated in one frame period, for example, is obtained from the output of the register 46.

In the comparison circuit 47, the generated information amount Ai is compared with the target value Q from the terminal 48, and the output signal of the comparison circuit 47 is supplied to the parameter code generation circuit 49 and the register 51. Parameter code Pi from parameter code generation circuit 49 is supplied to address generation circuit 50 and register 51. The parameter code Pi taken into the register 5l is supplied to the framing circuit 25 as described above, and is also supplied to the ROM 52. The ROM 52 stores a set of threshold values (Tl i, T2 t, Tat, T4
i) Generate. This threshold value is supplied to the comparator circuit 21 as described above.

FIG. 5 is a flowchart showing the operation of the buffering circuit 20. In the first step 61, the memory 41
Register 46 is cleared to zero. To zero-clear the memory 4l, the multiplexer 42 selects the address generated by the address generation circuit 50, and the output of the adder circuit 44 is always set to 0. The address is (0.1.2.・
. . , 255), and O data is written to all addresses of the memory 4l.

In the next step 62, the dynamic range D of one frame, which is a unit period buffered in the memory 41, is
A frequency distribution table of R' is generated.

The multiplexer 42 selects the dynamic range DR' from the terminal 43, and the multiplexer 45 selects +1. Therefore, when one frame period ends, each address in the memory 4l corresponding to the dynamic range DR' is The frequency of occurrence of each DR" is stored. The frequency distribution table in the memory 41, as shown in FIG. 6A, has DR'' as the horizontal axis and frequency as the vertical axis.

Next, the frequency distribution table is converted into a cumulative frequency distribution table (step 63). When calculating the cumulative frequency distribution table, the multiplexer 42 selects the address from the address generation circuit 50, and the multiplexer 45 selects the output of the register 46. The address decrements sequentially from 255 to 0.

The readout output of the memory 4l is supplied to the adder circuit 44,
The adder circuit 44 adds the contents of the register 46. The output of the adder circuit 44 is written to the same address as the read address of the memory 41, and the contents of the register 46 are updated to the output of the adder circuit 44. In the initial state where the address of the memory 4l is 255, the register 46 is cleared to zero. When the frequencies are accumulated for all addresses in the memory 41, the memory 41 stores the information shown in FIG. 6B.
The cumulative frequency distribution table shown in is created.

For this cumulative frequency distribution table, a set of threshold values (T1 i
, T 2 iST 3 t . ．． The amount of information At generated when T 4 i ) is applied is calculated (step 64
).

When calculating the generated information amount At, the multiplexer 42 selects the output of the address generation circuit 50, and the multiplexer 4
5 selects the output of register 46. The parameter code generation circuit 49 generates parameter codes that change sequentially from PO to P31. Parameter code Pi
is supplied to the address generation circuit 50, and (Tlt, T2
Addresses corresponding to each threshold value (t, T3 i, T4 i) are generated sequentially. Values read from addresses corresponding to each threshold value are accumulated by an adder circuit 44 and a register 46. This cumulative value corresponds to the amount of information At generated when the second half of the threshold specified by the parameter code Pi is applied. That is, in the cumulative frequency distribution table shown in FIG. 6B, values A1, A2, A3, A4 read from addresses corresponding to threshold values T1, T2, T3, T4
The value obtained by multiplying the total value (A1+A2+A3+A4) by the number of pixels in the block (64) is the amount of generated information (number of bits). However, the number of pixels is constant. Therefore, in the buffering circuit 20 shown in FIG. 4, 64 multiplication processes are omitted.

This generated information amount Ai is compared with the target value Q (step 65). The output of the comparison circuit 47, which occurs when (At≦Q) is established, is supplied to the parameter code generation circuit 49 and the register 51, and the increment of the parameter code Pi is stopped, and the parameter code Pi is taken into the register 5l. It will be done. The parameter code Pi from the register 5l and the set of threshold values generated in the ROM 52 are output (step 66).

At step 65 of determination in the comparison circuit 47, (Ai≦
When Q) is not established, the parameter code Pi is changed to the next one P i+1, and the address corresponding to P i+1 is generated from the address generation circuit 50. The generated information amount Ai+1 is calculated in the same manner as described above, and compared with the target value Q in the comparison circuit 47. The above-mentioned operation is repeated until (Al≦Q) is established.

d. Modification In the above description, the code signal DT, dynamic range OR', and average value MIN' are transmitted. However, instead of the dynamic range DR', the average value MAX'' or the quantization step width may be transmitted as the additional code.

〔Effect of the invention〕

According to the present invention, it is possible to prevent block distortion from occurring in blocks containing ringing, impulsive noise, and the like. In this invention, encoding can be performed efficiently using variable length ADRC, and since the dynamic range used for controlling the amount of generated information and quantization is the same, it is possible to make a mistake in the number of allocated bits n on the decoding side. This does not cause any problems.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a schematic diagram of an example of a block, Fig. 3 is a block diagram showing an example of a structure on the receiving side, and Fig. 4 is a diagram of a buffering circuit. An example block diagram, FIGS. 5 and 6 are flowcharts and schematic diagrams used to explain the buffering circuit, and FIGS. 7 and 8 are
9 and 9 are schematic diagrams used to explain the quantization operation and the occurrence of block distortion. Explanation of main symbols in the drawings 1: Input terminal, 3: Maximum value, minimum value detection circuit, 7: Subtraction circuit, 8: Addition circuit, 9: Bit shift circuit, l2, 13: Averaging circuit, 18: Quantization circuit, 20: buffering circuit, 25: framing circuit, 26: output terminal.

Claims (1)

[Scope of Claims] Means for determining the maximum and minimum values of a plurality of pixel data contained within a two-dimensional block of a digital image signal or a block consisting of N regions belonging to each of N temporally consecutive frames. , means for extracting pixels existing within a predetermined level range from each of the maximum value and the minimum value; means for forming a second average value of input image data included in a level range; means for calculating a dynamic range from the difference between the first average value and the second average value; The amount of information generated in a predetermined period is calculated, and the threshold value for setting the number of allocated bits for each block is controlled so that the amount of information generated falls within the predetermined amount of data. means for setting the number of allocated bits for each block based on the comparison output with the dynamic range; means for subtracting the second average value from the input image signal; and means for edge matching quantization.