JP3104384B2 - Decoding device and decoding method for block transform code - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block conversion code decoding apparatus for compressing a data amount by dividing a digital image signal into small blocks and processing the divided blocks.
In particular, the present invention relates to a decoding device and a decoding method capable of satisfactorily modifying an important word when the important word is an error.

[0002]

2. Description of the Related Art When a digital video signal is recorded on a recording medium such as a magnetic tape, the amount of information is large. Therefore, in order to achieve a transmission rate that can be recorded / reproduced, the digital video signal is encoded by a high efficiency encoding. Is usually compressed. ADRC and DCT (Discrete Cosine Trunking), which divide a digital video signal into a number of small blocks and perform coding processing for each block, are performed as high-efficiency coding.
ansform) are known. ADRC can be used, for example, as described in Japanese Patent Application Laid-Open No.
This is a high-efficiency coding that obtains a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a dimensional block, and performs encoding adapted to the dynamic range.

The coded outputs obtained by block transform coding do not have equal importance. In the ADRC, if the dynamic range information is not known on the reproduction side, decoding of all the pixels in the block becomes impossible. Therefore, the dynamic range information detected for each block is more important than the code signal for each pixel. high. In the case of DCT, D
In the coefficient data generated by CT, the DC component has a higher importance than the AC component. Also, in the case of DCT, not only the DC component but also information of the quantization step for each block is important. These encoded outputs with high importance are referred to as important words.

[0004]

In a digital VTR using ADRC, even if an important word is an error, all encoded outputs are decoded by using the value of the important word, or a block in which the important word is erroneous is replaced with an error block. In order to correct the error block with the surrounding decoded data. Regardless of the process, the block whose key word is an error is
There is a problem that block-shaped distortion is caused and deterioration of a restored image is conspicuous. Therefore, it is conceivable to estimate the error of the important word by a statistical method based on the spatial correlation between the peripheral block and the block of interest, but the estimation accuracy may be low depending on the picture. In the case of DCT as well, important words are modified using spatial correlation, but there is a similar problem.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a block transform code decoding apparatus and a decoding method capable of suppressing deterioration of a restored image when an important word is an error.

[0006]

According to the first aspect of the present invention, block encoding for compressing the amount of transmission information is performed for each block composed of a plurality of spatially adjacent pixels, and the degree of importance for decoding is high. The first data and the second
Is generated by block coding, and parity of an error correction code is added to the coded data to form transmission data, and block conversion for decoding each pixel data from the received transmission data In the code decoding device, a circuit for performing error correction of transmission data and generating an error flag indicating presence or absence of an error, and a decoding value of a peripheral block adjacent to the block of interest when the first data is an error. A first error correction circuit for estimating the first data by the least square method using the coded value of the block of interest, and a peripheral block adjacent to the block of interest when the first data is erroneous. For estimating the first data from the level of the decoded value of
Error correction circuit, a detection circuit for detecting the level distribution of the pixel data of the target block from the coded value of the target block, and selecting the outputs from the first and second error correction circuits in response to the detection. And a decoding circuit for supplying encoded data and decoding encoded data using the correct first data or selected first data for each block. It is a block transform code decoding device. The invention of claim 2 is empty
Transmission is performed for each block of pixels
Block coding is performed to compress the amount of information and is used for decoding
The first data with high importance and the
And the encoded data including the second data
And the parity of the error correction code is added to the encoded data.
Is added to the transmission data, and the received transmission data
Block transform code for decoding each pixel data from data
Error correction of transmission data in the decoding method of
Stearyl for generating an error flag indicating the presence or absence of an error
And-up, when the first data is in error, the target block
And the decoded value of the neighboring block
The first data is obtained by the least squares method using
A first error correction step for estimating a first de
If the data is in error, the neighboring blocks close to the block of interest
The first data is estimated from the level of the decoded value of the lock.
Second error correction step and the code of the block of interest
Detects the level distribution of pixel data of the block of interest from digitized values
A detecting step for performing the first and
To select the output from the second error correction step
The selection step and the transmission data are supplied, and the
Correct first data or selected first data
A decoding step for decoding the encoded data using
Decoding method of block transform code, characterized by comprising:
It is.

[0007]

A first error correction circuit and a second error correction circuit are provided, and a more appropriate error correction method is selected from the level distribution of a block of interest to be decoded. Thus, the accuracy of estimation can be improved by adaptive processing.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the decoding device according to the present invention will be described below. In FIG. 1, 1 indicates a first ADRC decoder, and 2 indicates a delay circuit. Although not shown,
The reproduced data reproduced from the magnetic tape, the channel code is decoded, and TBC (time axis correction), frame decomposition and error correction are supplied to one of the decoder 1 and the delay circuit 2 via the input switch S1. You. The reproduction data includes encoded data (code signal) of each pixel, a dynamic range DR for each block, and a minimum value MIN. The reproduced data also includes an error flag indicating whether or not there is an error for each sample of the code signal. An output switch S2 is provided on the output side of the decoder 1 and the delay line 2. When the present invention is applied to the (4: 2: 2) component digital signal, the configuration of FIG. 1 is provided for the luminance signal and the color difference signal.

EF1 is an error flag related to the dynamic range DR and the minimum value MIN, which are important words. The error flag EF1 has information on the presence or absence of an error regarding each of DR and MIN. For example, it is “1” when there is an error, and “0” when there is no error. The error flag EF1 is supplied to the delay circuit 3. Delay circuits 2 and 3 have a delay amount corresponding to the time required for the decoding operation of ADRC decoder 1. The input switch S1 is determined by the input error flag EF1.
Is controlled, and the output switch S2 is controlled by the delay error flag EF2.

That is, by EF1 and EF2,
When the key word is not an error, the input switch S1 and the output switch S2 are connected to the ADRC decoder 1
When the key word is an error, the input switch S1 and the output switch S2 select the delay circuit 2 side. As a result, from the output switch S2, a decoded output of a block whose important word is not error and a coded output of a block whose important word is error are extracted.

In this embodiment, the effective area of one frame is divided into blocks of (4 × 4) pixels. The ADRC encoder provided on the recording side detects the dynamic range DR and the minimum value MIN of each block, and requantizes the video data from which the minimum value has been removed in a quantization step. In the case of 4-bit fixed-length ADRC, the quantization step Δ can be obtained by setting the dynamic range DR to 1/16. In the quantization step Δ, the video data from which the minimum value has been removed is divided, and a value obtained by rounding down the quotient to an integer is used as a code signal.

Referring to FIG. 1, one embodiment of the present invention will be described again. The decoded value Li of each pixel is obtained from the ADRC decoder 1. This decoded value Li is represented by the following equation. Li = [(DR / 2 ⁴ ) × xi + MIN] = [Δ × xi + MIN]

Here, xi is the value of the code signal, Δ is the quantization step, and [] is the Gaussian symbol. The ADRC decoder 1 has a configuration in which the operation in the parentheses in the above equation is realized by, for example, a ROM and the minimum value MIN is added. From this equation, it can also be seen that when there is an error in the upper bits of the key words (DR and MIN), the error in the decoded value increases. The output of the output switch S2 is supplied to the memory 4 and the delay circuit 5.

The memory 4 is provided for extracting a code signal of a target block to be decoded and decoded data around the target block. In FIG.
x1 to x16 are coded values of the target block, and peripheral data y1 to y16 exist around the target block.
The peripheral data y1 to y16 are values decoded as described above for the upper, lower, left, and right blocks of the target block. The encoded data xi and the peripheral data y1 to y16 are supplied to the arithmetic circuit 6.

The arithmetic circuit 6 calculates the coded value x of the block of interest.
7 is a first important word error correction circuit for estimating an important word that is in error using i and peripheral data yi. Where x
Among i and yi, those determined to have an error by the error flag are not used for the estimation calculation. This prevents the accuracy of estimation from lowering. The arithmetic circuit 6 estimates an important word by the least square method as described below.

[0016] First, when both of the dynamic range DR and the minimum value MIN of the error Σxiyi = x1y1 + x2y2 + x3y3 + x4y4 + ··· + x16y16 Σxi = x1 + x2 + x3 + x4 + x1 + x5 + x9 + x13 + x13 + x14 + x 15 + x16 + x4 + x8 + x12 + x16 Σyi = y1 + y2 + y3 + ··· + y16 Σxi 2 = x 1 2 + x 2 2 + x 3 2 + · .. + Y ₁₆ ² Δ = (16Σxiyi−Σxi · Σyi) / (16Σxi ² − (Σxi) ² ) MIN = (Σyi−Σxi · Δ) / 16

Next, when an error occurs only in the dynamic range DR Δ = (Σyi−16 · MIN) / Σxi Further, when an error occurs only in the minimum value MIN MIN = (Σyi−Σxi · DR / 2 ⁴⁾ ) / 16

The arithmetic circuit 6 generates an estimated output of the dynamic range DR and the minimum value MIN by performing the above-described arithmetic operations. The dynamic range DR1 and the minimum value MIN1 from the arithmetic circuit 6 are supplied to the selector 7. The estimation of the important words performed by the arithmetic circuit 6 is a statistical method, and therefore causes a relatively large error depending on the picture. In order to increase the accuracy of the estimation, as described above, adaptive processing is performed in addition to excluding the error samples from the calculation targets.

That is, a second important word error correction circuit is provided. The dynamic range and minimum value detection circuit 7 in FIG. 1 is the second modification circuit. This circuit estimates the important word of the block of interest from the surrounding data by utilizing that the peripheral data adjacent to the block of interest has a strong spatial correlation with the block of interest when the important word is an error. The peripheral data y1 to y16 are supplied from the memory 4 to the detection circuit 7. The detection circuit 7 is also supplied with an error flag.

The detection circuit 7 detects the maximum value MAX2 (= max {y1 to y16}) and its minimum value MIN2 (= min {y1 to y16}) among the peripheral data y1 to y16, and detects the minimum value MIN2 and the minimum value MIN2. DR2 (= MAX2-MIN2) is output. These maximum value MAX2 and minimum value MIN
When forming 2, error data in the peripheral data is excluded by referring to the error flag. Further, when (DR2 <0), DR2 = 0, and (MIN
When 2 <0), MIN2 = 0. The output DR2 of the detection circuit 7 and the minimum value MIN2 are supplied to the selector 8.

The selector 8 is controlled by a control signal SL corresponding to the level distribution of the coded values of the block of interest. That is, when an important word monotonically increases (or decreases) in a direction in which an error block of interest is present, a method of estimating an important word of a block of interest from the maximum value and the minimum value of the surrounding data yi is based on the least square method. It is more effective. In other words, when there is a protrusion or a recess near the center of the block of interest, the estimation by the detection circuit 7 is not so effective.

There are various methods for detecting the monotone increase (or monotone decrease) of the block of interest. Here, a relatively simple method is employed. In other words, as shown in FIG. 2, the data of the target block is set to the data of the central part (x6, x7, x10, x11) and the data of the peripheral part (x1, x2, x3, x4, x5, x8, x
9, x12, x13, x14, x15, x15), and when both the maximum value and the minimum value of the block of interest exist in the data of the peripheral portion, conversely, the maximum value and If none of the minimum values exists, it is determined that the value is monotonically increasing (or decreasing).

In order to make this determination, in this example, the maximum value detection circuits 9 and 10, the minimum value detection circuit 11, and the comparison circuit 1
2, 13 and an AND gate 14 are provided. The maximum value detection circuit 9 detects the maximum value among all the coded values xi of the block of interest. The maximum value detection circuit 10 detects the maximum value among the above-described encoded values of the peripheral portion of the target block. The outputs of these detection circuits 9 and 10 are
2 is supplied. The comparison circuit 12 performs match detection. If the two detected maximum values are equal, the comparison circuit 12 determines that the maximum value of the target block exists in the peripheral portion, and outputs "1". Is generated from the comparison circuit 12.

The minimum value detection circuit 11 detects the minimum value in the peripheral data of the target block. The detected minimum value is supplied to the comparison circuit 13. Zero data is supplied to the comparison circuit 13. When the minimum value is zero, it is determined that the minimum value of the target block exists in the peripheral portion, and "1" is determined.
Is output from the comparison circuit 13. The outputs of the comparison circuits 12 and 13 are supplied to an AND gate 14. AND
The gate 14 generates a control signal SL for the selector 8.
This control signal SL becomes “1” when the maximum value and the minimum value exist in the peripheral portion of the target block.

The selector 8 selects the dynamic range DR2 and the minimum value MIN2 from the detection circuit 7 according to the control signal SL of "1". When this is "0", the dynamic range DR1 and the minimum value MI of the arithmetic circuit 6 are selected.
Select N1. That is, when the maximum value and the minimum value exist in the peripheral portion of the target block, it is determined that the level change is a monotonous change, and the outputs DR2 and MIN2 of the detection circuit 7 are selected.

An important word from the selector 8 is supplied to a second ADRC decoder 16 via a correction circuit 15. The error flag EF3 relating to the important word is supplied to the correction circuit 15. This error flag EF3 is
F2 is via a delay circuit 17 for timing adjustment. The important word from the correction circuit 15 and the code signal from the delay circuit 5 are supplied to the ADRC decoder 16. From the ADRC decoder 16, decoded data of each pixel and its error flag are obtained.

The decoded output of the ADRC decoder 16 is supplied to the input terminal a of the switch circuit S3. The output of the delay circuit 5 is supplied to the other input terminal b of the switch circuit S3 via the delay circuit 18. The switch circuit S3 is controlled by an important word error flag EF3, from which a decoded output DEC is extracted. The output of the delay circuit 5 is the output of the output switch S2, which is data in which the decoded output of the ADRC decoder 1 for the block in which the important word is not error and the encoded output of the block for the error block are mixed. The switch circuit S3 replaces the encoded output of the block in which the important word is in error with the decoded output from the ADRC decoder 16. Although not shown, the decoded output DEC undergoes processing such as error correction for correcting decoded data in error at the next stage, block decomposition, and the like.

The correction circuit 15 is provided to further improve the accuracy of the estimation of the important word, and has a configuration shown in FIG. Reference numeral 21 denotes a correction amount C formed as described later, which is DR1 or DR2, or MIN1 or MIN.
This is a correction circuit that performs correction by subtracting from 2. The addition circuit 22 adds the values of the two important words, and the addition output is supplied to the subtraction circuit 23, and the addition result is calculated based on the addition result.
5 is subtracted. The output SA of the subtraction circuit 23 is supplied to the correction value generation circuit 24 and the comparison circuit 25.

The correction circuit 15 utilizes that the sum of the dynamic range and the minimum value obtained by the addition circuit 22 should be 255 or less in the case of 8-bit quantization. The subtraction result SA obtained by subtracting 255 from the output of the addition circuit 22 is compared with a threshold value TH (for example, 0 data) by the comparison circuit 25, and the comparison circuit 25 detects that the subtraction result SA is 0 or less. As described above, the correction value generation circuit 24 generates the correction value C only when the subtraction result SA is 0 or less. The correction value generation circuit 24 is provided with an error flag EF3 indicating the presence or absence of an important word error.

In the correction circuit 15, the input important word is corrected as follows by the correction value C generated by the correction value generation circuit 21. Here, DR and MIN are D
R1 or DR2, MIN1 or MIN2, respectively. If both DR and MIN have an error, C = (MIN + DR-255) / 2, and DR-
C and MIN-C are corrected. If only DR is in error, C = MIN + DR-255, and DR-C
, And no correction for MIN is required.
If only MIN has an error, C = MIN + DR-2
55, the correction is performed by DR-C, and the correction for DR is unnecessary. If both DR and MIN are correct, it is normal to satisfy the condition of (DR + MIN) -255 ≦ 0, and no correction is made for the key word (C
= 0).

[0031]

According to the present invention, for a block in which an important word is erroneous, when estimating the important word of the block, the estimation process of the important word is changed in accordance with the distribution of the coded values of the block. , The accuracy of the estimation can be improved. Therefore, the accuracy of the estimation is not affected by the pattern,
A good restored image is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an important word processing circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining data used for an important word estimation process.

FIG. 3 is a block diagram of an example of a correction circuit in one embodiment of the present invention.

[Explanation of symbols]

1, 16 ADRC decoder 4 Memory for extracting peripheral data 6 Arithmetic circuit for estimating important words by least square method 7 Detection circuit for estimating important words from maximum and minimum values of peripheral data 8 Selector

Claims (2)

(57) [Claims] 1. Block coding for compressing a transmission information amount is performed for each block including a plurality of pixels spatially close to each other, and first data having high importance for decoding and relatively insignificant data And coded data including second data is generated by the block coding, parity of an error correction code is added to the coded data to form transmission data, and each pixel data is decoded from the received transmission data. Means for performing error correction on the transmission data and generating an error flag indicating presence / absence of an error, when the first data is an error, A first error for estimating the first data by a least square method using a decoded value of a peripheral block to be changed and an encoded value of the block of interest. Correction means; second error correction means for estimating the first data from a decoded value level of a neighboring block adjacent to the target block when the first data is an error; Detecting means for detecting a level distribution of pixel data of the block of interest from an encoded value; selecting means for selecting an output from the first and second error correcting means in response to the detection; A block to which the transmission data is supplied and decoding means for decoding the coded data by using the correct first data or the selected first data for each block. Decoding device for transform code. 2. A block comprising a plurality of spatially adjacent pixels.
For each lock, there is no block coding to compress the amount of transmitted information.
And the first data, which is important for decoding,
Encoded data including second data that is not
The encoded data generated by the block encoding
The parity of the error correction code is added to the
And restores each pixel data from the received transmission data.
In a method for decoding a block transform code for decoding, Performs error correction on the above transmission data and indicates whether there is an error.
Generate error flag Steps to When the first data is an error, the first data
The decoded value of the neighboring block that is in contact with the
The first data by the least squares method using the
A first error correction step for estimating the When the first data is an error, the first data
From the level of the decoded value of the neighboring block in contact, the first
A second error correction step for estimating the data; From the coded value of the noted block,
Detection step for detecting the level distribution of elementary data
When, The first and second error correction scans are responsive to the detection.
A selection step for selecting the output from the step; The transmission data is supplied, and the
The first data or the selected first data is
And a decoding step for decoding the encoded data.
Decoding of a block transform code, comprising:
Method.