JP2783898B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for planarizing an interlayer insulating film in a semiconductor device having a multilayer wiring structure.

(Prior Art) In recent years, since semiconductor devices have become sophisticated, many of the wirings have a multilayer wiring structure. This multilayer wiring has a structure in which conductive layers and insulating layers are alternately overlapped on a semiconductor substrate on which an element region is formed. In general, a liquid-absorptive film formed between conductive layers is called an interlayer insulating film.

By the way, the most important technique when forming a multilayer wiring is flattening of an interlayer insulating film. This is because when a first layer wiring is formed on a silicon oxide film formed on a semiconductor substrate to separate an element formation region and a wiring region, and a first interlayer insulating film is formed thereon as it is, the first The unevenness of the wiring pattern of the layer is directly reflected on the first interlayer insulating film, and a steep step is formed on the surface of the first interlayer insulating film. If the second wiring layer is formed on the first interlayer insulating film having such a steep step on the surface, the coverage of the wiring metal film becomes extremely poor and the processing of the wiring metal film becomes difficult.
As a result, a problem such as disconnection or short circuit occurs in the wiring of the second layer at the step portion, so that the surface of the interlayer insulating film needs to be as flat as possible.

Various devices have been devised in order to reduce such a step on the surface of the interlayer insulating film. As one of them, there is a resist etch back method as described in, for example, JP-A-59-2350.

FIG. 3 is a sectional view showing sequential steps of the resist etch-back method. As shown in FIG. 3A, an insulating film 22 and an aluminum wiring are formed on a semiconductor substrate 21 on which an element region is formed.
23, and a first interlayer insulating film 24 is formed thereon.

Next, as shown in FIG. 3B, an organic substance 25 such as a resist is spin-coated on the surface of the interlayer insulating film 24. At this time,
Since the resist 25 is formed by spin coating, its surface is substantially flat.

Next, as shown in FIG. 3 (c), the resist 25 and the interlayer insulating film 24 are etched back at a constant speed, and the resist remaining on the surface is removed, and as shown in FIG. 3 (d). Next, the surface of the interlayer insulating film 24 is flattened.

As another method for flattening the surface of the interlayer insulating film, for example, a spin-on-glass method (SOG method) disclosed in Japanese Patent Application Laid-Open No. 63-88845 is known. As shown in FIG. 4, the insulating film 32 is formed on the semiconductor substrate 31 on which the element region is formed.
Formed on the insulating film 32, and further, the aluminum wiring 33 is covered with a plasma oxide film 34, and further, silane is dissolved in an organic solvent (SO
G) After spin coating 35, it is baked to flatten the surface to some extent, and an interlayer insulating film 36 is formed thereon. According to this method, as shown in FIG. 4, an interlayer insulating film having no overhang portion on the surface can be obtained.

(Problems to be Solved by the Invention) However, in the case of the resist etch-back method, the success or failure of the planarization largely depends on the coating state of the interlayer insulating film. As shown in the figure, a step 23a on the reverse taper remains on the surface of the interlayer insulating film. Therefore, when wiring of the second layer is provided on the interlayer insulating film 23, there is a high possibility that disconnection or short circuit will occur, and there is a problem that the reliability of the semiconductor device is reduced.

Further, in the case of the spin-on-glass method, although the coating shape of the interlayer insulating film is improved as compared with the resist etch-back method, the SOG 35 cannot be applied thick because cracks are formed. Therefore, as shown by arrows in FIG. 6, there is a disadvantage that a large step remains on the surface of the interlayer insulating film 36 in a portion where the wiring pattern is sparse.

If a step is left on the surface of the interlayer insulating film as described above, it becomes difficult to process the upper metal wiring formed thereon. That is,
An aluminum layer is formed by sputtering an aluminum layer on the surface of the interlayer insulating film having a step, and a resist film for forming an aluminum pattern is applied on the aluminum layer. In such a case, there arises a problem that, for example, it is not possible to perform an in-focus good exposure when exposing the object.

The present invention compensates for the drawbacks of these conventional planarization techniques, and provides a method of manufacturing a semiconductor device in which a step is reduced to some extent when an interlayer insulating film is formed.

(Means and Actions for Solving the Problems) In order to solve the above problems, a method for manufacturing a semiconductor device according to the present application is a method for manufacturing a semiconductor device having a multilayer wiring structure, wherein a metal wiring film is formed on an insulating film. Forming a compensating film made of a substance on the metal wiring film such that a film forming speed of an interlayer insulating film to be formed later is lower than a film forming speed on the insulating film; Forming a wiring pattern by selectively etching the metal wiring film and the compensation film via a mask formed on the wiring film, and forming an interlayer insulating film on the insulating film and the wiring pattern It is characterized by having.

As described above, in the method of manufacturing a semiconductor device according to the present invention, the compensation film is formed on the surface of the wiring pattern, and the interlayer insulating film is formed thereon. As the compensation film, a substance is used in which the film formation rate of an interlayer insulation film to be formed later is lower than the film formation rate on the insulation film, so that the film of the interlayer insulation film formed on the wiring pattern surface is used. The thickness is smaller than the thickness of the interlayer insulating film formed on the insulating film exposed between the wiring patterns, and the surface of the interlayer insulating film is planarized to some extent at the stage of forming the interlayer insulating film. Can be.

Further, in the method for manufacturing a semiconductor device according to the present application, the method for manufacturing a semiconductor device having a multilayer wiring structure includes the steps of: forming a non-doped silicon oxide film or a phosphosilicate glass film on a boron phosphosilicate glass film; Forming a metal wiring layer on the oxide film or the phosphosilicate glass film,
Forming a compensating film on the metal wiring film such that a film forming speed of an interlayer insulating film to be formed later is smaller than a film forming speed on the non-doped silicon oxide film or the phosphosilicate glass film. Forming a resist pattern on the compensation film; selectively etching the metal wiring film and the compensation film using the resist pattern as a mask to form a wiring pattern; Normal pressure CV on the silicon oxide film or phosphosilicate glass film and the wiring pattern
Forming an interlayer insulating film by means of D.

As the compensation film, for example, boron phosphosilicate glass (hereinafter referred to as “BPSG”) can be given. Normal pressure CV
The deposition rate of the interlayer insulating film by D is
Since it is slower than the deposition rate on other oxide films and metal layers,
If the BPSG film is provided on the wiring pattern, the film thickness on the wiring pattern is reduced. When a BPSG film is used as an insulating film formed on a semiconductor substrate on which an element region is formed, the lower insulating film on the lower BPSG film is thickened so as to be thicker.
Non-doped silicon oxide film or PS on BPSG film surface
The G film is provided.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the thickness of the compensation film formed on the surface of the wiring pattern is 3000 mm or less.

If the thickness of the compensating film formed on the surface of the wiring pattern is too large, a reverse step will occur on the surface of the interlayer insulating film, and processing of the metal pattern by etching becomes difficult. Therefore, the thickness of the compensation film is 3000 は
Is preferably not exceeded.

Embodiment FIG. 1 is a cross-sectional view showing sequential manufacturing steps of a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

As shown in FIG. 1 (a), a non-doped silicon oxide film (hereinafter referred to as "NSG film") 2 is formed as an insulating film on the surface of a semiconductor substrate 1 on which an element region is formed. An aluminum alloy thin film 3 is formed as a metal wiring layer on the surface of the substrate.

Next, as shown in FIG. 1 (b), a BPSG film 4 is formed on the aluminum alloy thin film 3 as a compensating film so as to have a thickness of about 2000 °, and then the surface of the BPSG film 4 is formed. Next, a resist pattern 5 is formed by ordinary photolithography and etching techniques.

Next, as shown in FIG. 1C, dry etching is performed using the resist pattern 5 as a mask, and the BPSG film 4 and the aluminum alloy film 3 are selectively removed to form a first layer wiring pattern 6. I do.

Then, as shown in FIG. 1 (d), the non-doped silicon film 2 and the wiring pattern of the first layer are placed on
The silicon oxide film 7 is formed as an interlayer insulating film by the CVD method to complete the first layer wiring.

By repeating the above steps, wiring of the second and third layers is performed to form a multilayer wiring.

The film formation rate of the silicon oxide film by the normal pressure CVD method decreases in the order of aluminum, NSG film, PSG film, and BPSG film. Therefore, in this embodiment, since the BPSG film is formed on the first layer wiring pattern, the film forming speed of the interlayer insulating film 7 on the insulating film (non-doped silicon film) on the semiconductor substrate 1 is reduced. And the film forming speed is higher than the film forming speed on the first layer wiring pattern. Therefore, a step a caused by the wiring pattern 6 on the surface of the silicon oxide film 7
Is (thickness b of the interlayer insulating film 7 on the insulating film 2) − (thickness c of the interlayer insulating film 7 on the compensating film 6a) − (compensation) The film thickness d ) is reduced by (1).

As described above, according to the manufacturing method of the present invention, the surface of the interlayer insulating film can be flattened by a simple process of forming a compensation film, but the formula (1) becomes positive. It is necessary to form the silicon oxide film (interlayer insulating film) 7 up to the thickness, and the effect is limited. That is, the flattening effect cannot be obtained above (thickness b of the interlayer insulating film 7 on the insulating film 2)-(thickness c of the interlayer insulating film on the compensation film 6a).
It does not exceed 00-5000〜. Therefore, not only the method of manufacturing the semiconductor device of the present invention, but also the method of the present invention and the conventional etch-back method or spin-on-glass method are combined to more effectively planarize the surface of the interlayer insulating film. Can be. From equation (1), it can be seen that the maximum effect can be obtained by forming the silicon oxide film (interlayer insulating film) 7 thick and the BPSG film 6a thin in this embodiment. Can be more effectively planarized when combined with an etch-back method.

FIG. 2 is a sectional view showing a sequential manufacturing process of another embodiment of the method of manufacturing a semiconductor device according to the present invention.

In a normal semiconductor device, a BPSG film is often used as an insulating film for insulating a semiconductor substrate on which an element region is formed from a lowermost wiring layer because of its good covering shape. The BPSG film can be made to have a good covering shape by reflow after the film formation. On the other hand, when a silicon oxide film is formed by normal-pressure CVD, the film formation rate on the BPSG film becomes slow. Therefore, a BPSG film is suitable as the compensation film. In such a case, the interlayer insulating film is formed at the same speed on the lower insulating film and the compensation film. In this embodiment, in order to improve this, a material whose film formation rate is higher than the film formation rate of the interlayer insulating film on the BPSG film, for example, an NSG film is formed on the lower insulating film. It was made.

As shown in FIG. 2A, a BPSG film 12 is formed on a semiconductor substrate 11 on which an element region is formed as an insulating film for separating an element region and a wiring region, and an NSG film is formed on the BPSG film 12. Membrane 13
To form

Next, as shown in FIG. 2B, an aluminum alloy film 14 is formed as a metal wiring layer on the film 13, and a BPSG film 15 is formed on the aluminum alloy film 14.

Further, similarly to the first embodiment, a resist pattern is formed on the BPSG film 15 using a photolithography technique and an etching technique (not shown), and using this resist pattern as a mask, as shown in FIG. Wiring pattern as shown
Form 16. Next, an interlayer insulating film 17 is formed by normal pressure CVD to form a first wiring layer. By repeating the same steps, the second and subsequent wiring layers are performed in the same manner as in the first embodiment.

In the present embodiment, a BPSG film 15 was formed on the surface of an aluminum wiring layer and an NSG film 13 was formed between a BPSG film 12 and an interlayer insulating film 17 on a semiconductor substrate 11, as in the first embodiment. . Therefore, the interlayer insulating film 17 is formed on the BPSG film 16a provided on the NSG film 13 and the aluminum wiring 14, and is formed faster on the NSG film 13.
Therefore, the step e on the surface of the interlayer insulating film 17 is reduced by (interlayer insulating film f on the oxide film 13) − (interlayer insulating film g on the compensating film 16a) − (film thickness h of the compensating film 16a). Will be done.

As described above, since the film formation speed of the interlayer insulating film by the normal-temperature CVD decreases on the NSG film, the PSG film, and the BPSG film in this order, in the case of the second embodiment, BPSG is used as a compensation film. When the NSG film is formed under the aluminum wiring, the effect of the present invention is the greatest.

In the above-described embodiment, the film formed on the BPSG film 12 is NS
Although the G film 13 was used, since the film formation speed of the interlayer insulating film on the PSG film is higher than the film formation speed on the BPSG film, if the NSG film cannot be formed due to film stress or other problems, the PSG film is formed. You may do it.

It is preferable that the thickness of the compensation film formed on the metal wiring be 3000 mm or less. For example, NSG as an interlayer insulating film
When a film is used, the film formation rate is in the order of on aluminum alloy> on NSG> on BPSG, but if the compensation film is deposited thickly, the effect of the present invention is reduced, and a negative effect is also caused. . Further, since there is a demerit that the dry etching becomes difficult when the compensation film is deposited in a large thickness, about 2000 mm is preferable.

In the above-described embodiment, providing the compensation film
Even when the resist layer is deteriorated during aluminum wiring processing and becomes difficult to peel off, the effect of increasing variations in the process for removing the resist can be expected.

In the above-described embodiment, when dry etching the metal wiring layer, after etching the compensating film, the resist pattern is removed, and for example, a gas such as CHCl _{3 to which} the sidewall protective film easily adheres is selected as an etching gas. Thus, the metal wiring pattern may be formed using the compensation film as a mask. In this case, since the resist does not contact the surface of the metal wiring layer, it is advantageous for erosion and corrosion.

(Effect of the Invention) As described above, according to the method of manufacturing a semiconductor device of the present invention, an interlayer insulating film is formed by a simple and simple method of forming a compensation film immediately after forming a metal wiring layer. In this step, the surface of the interlayer insulating film can be flattened to some extent, and the reliability of wiring of the semiconductor device can be significantly improved. As a secondary effect, the second
In the photo-etching performed when the layer and the third wiring layer are formed, the compensating film functions as an antireflection film for the metal wiring layer, so that the productivity of the semiconductor device is also improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a sequential manufacturing process of a first embodiment of the present invention, FIG. 2 is a sectional view showing a sequential manufacturing process of a second embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view showing a planarization step by the back method, and FIG. 4 is a cross-sectional view showing a planarization step by the SOG method. 5 and 6 are views showing a wiring layer formed by a conventional method. 1, 11, a semiconductor substrate, 2, 12, an insulating film 3, 14, a metal wiring layer, 4, 15, a compensating film 6, 16, a wiring pattern 7, 17, an interlayer insulating film 13, etc. Non-doped silicon oxide film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768 H01L 21/316

Claims (3)

(57) [Claims] In a method of manufacturing a semiconductor device having a multilayer wiring structure, a step of forming a metal wiring film on an insulating film;
Forming a boron phosphosilicate glass film on the metal wiring film in which a film formation speed of an interlayer insulating film to be formed later is smaller than a film formation speed on the insulating film; and forming a film on the boron phosphosilicate glass film. A step of selectively etching the boron phosphosilicate glass film and the metal wiring film through the formed mask to form a wiring pattern, and forming an interlayer insulating film on the insulating film and the wiring pattern by normal pressure CVD. A method of manufacturing a semiconductor device. 2. A method for manufacturing a semiconductor device having a multi-layer wiring structure, comprising: forming a non-doped silicon oxide film or a phosphosilicate glass film on a boron phosphor silicate glass film; A step of forming a metal wiring film on the glass film, and a compensation made of a substance such that a film formation rate of an interlayer insulating film to be formed later is smaller than that on the non-doped silicon oxide film or the phosphosilicate glass film. Forming a film on the metal wiring film, forming a resist pattern on the compensation film, and selectively etching the metal wiring film and the compensation film using the resist pattern as a mask. Forming a wiring pattern, the non-doped silicon oxide film or phosphor film; The method of manufacturing a semiconductor device, characterized in that comprises a step of forming an interlayer insulating film by atmospheric pressure CVD on silicate glass film. 3. The film according to claim 1, wherein the thickness of the boron phosphosilicate glass film according to claim 1 or the thickness of the compensation film according to claim 2 is 3000 ° or less. A method for manufacturing a semiconductor device.