KR100509434B1 - Method for improving photo resist adhesion - Google Patents
Method for improving photo resist adhesion Download PDFInfo
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- KR100509434B1 KR100509434B1 KR10-2003-0006320A KR20030006320A KR100509434B1 KR 100509434 B1 KR100509434 B1 KR 100509434B1 KR 20030006320 A KR20030006320 A KR 20030006320A KR 100509434 B1 KR100509434 B1 KR 100509434B1
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
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- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02107—Forming insulating materials on a substrate
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Abstract
본 발명은 듀얼 대머신(Dual Damascene) 공정을 이용한 반도체 소자의 제조방법에 관한 것으로, 보다 자세하게는 듀얼 대머신 공정 중에 포토레지스트 점착성 개선 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device using a dual damascene process, and more particularly, to a method for improving photoresist adhesiveness during a dual damascene process.
본 발명의 상기 목적은 소정의 하부 구조물이 형성된 실리콘 기판(20)상에 각각 제 1 절연막층(21), 식각스톱층(22) 및 제 2 절연막층(23)을 형성하는 제 1공정; 제 1 포토공정으로 상기 제 2 절연막층(23)을 선택적으로 제거하여 트랜치(25)를 형성하는 제 2공정; 포토레지스트의 단차피복성 개선과 포토레지스트의 점착성의 향상을 위하여 막질의 표면을 미세하게 식각하는 프리패턴 애쉬 공정인 제 3공정; 제 2 포토공정으로 상기 반도체 기판(20)의 표면이 소정부분 노출되도록 상기 제 1 절연막층(21)을 제거하여 콘택홀(27)을 형성하는 제 4공정; 및 상기 콘택홀(27)을 포함한 반도체 기판(G)의 전면에 금속층(28)을 형성한 후, 평탄화 공정을 실시하여 상기 콘택홀(27) 내부에 듀얼 대머신 구조를 갖는 금속배선을 형성하는 제 5공정을 포함하여 이루어짐을 특징으로 하는 포토레지스트 점착성 개선 방법에 의해 달성된다.The above object of the present invention is a first process of forming a first insulating film layer 21, an etch stop layer 22 and a second insulating film layer 23 on the silicon substrate 20, the predetermined lower structure is formed; A second process of selectively removing the second insulating film layer 23 to form a trench 25 in a first photo process; A third process, which is a pre-pattern ash process of finely etching the surface of the film to improve the step coverage of the photoresist and the adhesion of the photoresist; A fourth step of forming a contact hole 27 by removing the first insulating layer 21 to expose a predetermined portion of the surface of the semiconductor substrate 20 by a second photo process; And forming a metal layer 28 on the entire surface of the semiconductor substrate G including the contact hole 27, and then performing a planarization process to form a metal wiring having a dual damascene structure inside the contact hole 27. It is achieved by a method for improving the photoresist adhesion, characterized in that comprises a fifth step.
따라서, 본 발명의 듀얼 대머신 공정에서의 포토레지스트 점착성 개선 방법은 듀얼 대머신 공정중에 콘택을 형성하기 위해 포토레지스트를 도포하기 전에 프리패턴 애쉬 공정을 추가하므로써 포토레지스트공정의 단차피복성의 개선과 포토레지스트의 점착성을 향상시키는 효과가 있다.Therefore, the method of improving photoresist adhesion in the dual damascene process of the present invention improves the step coverage of the photoresist process by adding a prepattern ash process before applying the photoresist to form a contact during the dual damascene process. There is an effect of improving the adhesion of the resist.
Description
본 발명은 듀얼 대머신(Dual Damascene) 공정을 이용한 반도체 소자의 제조방법에 관한 것으로, 보다 자세하게는 듀얼 대머신 공정 중에 포토레지스트 점착성 개선 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device using a dual damascene process, and more particularly, to a method for improving photoresist adhesiveness during a dual damascene process.
일반적으로 반도체 장치의 금속배선 구조가 다층화됨에 따라 콘택홀 또는 비아홀은 횡(橫)방향과 같은 비율로 종(縱)방향의 기하학적 사이즈를 축소하기가 어려워져서 에스펙트 비(aspect ratio)가 증대하고 있다.In general, as the metallization structure of the semiconductor device is multilayered, the contact hole or the via hole becomes difficult to reduce the geometrical size in the longitudinal direction at the same ratio as the transverse direction, thereby increasing the aspect ratio. have.
이에 따라 기존의 금속배선층 형성방법을 사용하는 경우, 비평탄화, 불량한 단차 피복성(step coverage), 금속 단락, 낮은 수율 및 신뢰성의 열화 등과 같은 문제점들이 발생하게 된다.Accordingly, when using the conventional metallization layer forming method, problems such as unplanarization, poor step coverage, metal short circuit, low yield, and deterioration of reliability occur.
이러한 문제점들을 해결하기 위한 새로운 배선기술로서 콘택홀의 매몰과 금속배선층을 동시에 형성하는 소위, 듀얼 대머신 공정이 제안되었다.In order to solve these problems, a so-called dual damascene process for simultaneously forming a buried contact hole and a metal wiring layer has been proposed.
이러한 듀얼 대머신 구조의 금속 증착은 알루미늄(Al)이나 구리(Cu) 증착 공정을 사용하는 것이 가장 유력하며, Al 공정을 적용할 경우에는 화학적 기상 증착법(chemical vapor deposition : CVD)/물리적 기상증착법(physical vapor deposition : PVD) 연속 증착 공정을 이용하여 Al 플러그(plug)나 Al 라인(line)을 형성하고 있다.The metal deposition of the dual damascene structure is most likely to use an aluminum (Al) or copper (Cu) deposition process, and when the Al process is applied, chemical vapor deposition (CVD) / physical vapor deposition ( Physical vapor deposition (PVD) continuous deposition process is used to form Al plugs or Al lines.
점착성(Adhesion) 또한 반도체 공정에서 포토레지스트가 각종 막의 표면에 잘 붙는 특성도 중요한 변수이다. 만일 포토레지스트가 식각하는 동안 일어나 버리면(Life Off), 패턴의 크기는 마스크 패턴보다 크거나 작게 된다.Adhesion In addition, the adhesion of photoresist to the surface of various films in the semiconductor process is also an important parameter. If the photoresist rises during etching (Life Off), the size of the pattern becomes larger or smaller than the mask pattern.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 금속배선 형성방법을 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 제 1 실시예에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to a first embodiment of the present invention.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 절연막(12)을 형성하고, 상기 절연막(12)상에 제 1 포토레지스트(13)를 도포한 후, 노광 및 현상공정으로 제 1 포토레지스트(13)를 패터닝하여 트랜치(Trench) 영역을 정의한다.As shown in FIG. 1A, an insulating film 12 is formed on a semiconductor substrate 11, a first photoresist 13 is coated on the insulating film 12, and then the first photo is subjected to an exposure and development process. The resist 13 is patterned to define trench regions.
도 1b에 도시한 바와 같이, 상기 패터닝된 제 1 포토레지스트(13)를 마스크로 이용하여 상기 노출된 절연막(12)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(14)를 형성하고, 상기 제 1 포토레지스트(13)를 제거한다.As shown in FIG. 1B, the exposed insulating layer 12 is selectively removed using the patterned first photoresist 13 as a mask to form a trench 14 having a predetermined depth, and the first The photoresist 13 is removed.
도 1c에 도시한 바와 같이, 상기 트랜치(14)를 포함한 반도체 기판(11)의 전면에 제 2 포토레지스트(15)를 도포한 후, 노광 및 현상공정으로 상기 제 2 포토레지스트(15)를 패터닝하여 콘택영역을 정의한다.As shown in FIG. 1C, after the second photoresist 15 is applied to the entire surface of the semiconductor substrate 11 including the trench 14, the second photoresist 15 is patterned by an exposure and development process. To define the contact area.
도 1d에 도시한 바와 같이, 상기 패터닝된 제 2 포토레지스트(15)를 마스크로 이용하여 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 절연막(12)을 제거하여 콘택홀(16)을 형성하고, 상기 제 2 포토레지스트(15)를 제거한다.As shown in FIG. 1D, using the patterned second photoresist 15 as a mask, a contact hole 16 is formed by removing the insulating layer 12 to expose a predetermined portion of the surface of the semiconductor substrate 11. Then, the second photoresist 15 is removed.
도 1e에 도시한 바와 같이, 상기 콘택홀(16)을 포함한 반도체 기판(11)의 전면에 금속배선용 금속층(17)을 증착한 후, 화학 기계 연마(chemical machine polishing : CMP)나 에치백(Etch Back) 등의 평탄화 공정을 실시하여 상기 콘택홀(16)내부에 듀얼 대머신 구조를 갖는 금속배선을 형성한다.As illustrated in FIG. 1E, after depositing the metal layer 17 for metal wiring on the entire surface of the semiconductor substrate 11 including the contact hole 16, chemical machine polishing (CMP) or etch back (Etch) may be used. And a planarization process such as a back) to form a metal wiring having a dual damascene structure in the contact hole 16.
그러나 상기와 같은 종래의 반도체 소자의 금속배선 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming metal wirings of semiconductor devices has the following problems.
상기 제 2 포토레지스트(15)를 도포시 웨이퍼의 표면이 불균일한 상태에서 이루어 지기 때문에 트렌치 영역의 코너 부분에서 포토레지스트가 골고루 배포되지 않을 경우가 발생한다.Since the surface of the wafer is uneven when the second photoresist 15 is applied, the photoresist may not be evenly distributed at the corners of the trench region.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 콘택영역을 패터닝하기 전에 프리패턴 애쉬(Pre-pattern ash)라는 공정을 추가하여 포토레지스트 공정의 단차피복성의 개선과 포토레지스트의 점착성을 향상시키도록 하는 듀얼 대머신 공정에서의 포토레지스트 점착성 개선을 위한 방법을 제공함에 본 발명의 목적이 있다. Accordingly, the present invention is to solve the problems of the prior art as described above, by adding a process called pre-pattern ash before patterning the contact region to improve the step coverage of the photoresist process and It is an object of the present invention to provide a method for improving photoresist tackiness in a dual damascene process to improve tack.
본 발명의 상기 목적은 소정의 하부 구조물이 형성된 실리콘 기판(20)상에 각각 제 1 절연막층(21), 식각스톱층(22) 및 제 2 절연막층(23)을 형성하는 제 1공정; 제 1 포토공정으로 상기 제 2 절연막층(23)을 선택적으로 제거하여 트랜치(25)를 형성하는 제 2공정; 포토레지스트의 단차피복성 개선과 포토레지스트의 점착성의 향상을 위하여 막질의 표면을 O2 Plasma, CxFx계열의 가스 또는 Ar가스를 이용하여 미세하게 식각하는 프리패턴 애쉬 공정인 제 3공정; 제 2 포토공정으로 상기 반도체 기판(20)의 표면이 소정부분 노출되도록 상기 제 1 절연막층(21)을 제거하여 콘택홀(27)을 형성하는 제 4공정; 및 상기 콘택홀(27)을 포함한 반도체 기판(G)의 전면에 금속층(28)을 형성한 후, 평탄화 공정을 실시하여 상기 콘택홀(27) 내부에 듀얼 대머신 구조를 갖는 금속배선을 형성하는 제 5공정을 포함하여 이루어짐을 특징으로 하는 포토레지스트 점착성 개선 방법에 의해 달성된다.The above object of the present invention is a first process of forming a first insulating film layer 21, an etch stop layer 22 and a second insulating film layer 23 on the silicon substrate 20, the predetermined lower structure is formed; A second process of selectively removing the second insulating film layer 23 to form a trench 25 in a first photo process; A third process, which is a prepattern ash process of finely etching the surface of the film using O 2 Plasma, CxFx-based gas, or Ar gas to improve the step coverage of the photoresist and the adhesion of the photoresist; A fourth step of forming a contact hole 27 by removing the first insulating layer 21 to expose a predetermined portion of the surface of the semiconductor substrate 20 by a second photo process; And forming a metal layer 28 on the entire surface of the semiconductor substrate G including the contact hole 27, and then performing a planarization process to form a metal wiring having a dual damascene structure inside the contact hole 27. It is achieved by a method for improving the photoresist adhesion, characterized in that comprises a fifth step.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 금속배선 형성방법을 설명하기 위한 각 공정별 단면도로서, 이를 설명하면 다음과 같다.2A to 2G are cross-sectional views for each process for explaining a method for forming metal wirings according to an embodiment of the present invention.
도 2a에 도시한 바와 같이, 소정의 하부 구조물이 형성된 실리콘 기판(20)상에 제 1 절연막층(21)을 형성하고, 상기 제 1 절연막층(21) 상부에 식각 스톱퍼(Etch Stopper)역할을 하는 식각스톱층(22)을 형성한다.As shown in FIG. 2A, a first insulating layer 21 is formed on a silicon substrate 20 on which a predetermined lower structure is formed, and an etch stopper is formed on the first insulating layer 21. An etch stop layer 22 is formed.
상기 제 1 절연막층(21)은 화학적 기상증착법으로 증착된 PMD(Pre Metal Dielectric)막으로 소정 두께의 BPSG(borophospho silicate glass) 또는 TEOS(tetra-ethylortho silicate)로 형성할 수 있고 그 주성분은 SiO2이다.The first insulating layer 21 is a PMD (Pre Metal Dielectric) film deposited by chemical vapor deposition, which may be formed of borophospho silicate glass (BPSG) or tetra-ethylortho silicate (TEOS) having a predetermined thickness, and a main component thereof is SiO 2. to be.
상기 식각스톱층(22)은 SiON, Si3N4 등의 물질을 500 ~ 1000Å 두께로 형성한다.The etch stop layer 22 is formed of a material such as SiON, Si 3 N 4 to a thickness of 500 ~ 1000Å.
도 2b에 도시한 바와 같이, 상기 식각스톱층(22)상에 제 2 절연막층(23)을 형성한다.As shown in FIG. 2B, a second insulating layer 23 is formed on the etch stop layer 22.
상기 제 2 절연막층(23)은 화학적 기상증착법으로 증착된 IMD(Inter Metal Dielectric)막으로 소정 두께의 BPSG 또는 TEOS로 형성할 수 있고 그 주성분은 SiO2이다.The second insulating layer 23 is an intermetal dielectric (IMD) film deposited by chemical vapor deposition, and may be formed of BPSG or TEOS having a predetermined thickness, and a main component thereof is SiO 2 .
도 2c에 도시한 바와 같이, 상기 제 2 절연막층(23)상에 제 1 포토레지스트(24)를 도포한 후, 노광 및 현상공정으로 상기 제 1 포토레지스트(24)를 패터닝하여 트렌치(trench)영역을 정의한다.As shown in FIG. 2C, the first photoresist 24 is coated on the second insulating layer 23, and then the first photoresist 24 is patterned in an exposure and development process to trench. Define the area.
도 2d에 도시한 바와 같이, 상기 패터닝된 제 1 포토레지스트(24)를 마스크로 이용하여 상기 노출된 제 2 절연막층(23)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(25)를 형성하고, 상기 제 1 포토레지스트(24)를 제거한다.As shown in FIG. 2D, the exposed second insulating layer 23 is selectively removed using the patterned first photoresist 24 as a mask to form a trench 25 having a predetermined depth. The first photoresist 24 is removed.
후에, 포토레지스트의 단차피복성(step coverage) 개선과 포토레지스트의 점착성(adhesion)을 향상을 위하여 프리패턴 애쉬(Pre-Pattern Ash) 공정을 추가 한다.Subsequently, a pre-pattern ash process is added to improve step coverage of the photoresist and to improve adhesion of the photoresist.
도 2e에 프리패턴 애쉬 공정을 나타내었다.2E illustrates a prepattern ash process.
상기 프리패턴 애쉬 공정은 O2 Plasma를 이용하여 막질의 표면에 미세한 식각를 가해 표면을 거칠게 만들어 그 분위기를 이용하여 포토레지스트의 점착성을 증가시킨다.In the prepattern ash process, fine etching is performed on the surface of the film using O 2 Plasma to roughen the surface to increase the adhesion of the photoresist using the atmosphere.
상기 상기 프리패턴 애쉬 공정에는 에는 O2 Plasma외에 CxFx(C2F6…)계열의 가스, Ar가스 등 표면에 미세한 거칠기를 유발할수 있는 모든 가스를 포함한다.The prepattern ash process includes not only O 2 Plasma but also all gases that may cause fine roughness on the surface such as CxFx (C2F6...) -Based gas and Ar gas.
도 2f에 도시한 바와 같이, 프리패턴 애쉬 공정후에 상기 트랜치(25)를 포함한 반도체 기판(E)의 전면에 제 2 포토레지스트(26)를 도포한 후, 노광 및 현상공정으로 상기 제 2 포토레지스트(26)를 패터닝하여 콘택영역을 정의한다.As shown in FIG. 2F, after the prepattern ash process, the second photoresist 26 is coated on the entire surface of the semiconductor substrate E including the trench 25, and then the second photoresist is exposed and developed. (26) is patterned to define the contact area.
도 2g에 도시한 바와 같이, 상기 패터닝된 제 2 포토레지스트(26)를 마스크로 이용하여 상기 반도체 기판(20)의 표면이 소정부분 노출되도록 제 1 절연막층(21)을 제거하여 콘택홀(27)을 형성하고, 상기 제 2 포토레지스트(27)를 제거한다.As shown in FIG. 2G, by using the patterned second photoresist 26 as a mask, the first insulating layer 21 is removed to expose a predetermined portion of the surface of the semiconductor substrate 20 to form a contact hole 27. ), And the second photoresist 27 is removed.
상기 콘택홀(27)을 형성한 후에 클리닝(Cleaning)을 실시하여 식각공정중에 발생한 이물질을 제거한다.After the contact hole 27 is formed, cleaning is performed to remove foreign substances generated during the etching process.
도 2h에 도시한 바와 같이, 상기 콘택홀(27)을 포함한 반도체 기판(G)의 전면에 금속배선용 W, Al, Cu, Poly-Si등의 금속층(28)을 형성한 후, 에치백이나 화학 기계 연마 공정 등의 평탄화 공정을 실시하여 상기 콘택홀(27)내부에 듀얼 대머신 구조를 갖는 금속배선을 형성한다.As shown in FIG. 2H, a metal layer 28 such as W, Al, Cu, or Poly-Si for metal wiring is formed on the entire surface of the semiconductor substrate G including the contact hole 27, and then etch back or chemical A planarization process such as a mechanical polishing process is performed to form a metal wiring having a dual damascene structure in the contact hole 27.
도 3은 본 발명의 공정순서에 따른 프로우 차트이다.3 is a flow chart according to the process sequence of the present invention.
플로우 차트를 통하여 본 발명의 공정을 알아 볼 수 있다. The process of the present invention can be seen through a flow chart.
상세히 설명된 본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 다양한 변형이 가능함이 명백하다.The present invention described in detail is not limited to the above-described embodiment, and it is apparent that various modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.
따라서, 본 발명의 듀얼 대머신 공정에서의 포토레지스트 점착성 개선 방법은 듀얼 대머신 공정중에 콘택을 형성하기 위해 포토레지스트를 도포하기 전에 프리패턴 애쉬 공정을 추가하므로써 포토레지스트공정의 단차피복성의 개선과 포토레지스트의 점착성을 향상시키는 효과가 있다.Therefore, the method of improving photoresist adhesion in the dual damascene process of the present invention improves the step coverage of the photoresist process by adding a prepattern ash process before applying the photoresist to form a contact during the dual damascene process. There is an effect of improving the adhesion of the resist.
도 1a 내지 도 1e는 종래기술에 의한 반도체 제조 방법.1A to 1E illustrate a semiconductor manufacturing method according to the prior art.
도 2a 내지 도 2h는 본 발명에 의한 반도체 제조 방법.2A to 2H illustrate a semiconductor manufacturing method according to the present invention.
도 3은 본 발명에 의한 반도체 제조 방법의 flow chat.Figure 3 is a flow chat of the semiconductor manufacturing method according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 20 : 반도체 기판 12 : 절연막11 and 20: semiconductor substrate 12: insulating film
13, 24 : 제 1 포토레지스트 14, 25 : 트렌치13, 24: first photoresist 14, 25: trench
15, 26 : 제 2 포토레지스트 16, 27 : 콘택홀15, 26: second photoresist 16, 27: contact hole
17, 28 : 금속층 21 : 제 1 절연막층17, 28: metal layer 21: first insulating film layer
22 : 식각스톱층 23 : 제 2 절연막층22: etching stop layer 23: second insulating film layer
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