JPH05160126A - Formation of multilayer wiring - Google Patents

Abstract

PURPOSE:To reduce the residue of an unstable insulating film and thereby to increase the flatness, in the formation of a multilayer wiring. CONSTITUTION:Wiring layers 14A and 14B are formed on an insulating film 12 which covers the surface of a semiconductor substrate 10. After that, an insulating film 16 is so deposited to cover these wiring layers. Nextly, a resist layer is formed on the insulating film 16 and then the insulating film 16 and the resist layer are etched back at nearly the same speed to remove a residual resist layer. Then, an insulating film 26 formed of SOG or other material is formed on a residual insulating film 16 and then the insulating films 16 and 26 are etched back at nearly the same speed so that the insulating film 26 may not remain above the wiring layers 14A and 14B. After that, an insulating film 28 is so deposited as to cover the residual insulating films 16 and 26 and then a contact hole is so formed as to correspond to a part of the wiring layer 14B. Through this contact hole, wiring layer 30 is so formed as to be connected to the wiring layer 14B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer wiring used in the manufacture of LSIs and the like, and particularly to an unstable coating by performing an etchback process using a coating insulating film after an etchback process using a resist layer. This is intended to reduce the remaining insulating film and improve the flatness.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a multi-layer wiring of an LSI, the method exemplified in FIGS.

In the process of FIG. 7, a desired wiring material is deposited on an insulating film 12 such as silicon oxide covering the surface of a semiconductor substrate 10 such as silicon and patterned to form a first wiring layer 14A, 14B is formed. And
Plasma C is formed on the upper surface of the substrate by covering the wiring layers 14A and 14B.
The insulating film 16 made of silicon oxide or the like is formed by the VD (chemical vapor deposition) method or the like. Then, in order to flatten the upper surface of the substrate, S is deposited on the insulating film 16.
The coating insulating film 18 is formed by spin coating OG (spin on glass).

Next, in the process of FIG. 8, insulating films 16 and 18 are formed.
Is etched back at a substantially constant speed to remove the insulating film 18 above the wiring layers 14A and 14B. This is to prevent a part of the hygroscopic insulating film 18 from being exposed inside the connection hole, which will be described later, and causing conduction failure.

Next, in the process of FIG. 9, insulating films 16 and 18 are formed.
An insulating film 20 of silicon oxide or the like is formed by plasma CVD or the like so as to cover the remaining portion. Then, for example, a connection hole CH is formed in the lamination of the insulating films 16 and 20 corresponding to a part of the wiring layer 14B by a photolithography process or the like. At this time, part of the insulating film 18 is not exposed inside the connection hole CH.

After that, a wiring material is deposited on the upper surface of the substrate and patterned to form a second wiring layer 22. The wiring layer 22 is connected to the wiring layer 14B via the connection hole CH.

10 to 13 show another conventional example, in which the same parts as those in FIGS. 7 to 9 are designated by the same reference numerals.

In the step of FIG. 10, the first wiring layers 14A and 14B and the insulating film 16 are formed on the insulating film 12 on the surface of the semiconductor substrate 10 in the same manner as described with reference to FIG. Then, a resist layer 24 is formed by, for example, spin coating a resist.

Next, in the process shown in FIG. 11, the insulating film 16 and the resist layer 24 are etched back at a substantially constant speed to form the wiring layer 1.
The insulating film 16 and the resist layer 24 are partially left above the upper surface level of 4A and 14B. Then, the remaining portion of the resist layer 24 is removed by ashing with O ₂ plasma or the like.

Next, in the process of FIGS.
An insulating film 20 is formed so as to cover the remaining portion of 6. And
After forming connection holes as required, a wiring material is deposited on the insulating film 20 and patterned to form the second wiring layers 22A and 22B.

[0011]

According to the conventional method shown in FIGS. 7 to 9, it is necessary to form the coating insulating film 18 sufficiently thick with respect to the height of the wiring steps in order to obtain sufficient flatness. However, if the insulating film 18 is thickened, cracks are likely to occur and reliability is lowered.

Further, in order to reduce the conduction failure in the connection hole CH, it is necessary to sufficiently etch back so that the insulating film 18 does not remain above the wiring layer such as 14B. However, sufficient etch back deteriorates the flatness. That is, the insulating film 18 is likely to be excessively etched in the recess P or the like between the wirings due to the difference in effective etching rate, as shown in FIG. For this reason, when the wiring layer 22 is formed as shown in FIG. 9, the coverage of the wiring material in the recess P is deteriorated, which causes a problem of disconnection failure.

On the other hand, according to the conventional method shown in FIGS. 10 to 13, since the etching rate changes during the etching back, it is not easy to maintain the shape immediately after the resist application. For example, in FIG.
As shown in FIG. 12, in the recesses P between the wirings, two shaped portions remain after the resist remaining portion is removed, and when the insulating film 20 is formed on the insulating film 16 as shown in FIG. Corresponding to, and so on, two shaped portions S _{1 to} S ₄ are produced.
After this, as shown in FIGS.
Wiring layers 22A intersecting with B, and when forming the 22B, when patterned by selective etching wiring material layer was deposited, one Jo parts S ₁ to S wire which can elaborate around under ₄ is not sufficiently etched Will remain. That is, the wiring layers 22A and 22B by the wiring material remaining portion 22S ₂ under the horn-shaped portion S ₂ as shown in FIG. 13 One example is to be interconnected, there is an inconvenience that a short circuit failure occurs.

An object of the present invention is to provide a method for forming a highly reliable multilayer wiring structure with high yield.

[0015]

A method for forming a multilayer wiring according to the present invention comprises: (a) a step of forming a first wiring layer on an insulating surface of a substrate; and (b) a step of forming a first wiring layer on the insulating surface. Depositing and forming a first insulating film over the first wiring layer; (c) forming a resist layer overlying the first insulating film; and (d) the first insulating film. And etching back the resist layer at a substantially constant rate to leave a portion of the first insulating film on the first wiring layer and leave a portion of the resist layer adjacent to the remaining portion. And the process of
(E) removing the remaining portion of the resist layer,
(F) a step of forming a coating insulating film so as to cover the remaining portion of the first insulating film after the removing step, and (g) the first insulating film.
Of the remaining insulating film and the coated insulating film are etched back at a substantially constant rate so that a part of the first insulating film remains on the first wiring layer and the coated insulating film is removed from the first insulating film. And (h) depositing a second insulating film over the remaining portion of the first insulating film after the etch back step, and (i) From the second insulating film through the remaining portion of the first insulating film, the first insulating film is formed.
Forming a connection hole to reach the wiring layer of
(J) forming a second wiring layer on the second insulating film so as to be connected to the first wiring layer through the connection hole.

[0016]

According to the method of the present invention, since the etchback process using the resist layer is performed before the etchback process using the coating insulating film such as SOG, the coating insulating film such as SOG uses the resist layer. It may be thinly formed corresponding to the wiring steps reduced by the etch back process. By making the coating insulating film thin in this way, it is possible to avoid the occurrence of cracks, reduce the remaining of an unstable film such as SOG, and increase the ratio of a stable film such as silicon oxide to the interlayer film. Therefore, the reliability is improved.

In addition, in the etch-back process using a thin coated insulating film, it is possible to reduce conduction defects and improve flatness even with a small amount of etch-back. improves.

[0018]

1 to 6 show a method of forming a multilayer wiring according to an embodiment of the present invention, and steps (1) to (6) corresponding to the respective drawings will be sequentially described. The same parts as those in FIGS. 7 to 12 are designated by the same reference numerals and detailed description thereof will be omitted.

(1) Insulating film 12 on the surface of semiconductor substrate 10
After the wiring layers 14A and 14B of the first layer are formed thereon, an insulating film 16 of silicon oxide or the like is formed by plasma CVD or the like so as to cover these wiring layers. Then, a photoresist is spin-coated on the insulating film 16, and then a softening treatment is performed as necessary to fluidize the insulating film 16 to form a flat resist layer 24.

(2) Next, the insulating film 16 and the resist layer 2
4 is etched back at a substantially constant speed to form wiring layers 14A and 14B.
Above the upper surface level of the insulating film 16 and the resist layer 24.
Partially remain. Then, the remaining portion of the resist layer 24 is removed by ashing with O ₂ plasma or the like.

(3) Next, S on the remaining portion of the insulating film 16.
OG is spin-coated and annealed, etc. to apply insulating film 2
6 is formed. In this case, since the wiring step of the insulating film 16 is reduced by the etching back process using the resist layer 24, the insulating film 26 may be considerably thinner than the insulating film 18 of FIG.

(4) Next, the insulating films 16 and 26 are etched back at a substantially constant rate to remove the insulating film 26 above the wiring layers 14A and 14B. This is to prevent poor conduction in the connection hole.

(5) Next, an insulating film 28 of silicon oxide or the like is formed by plasma CVD or the like so as to cover the remaining portions of the insulating films 16 and 26. In this case, the insulating film 28 is
Considering that the remaining film thickness of the insulating film 16 on the wiring layers such as 14A and 14B is thinner than that in the case of FIG. 8, the insulating film 16 is formed sufficiently thick so as to obtain a required interlayer film thickness. Then, the insulating film 16 is formed above the wiring layer 14B by a known photolithography process or the like.
And 28, a connection hole CH is formed.

(6) Thereafter, a wiring material is applied to the upper surface of the substrate and patterned to form the second wiring layer 30. The wiring layer 30 has the wiring layer 14 via the connection hole CH.
Connected to B.

According to the above-described method for forming a multilayer wiring, the insulating film 26 formed in the step of FIG. 3 is thin, so that the insulating film 26 is hardly cracked. Further, in the process of FIG. 4, the insulating film 26 can be eliminated above the wiring layer such as 14B with a small amount of etch back, so that good flatness can be obtained. Further, in the interlayer film formed by the insulating films 16, 26 and 28, the unstable film 26 such as SOG hardly remains, and the stable film 16 such as silicon oxide is stable.
Since the ratio of 28 is large, the reliability of the wiring is improved.

[0026]

As described above, according to the present invention, the etchback process using the resist layer is followed by the etchback process using the coating insulating film such as SOG.
Since the remaining of the unstable coating such as G is reduced and the flatness is improved, the effect that the highly reliable multilayer wiring can be formed with a high yield can be obtained.

[Brief description of drawings]

[Figure 1]

FIG. 6 is a substrate cross-sectional view showing a method for forming a multilayer wiring according to an embodiment of the present invention.

[Figure 7] ~

FIG. 9 is a substrate cross-sectional view showing an example of a conventional multilayer wiring forming method.

10]

FIG. 12 is a cross-sectional view of a substrate showing another conventional example.

FIG. 13 is a substrate cross-sectional view taken along the line XX ′ of FIG.

[Explanation of symbols]

10: semiconductor substrate, 12, 16, 28: insulating film, 14
A, 14B, 30: wiring layer, 24: resist layer, 26:
Coating insulation film.

Claims (1)

[Claims] 1. A step of: (a) forming a first wiring layer on an insulating surface of a substrate; and (b) a first insulating layer covering the first wiring layer on the insulating surface. A step of depositing and forming a film; (c) a step of forming a resist layer overlying the first insulating film; and (d) etching back the first insulating film and the resist layer at a substantially constant rate. A part of the first insulating film is used as the first
Of the remaining resist layer adjacent to the remaining portion of the wiring layer, and (e) removing the remaining portion of the resist layer; and (f) removing the remaining portion of the resist layer. A step of forming a coated insulating film so as to cover the remaining portion of the first insulating film, and (g) etching back the remaining portion of the first insulating film and the coated insulating film at a substantially constant rate. A step of leaving a part of the first insulating film on the first wiring layer and removing the coated insulating film above the first wiring layer, and (h) after this etch back step A step of depositing and forming a second insulating film so as to cover the remaining portion of the first insulating film, and (i) the first insulating film via the remaining portion of the first insulating film. Forming a connection hole so as to reach the wiring layer of (1), and (j) the first hole through the connection hole. Multi-layer wiring forming method and forming a second wiring layer on the second insulating film to be connected to the wiring layer.