JP2623459B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, for example, to a technology effective when used in a dual-port memory or the like constituting an image memory of an image processing system. Things.

[Conventional technology]

Random access port and serial access
There is a dual-port memory with ports.
Also, there is an image memory (image frame buffer memory) for displaying a CRT (cathode ray tube) display of characters or figures, for example, by combining a plurality of such dual port memories. Further, there is an image processing system including such an image memory, a bitmap processor, a CRT display, and the like.

The random and serial access ports of such dual-port memories include:
For example, a 4-bit data input / output terminal is provided.

The dual port memory is described in, for example, "Nikkei Electronics", March 24, 1986, pp. 243 to 264, published by Nikkei McGraw-Hill.

[Problems to be solved by the invention]

Prior to the present invention, the present inventors have developed an image processing system as shown in FIG. In the figure, the image processing system has a bit
It includes a map processor BMP and a pixel data controller PDC that performs a coloring process on image data output from the bit map processor BMP, for example, in 32-bit units. The image data coloring process by the pixel data controller PDC is performed by setting the logical “0” level or the logical “1” level of the image data of each bit to 4 in advance.
This is performed by code conversion into bit color codes. Therefore, the pixel data controller PDC includes two color code registers corresponding to the logic “0” level and the logic “1” level of the image data,
A data selection circuit is provided for selectively transmitting the color codes held in the two color code registers to the image memory according to the logical level of the image data of each bit.

Image data colored by the pixel data controller PDC is stored in the image memory VRAM. The image memory VRAM includes, for example, 32 dual port memories DPM1 to DPM32. Dual port
The memories DPM1 to DPM32 are a random access port that writes image data randomly to specified addresses in 4-bit units, and a serial access that reads these image data and outputs them serially in 4-bit units corresponding to color codes・ Has a port.

The image data output from the dual port memories DPM1 to DPM32 is temporarily stored in the shift register SR and then sent to the color palette CP at a speed according to the data rate of the CRT display. The color palette CP decodes 4-bit image data sent from the shift register SR in accordance with a color code, and then supplies the analog image signal including a color signal to a CRT display.

However, it has been clarified by the inventors of the present application that the above-described image processing system further has the following problems. That is, in the image processing system shown in FIG.
This is performed by a pixel data controller PDC provided outside the VRAM. Also, the random access memory of the dual port memory that constitutes the image memory VRAM
Port and serial access port, for example, 4
The same number of data input / output terminals are provided for each bit. For this reason, the bit width of the data bus provided between the pixel data controller PDC and the image memory VRAM is increased to four times the bit width of the original image data, and 32 The result is that as many dual port memories are required. This not only increases the physical amount of the signal cable provided between the pixel data controller PDC and the image memory VRAM and the required number of bits of the shift register SR, but also increases the image memory
This causes a reduction in the use efficiency of the VRAM memory area. As a result, the mounting efficiency of the image processing system including the image memory VRAM is reduced, and cost reduction is prevented.
Also, the coloring process for the image data is performed in the image memory VRAM.
Pixel data controller PD provided outside
Since it is executed via C, the memory cycle of the bit map processor BMP cannot be sped up as desired, and the processing capacity of the image processing system is limited.

An object of the present invention is to provide a dual port memory having a new function. It is another object of the present invention to simplify and reduce the cost of an image processing system or the like including a dual port memory.

The above and other objects and novel features of the present invention will become apparent from the foregoing description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative embodiment among the embodiments disclosed in the present application will be briefly described as follows. That is, the random access memory of the dual port memory
The first and second code registers respectively corresponding to the logic “0” level and the logic “1” level of the input data, and the color code held in the first or second code register are input to the port. A data selection circuit for selectively transmitting the data to the write circuit according to the logic level is provided.

[Action]

According to the above means, since the coloring process for the image data can be executed at the random access port of the dual port memory, the bit width of the data bus provided between the pixel data controller and the image memory can be reduced. At the same time, the number of dual-port memories constituting the image memory can be reduced and the mounting efficiency thereof can be increased, so that the image processing system can be simplified and the cost can be reduced.

〔Example〕

FIG. 5 is a block diagram showing an embodiment of an image processing system including an image memory VRAM constituted by a dual port memory to which the present invention is applied.

In the image processing system of this embodiment, the image memory
The serial port of the dual port memory that constitutes VRAM
The access port is provided with four data input / output terminals (second external terminals), and the random access port is provided with eight data input / output terminals (first external terminals). Each of these dual-port memories has a function of performing a coloring process on 8-bit image data supplied from the bit map processor BMP using a predetermined color code. For this reason, the data bus provided between the pixel data controller PDC and the image memory VRAM has 32 bits, and the image memory VRAM includes four dual-port memories DPM1 to DPM4.

In FIG. 5, the image processing system is controlled by a bit map processor BMP. The bit map processor BMP is, but not limited to, a processor of a stored program type using a microprogram. Although not particularly limited, the bit map processor BMP processes image data to be displayed on a CRT display in 32-bit units.

The bit map processor BMP is coupled to the pixel data controller PDC via a system bus. This system bus includes a 32-bit data bus,
An address bus and a control bus (not shown) are included.

The pixel data controller PDC controls access to the image memory VRAM by the bit map processor BMP and coloring of image data. The functions of these pixel data controllers PDC may be substituted by a normal memory control unit.
As shown in FIG. 5, a bit map processor
Image data output from the BMP in 32-bit units is transmitted to the image memory VRAM with the same bit width.

Although not particularly limited, the image memory VRAM includes four dual-port memories DPM1 to DPM4.
These dual-port memories are supplied with 8-bit image data corresponding to the 32-bit image data. Dual port memory DPM1 to DP
M4, as described later,
It has a port and a serial access port. As described above, the random access ports of these dual port memories have a function of performing a coloring process. In other words, the random access port of each dual port memory is the first access port provided corresponding to the logical "0" level and the logical "1" level of the image data.
And second color code registers CR0 and CR1 (see FIG. 1). Also, eight data selection circuits SEL1 to SEL8 provided corresponding to each of the 8-bit image data.
(See FIG. 1). These data selection circuits selectively transmit the color code held in the corresponding color code register CR0 or CR1 to the corresponding writing circuit according to the logic level of the corresponding image data. As a result, the image data of each bit is code-converted as a 4-bit color code, and written to a designated address of the memory array.

On the other hand, as described later, the serial access ports of the dual-port memories DPM1 to DPM4 sequentially and simultaneously store stored data of 32-bit memory cells corresponding to eight image data starting from a designated address. After reading, the stored data corresponding to the eight pieces of image data are serially output in 4-bit units. Storage data output from the serial access port of each dual port memory is supplied to a shift register SR provided outside the image memory VRAM.

Although the shift register SR is not particularly limited,
Includes two sets of 16-bit shift registers. The image data output from the dual port memories DPM1 to DPM4 is first loaded into the first shift register in accordance with the access time of the dual port memory,
To the shift register. The image data sent to the second shift register is further serially transmitted to the color palette CP in 4-bit units according to the data rate of the CRT display.

The color palette CP decodes 4-bit image data supplied from the shift register SR according to a color code and converts the image data into an analog signal including a color signal. These analog signals are supplied to a CRT display, and a display image of 16 colors is formed.

FIG. 2 is a block diagram showing one embodiment of the dual port memory DPM1 constituting the image memory VRAM of FIG. Other dual memory that constitutes image memory VRAM
The port memories DPM2 to DPM4 have the same configuration as the dual port memory DPM1 in FIG. The circuit elements constituting each block of the dual-port memories DPM1 to DPM4 are each formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known semiconductor integrated circuit manufacturing technique. .

Although not particularly limited, the dual-port memory DPM1 of this embodiment has eight memory arrays M-AR each.
Y1 to M-ARY8 are provided, and a random access port and a serial access port are provided across these memory arrays.

The random access port of the dual port memory DPM1 further has the above-mentioned eight memory arrays M-ARY1
Sense amplifiers SA1 to SA8 and column switches CSW1 to CSW8 are provided corresponding to .about.M-ARY8. Also, a random access memory is commonly used for the memory arrays M-ARY1 to M-ARY8.
A port column address decoder RCD and a row address decoder RD are provided. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. However, in order to avoid complicating the drawing, FIG. 2 exemplarily shows a memory array M-ARY1 and peripheral circuits corresponding thereto, and the memory arrays M-ARY2 to M-ARY8 are shown in FIG. Not shown.

Eight data input / output terminals IO1 to IO8 (first data input / output terminals) are connected to the random access port of the dual port memory DPM1.
Corresponding to these data input / output terminals, a total of 32 sets of complementary common data lines C D0 -C 4
D3 to C D28~ C D31 (where, for example, non-inverted signal line CD
Complementary data line by combining 0 and inverted signal line ▲ ▼
Expressed as C D0. The same applies hereinafter). Complementary common data line C D0-C D3 is coupled to the memory array M-ARY1 through the corresponding column switch CSW1. Similarly, the complementary common data line C D4~ C D7 to C D28~ C D31 are respectively coupled to the memory array M-ARY2~M-ARY8 through the column switch CSW2~CSW8 that corresponding.

The random access port of the dual port memory DPM1 of this embodiment is a bit map processor.
It has a function to perform coloring processing on image data supplied from the BMP. That is, the random input / output circuit RIO of the random access port has a color code register corresponding to the logical "0" level and the logical "1" level of the image data, as will be apparent from FIG. CR0
(First code register) and CR1 (second code register). Also, eight data selection circuits SEL1 to SEL8 corresponding to each image data, that is, each memory array.
Is provided. The data selection circuits SEL1 to SEL8 select the color code held in the color code register CR0 or CR1 according to the logical level of the image data of the corresponding bit, and transmit it to the corresponding write amplifiers WA1 to WA8. Thereby, each image data is code-converted into a 4-bit color code according to the logical level.

The color codes held in the color code registers CR0 and CR1 are rewritten by executing the color code register set mode.

In FIG. 2, a memory array M-ARY1 has m + 1 word lines arranged in the vertical direction in the figure, n + 1 sets of complementary data lines arranged in the horizontal direction in the figure, and these word lines and complementary data. (M + 1) × placed at the intersection of the lines
It is composed of (n + 1) dynamic memory cells.

Although each memory cell is not particularly limited, an information storage capacitor and an N-channel type address selection MO are provided.
It is composed of SFET. For address selection of n + 1 memory cells arranged in the same row of the memory array M-ARY1
MOSFET gates are commonly coupled to corresponding word lines. The drains of the address selection MOSFETs of the (m + 1) memory cells arranged in the same column of the memory array M-ARY1 are alternately provided as input / output nodes of the memory cells to corresponding complementary data lines with a predetermined regularity. Be combined.

Each word line constituting the memory array M-ARY1 is coupled to a row address decoder RD, and one of the word lines designated by the X address signals AX0 to AXi is selectively set to a high level. .

The row address decoder RD is provided with a row address buffer RA.
Complementary internal address signals a x0 to a xi supplied from DB (here, for example, the non-inverted internal address signal ax0 and the inverted internal address signal
expressed as a x0. The same applies hereinafter), and one designated word line is set to a high-level selected state. The operation of selecting a word line by the row address decoder RD is performed in synchronization with the high level of the word line selection timing signal φx supplied from the timing control circuit TC.

The row address buffer RADB receives a row address signal supplied from the address multiplexer AMX, forming the complementary internal address signals a x0~ a xi, supplied to the row address decoder RD.

The dual port memory DPM1 of this embodiment includes, but not limited to, an X address signal AX0 to AXi for specifying a row address and a Y address signal for specifying a column address.
A so-called address multiplex system in which AY0 to AYi are supplied in a time-division manner via the same external terminals A0 to Ai is adopted. That is, the X address signals AX0 to AXi are supplied to the external terminals A0 to Ai in synchronization with the fall of the row address strobe signal ▲, and the Y address signals are synchronized with the fall of the column address strobe signal ▼.
AY0 to AYi are supplied. In addition, the dual
The port memory DPM1 is provided with an automatic refresh mode for reading / rewriting data stored in a memory cell within a predetermined cycle, and a refresh address for sequentially specifying a word line to be refreshed in this automatic refresh mode. A counter PEFC is provided. Further, an address multiplexer for selectively transmitting the refresh address signals rx0 to rxi or the X address signals AX0 to AXi formed by the refresh address counter REFC to the row address buffer RADB.
AMX is provided.

The address multiplexer AMX has a timing control circuit T
In a normal memory access mode in which the timing signal φref supplied from C is at a low level, the external terminal A0
AX0 to AXi supplied through .Ai to Ai, and a row address buffer RADB as a row address signal.
To communicate. Further, in the automatic refresh mode in which the timing signal φref is set to the high level, the refresh address signals rx0 to rxi output from the refresh address counter REFC are selected and transmitted to the row address buffer RADB as row address signals.

The refresh address counter REFC is incremented in accordance with the timing signal φrc supplied from the timing control circuit TC, so that the refresh address signal
rx0 to rxi are formed. These refresh address signals rx0 to rxi are selectively transmitted to the row address buffer RADB via the address multiplexer AMX.

As described above, the X address signals AX0 to AXi are supplied in synchronization with the fall of the row address strobe signal ▼. Therefore, the acquisition of the row address signal by the row address buffer RADB is performed by the timing control circuit TC.
At a timing signal φar (not shown) formed by detecting the fall of the row address strobe signal ▲.

On the other hand, the complementary data lines constituting the memory array M-ARY1 are divided into four groups, although not particularly limited. On one side, these complementary data lines are coupled to the corresponding switch MOSFETs of the column switch CSW1, and four groups are simultaneously selected in each group.

The column switch CSW1 is configured by n + 1 pairs of switch MOSFETs. One terminal of the switch MOSFET is coupled to the corresponding complementary data lines, the other terminal is commonly connected to a complementary common data line C D0~ C D3. These switch MOSFETs are divided into groups of four sets corresponding to the complementary data lines. The gates of the four sets of switch MOSFETs forming each group are commonly connected, and the corresponding data line group selection signals G0 to Gq are supplied from the random access port column address decoder RCD. As a result, the column switch CSW1 is
Selectively coupling the set of complementary data lines and the common complementary data lines C D0~ C D3.

The column address decoder RCD for the random access port is supplied with complementary internal address signals a y0 to a yi from the column address buffer CADB and the timing signal φyr from the timing control circuit TC. The timing signal φyr is normally at a low level, and is at a high level when the dual port memory DPM1 is set to the selected state in the random access mode and the data line selecting operation can be started. The random access port column address decoder RCD decodes the complementary internal address signals a y0 to a yi supplied from the column address buffer CADB, and outputs the corresponding data line group selection signals G0 to Gq according to the timing signal φyr. Alternatively, it is set to the high level.

Column address buffer CADB is a timing control circuit
In accordance with a timing signal φac (not shown) supplied from the TC, Y address signals AY0 to AYi supplied via external terminals A0 to Ai are taken in and held. Also, based on these Y address signals AY0 to AYi, the complementary internal address signal
a y0~ a yi is formed, and supplies the column address decoder RCD for random access port. These complementary internal address signals a y0 to a yi are also supplied to a serial access port column address decoder SCD described later.

On the other side, the complementary data lines constituting the memory array M-ARY1 are coupled to the corresponding unit amplifier circuit of the sense amplifier SA1, and further coupled to the corresponding unit circuit of the data register DR1 provided in the serial access port. You.

Although each unit amplifier circuit of the sense amplifier SA1 is not particularly limited, its basic configuration is a latch composed of two sets of CMOS inverter circuits that are cross-connected. These unit amplifier circuits are simultaneously activated according to a timing signal φpa supplied from the timing control circuit TC. In this operating state, each unit amplifier circuit amplifies the minute read signal output from the selected memory cell to the corresponding complementary data line, and converts it into a high level / low level binary read signal.

Complementary common level line C D0-C D3 are random output circuit
Combined with RIO. The random output circuit RIO, to no complementary common data line C D4~ C D7 is provided corresponding to the other memory array M-ARY2~M-ARY8 C D28~ C D31 are coupled in the same manner.

The random input / output circuit RIO includes data amplifiers DA1 to DA8 provided corresponding to the memory arrays M-ARY1 to M-ARY8, as described later. In addition, these data amplifiers DA
Color code register commonly provided for 1 to DA8
It includes CR0 and CR1, a mask register MR, a data input buffer DIB, and a data output buffer DOB. The timing signal φcs is supplied from the timing control circuit TC to the color code registers CR0 and CR1. The timing signal φms is supplied from the timing control circuit TC to the mask register MR.

The data amplifiers DA1 to DA8 are provided with corresponding data selection circuits SEL1 to SEL8 and line amplifiers WA1 to WA.
A8 and read amplifiers RA1 to RA8 are included. Among them, the timing signal φwr supplied from the timing control circuit TC is selectively supplied to the write amplifiers WA1 to WA8 according to the mask data held in the corresponding bits of the mask register MR.

The specific configuration and operation of the random input / output circuit RIO will be described later in detail.

On the other hand, the serial access ports of the dual-port memory of this embodiment correspond to the eight memory arrays M
Data registers provided corresponding to -ARY1 to M-ARY8
DR1 to DR8, data selectors DSL1 to DSL8, a pointer PNT provided commonly to these data registers and data selectors, a column address decoder SCD for a serial access port, and a serial input / output circuit SIO. A plurality of pointers PNT and serial access port column address decoders SCD may be provided depending on the arrangement of the memory array on the semiconductor substrate. Second
In the figure, a data register DR1 and a data selector DSL1 corresponding to the memory array M-ARY1 are exemplarily shown.

The serial port of the dual port memory of this embodiment is
The access port is not particularly limited, four data input terminals SIO1~SIO4 is provided, 32 sets of serial input-output complementary common data in a manner corresponding to the complementary common data line C D0-C D31 Lines C DS0 to C DS31 are provided. These serial input / output complementary common data lines C DS0 to C DS3
1 is divided into four sets each, and coupled to the corresponding memory arrays M-ARY1 to M-ARY8 via the corresponding data selectors DSL1 to DSL8 and the data registers DR1 to DR8, respectively. In addition, complementary common data line C DS for serial input / output
0 to C DS31 is divided in other forms eight pairs respectively associated with the data input-output terminal SIO1～SIO4. That is, the first serial input / output complementary common data lines C DS0, C DS4... C DS28 coupled to each memory array are associated with the data input / output terminal SIO1. Similarly, the second through fourth serial input / output complementary common data lines C DS1, C DS5... C DS29 through C DS coupled to each memory array
3, C DS7 ... C DS31 are data input / output terminals SIOO2
~ SIO4.

The dual port memory DPM1 of this embodiment has a serial clock signal SE and an external shift register SR.
SC is supplied, and timing signals φse and φsc are formed according to these serial clock signals. this house,
The frequency of the serial clock signal SE, that is, the timing signal φse is 1/8 of the frequency of the serial clock signal SC, that is, the timing signal φsc. The serial input / output circuit SIO of the serial access port is provided with an 8-bit shift register corresponding to each of the data input / output terminals SIO1 to SIO4. These shift registers, according to the timing signal .phi.SE, corresponding first to fourth serial input-output complementary common data lines C D coupled to the memory array
0, C D4 ··· C D28 to C D3, C D7 ··· 8-bit memory data output via the C D31 is captured. These stored data are sequentially sent out to the shift register SR four bits at a time in accordance with the timing signal φsc. In other words, the four sets of shift registers provided in the serial input / output circuit SIO perform serial-to-parallel conversion on storage data output in parallel via the corresponding eight sets of serial input / output complementary common data lines. Input / output terminals SIO1 ~
It has the function to transmit serially to SIO4.

In FIG. 2, a data register DR1 includes n + provided corresponding to each complementary data line of the memory array M-ARY1.
Includes one latch. These latches are each divided into four groups. The input / output node of each latch has, on one side, n + 1 pairs of switch MOSFETs for data transfer.
Via the corresponding complementary data lines of the memory array M-ARY1. The gates of these switch MOSFETs are all connected in common, and a timing signal φtr for data transfer is supplied from the timing control circuit TC. The timing signal φtr is normally set to the low level, and when the dual port memory is set to the selected state in the read data transfer cycle and the read signal output from the selected memory cell is established on the corresponding complementary data line, High level temporarily. Data register DR
The switch MOSFET for data transfer 1 is the timing signal φt
When r is temporarily set to a high level, all of them are simultaneously turned on. As a result, the storage data read from the (n + 1) memory cells coupled to the selected word line is simultaneously transferred to the data register DR1.

The n + 1 latches constituting the data register DR1 are:
On the other side, it is coupled to the corresponding switch MOSFET of data selector DSL1. These switch MOSFETs
Similarly, each group is divided into four groups. Each group consists of switches
MOSFET of the other, are commonly coupled to a corresponding serial input-output complementary common data line C DS1~ C DS4. The gates of four sets of switch MOSFETs constituting each group are connected in common, and a corresponding group selection signal is supplied from the pointer PNT. As a result, the data selector DSL1
Data register DR1 according to the group selection signal supplied from T
Select the four sets of latches from, it has a function of selectively connecting the serial input-output complementary common data line C DS0~ C DS3.

The pointer PNT is a complementary data line and a data selector DSL.
It includes an (n + 1) / 4-bit shift register and an address latch provided corresponding to each data line group obtained by dividing one switch MOSFET.

The output signal sb of the last bit of the shift register of the pointer PNT is supplied to the input terminal of the first bit. The pointer PNT shift register includes a timing control circuit TC.
Supplies a shift clock timing signal φse. This timing signal φse is formed according to the above-described serial clock signal SE. The shift register of the pointer PNT performs a loop-shaped shift operation in accordance with the timing signal φse, and sequentially forms the group selection signal. These group selection signals are respectively supplied to the commonly connected gates of the four sets of switch MOSFETs of the corresponding group of the data selector DSL1.

Each bit of the shift register of the pointer PNT is further coupled to a corresponding bit of the address latch of the pointer PNT via a corresponding switch MOSFET. The gates of these switch MOSFETs are all commonly connected, and a timing signal φps is supplied from the timing control circuit TC. This timing signal φps sets the dual port memory to a selected state in a read data transfer cycle,
Column address decoder for serial access port
When the decoding operation of the column address by the SCD is completed and the data transfer control signal 信号 / ▲ is returned from the low level to the high level, the signal is temporarily set to the high level. These switch MOSFETs in the pointer PNT are:
When the timing signal φps is temporarily set to the high level, they are simultaneously turned on. This allows the pointer PNT
The selection signal of logic “1” held in the address latch of
The corresponding bit of the shift register of the pointer PNT is set as a shift signal.

The input / output node of each bit of the address latch of the pointer PNT is further connected to the corresponding output of the serial access port column address decoder SCD decoder via the corresponding switch MOSFET of the serial access port column address decoder SCD. Connected to each terminal. The gates of these switch MOSFETs are all connected in common, and a timing signal φ
ys is supplied. The timing signal φys is temporarily set to the high level when the dual port memory is set to the selected state in the read data transfer cycle and the column address decoding operation by the serial access port column address decoder SCD is completed. You.

The switch MOSFETs of the serial access port column address decoder SCD are simultaneously turned on when the timing signal φys is set to the high level. As a result, the selection signal of logic "1" is input to the bit specified by the Y address signals AY0 to AYi of the address latch of the pointer PNT.

Complementary internal address signals a y0 to a yi are supplied from the column address buffer CADB to the serial access port column address decoder SCD. The column address decoder SCD for serial access port decodes these complementary internal address signals a y0 to a yi and selects an output signal corresponding to a set of data lines specified by the Y address signals AY0 to AYi. It is always set to high level.

As described above, this high-level output signal is taken into the corresponding bit of the address latch of the pointer PNT by temporarily setting the timing signal φys to the high level, and the timing signal φps is temporarily set to the high level. As a result, the corresponding bit of the pointer PNT is set as a logical "1" shift signal. Pointer
The shift signal set in the shift register of the PNT is not particularly limited, but is shifted in a loop in the pointer PNT in synchronization with the rising edge of the timing signal φse.

That is, in the serial output operation mode of the serial access port of the dual port memory, the first data line group to be selected is the complementary internal address signal a y0
Specified by ~ a yi (Y address signal AY0~AYi). These complementary internal address signals a y0 to a yi are decoded by the serial access port column address decoder SCD, and the result is set to the corresponding bit of the address latch of the pointer PNT according to the timing signal φys by the selection signal of logic “1”. Is entered as This selection signal is input to a corresponding bit of the shift register of the pointer PNT when the timing signal φps is temporarily set to the high level, and is used as a shift signal.

When the serial output operation of the stored data is started, the timing register φse for the shift clock is supplied to the shift register of the pointer PNT. The shift signal of logic "1" set in the designated bit of the pointer PNT is shifted in a loop in the pointer PNT in synchronization with the rising edge of the timing signal φse, and the group selection signals are sequentially formed. As a result, the four sets of switch MOSFETs of the data selector DSL1 are sequentially turned on, and the complementary common data line for serial input / output in which each bit of the data register DR1 sequentially corresponds from the 4 bits corresponding to the head data line group.
C DS0 to C DS3 are connected in 4-bit units. The stored data output via the serial input / output complementary common data lines C DS0 to C DS3 is taken into the corresponding shift register of the serial input / output circuit SIO according to the timing signal φse.

The complementary common data lines C DS0 to C DS3 for serial input / output are
Coupled to the serial input / output circuit SIO. This serial input / output circuit SIO includes other memory arrays M-ARY2 to M-ARY.
It is no serial input-output complementary common data line C DS4~ C DS7 provided corresponding to 8 C DS28~ C DS31 is similarly coupled.

Serial input-output circuit SIO has four sets of data provided and 32 sets of main amplifiers provided corresponding to the serial input-output complementary common data line C DS0~ C DS31, in response to the serial input-output terminal SIO1~SIO4 Includes output buffer. The four shift registers of 8 bits are provided between the main amplifier and the data output buffer. These shift registers are provided with the timing signals φse and φsc from the timing control circuit TC.
Is supplied. Further, the timing signal φrs is commonly supplied from the timing control circuit TC to the data output buffer of the serial input / output circuit SIO. The timing signal φsc is a serial clock signal supplied from the outside.
Formed according to SC. The timing signal φrs is
Normally, it is set to low level, and selectively set to high level when the dual port memory is set to the serial output mode.

When dual-port memory is a serial output mode, for serial input and output complementary common data line C D0-C
The read data output from the DS31 via the corresponding main amplifier is taken into the corresponding shift register of the serial input / output circuit SIO according to the timing signal φse,
Will be retained. These read data are sequentially transmitted to the corresponding data output buffers according to the timing signal φsc. The data input buffer of the serial input / output circuit SIO is selectively activated by setting the timing signal φrs to high level. In this operation state, each data output buffer of the serial input / output circuit SIO sends out the read data output from the corresponding shift register serially via the corresponding serial input / output terminals SIO1 to SIO4.

The timing control circuit TC includes a row address strobe signal ▲ ▼, a column address strobe signal ▲ ▼, a write enable signal ▲ ▼, and a data transfer control signal ▲ ▼ / ▲ which are supplied as control signals from the outside.
The various timing signals described above are formed on the basis of ▼, the serial output control signal ▲ ▼, and the color code register set signal ▲ ▼, and are supplied to each circuit. Further, the timing control circuit TC forms timing signals φse and φsc based on the serial clock signals SE and SC supplied from the outside, and supplies them to the pointer PNT and the serial input / output circuit SIO.

FIG. 1 shows the dual port memory DPM1 shown in FIG.
1 is a circuit block diagram of one embodiment of the random input / output circuit RIO.

Although not particularly limited, the dual-port memory of this embodiment includes data amplifiers DA1 to DA8 provided corresponding to the memory arrays M-ARY1 to M-ARY8, and a color code register CR0 commonly provided for each data amplifier. And CR1, a mask register MR, a data input buffer DIB, and a data output buffer DOB. The data amplifiers DA1 to DA8 are write amplifiers WA1 to WA8, read amplifiers RA1 to RA8, and a data selection circuit SEL1 provided corresponding to each write amplifier.
To SEL8.

As described above, the random access port of the dual port memory in this embodiment is a bit mapped
Processor BMP to Pixel Data Controller PDC
And a function of performing a coloring process on image data supplied via the data input / output terminals IO1 to IO8. This coloring process is performed by the write amplifiers WA1 to WA8 provided corresponding to the memory arrays M-ARY1 to M-ARY8 and the data selection circuit SE.
L1 to SEL8 and color code registers CR0 and CR1 provided commonly to these write amplifiers and data selection circuits. The write operation of the image data is not particularly limited, but is selectively performed in accordance with the mask data held in each bit of the mask register MR similarly provided. The random access port has a function of randomly reading stored data stored at a specified address.

In FIG. 1, data input / output terminals IO1 to IO8 are respectively coupled to input terminals of corresponding bits of a data input buffer DIB of a random input / output circuit RIO. These data input / output terminals are further connected to the random input / output circuit RIO
Of the data output buffer DOB (not shown).

The data input buffer DIB is connected to the data input / output terminal I via the data bus from the pixel data controller PDC.
After receiving various data supplied to O1 to IO8 and adjusting their signal waveforms, the signals are transmitted to each circuit as logic level internal signals.

The output terminal of each bit of the data input buffer DIB is coupled to the input terminal of the corresponding bit of the mask register MR and to the control terminal of the data selection circuit SEL1 to SEL8 of the corresponding data amplifier DA1 to DA8. The output terminals of the first to fourth bits of the data input buffer DIB are
It is coupled to the input terminals of the first to fourth bits of the color code register CR0. Similarly, the output terminals of the fifth to eighth bits of the data input buffer DIB are connected to the color code register CR.
It is coupled to the input terminals of the first to fourth bits. The timing signal φms is supplied from the timing control circuit TC to the mask register MR. Also, the color code register CR
0 and CR1 are supplied with a timing signal φcs from the timing control circuit TC.

Data input / output terminals IO1 to IO8 have dual port
Various data are input / output according to the operation mode of the memory. That is, the color code register set signal ▲
▼ is set to low level and dual port memory DP
When M1 is a color code set mode, the data input-output terminal IO1~IO4 color code c0 _L -C3 _L is supplied which corresponds to the logic "0" level of the image data. These color codes c0 _{L to} c3 _L are captured and held in the color code register CR0 according to the timing signal φcs. At this time, the data input-output terminal IO5~IO8 a color code c0 _H -C3 _H corresponding to a logical "1" level of the image data is supplied. These color codes c0 _H -C3 _H is taken into color code register CR1 according to the timing signal Faics, it is held.

On the other hand, when the dual-port memory DPM1 is in the normal random write operation mode, the data input / output terminal IO
Image data d1 to d8 are supplied to 1 to IO8. These image data d1 to d8 correspond to corresponding data selection circuits SEL1 to SE
It is supplied to L8 as a selection control signal. At this time, the output terminal of the data selection circuit SEL1~SEL8 a color code c0 _L -C3 _L or c0 _H -C3 _H is selectively output in accordance with the logical level of the image data. These output signals are supplied as write data wd0 to wd31 to the corresponding write amplifiers WA1 to WA8. In this random write operation mode, when the write enable signal ▼ is temporarily set to the low level prior to the row address strobe signal ▼, the write operation at the random access port of the dual port memory is selectively performed according to the mask data. Is executed. At this time, the data input / output terminals IO1 to IO8 are supplied with the row address strobe signal ▲
Synchronize with the falling edge of ▼, the mask data m1 to m8
Is supplied. These mask data m1 to m8 are fetched and held in corresponding bits of the mask register MR according to the timing signal φms.

Color code c held in color code register CR0
0 _L ~c3 _L, the data selection circuit SEL of data amplifier DA1~DA8
1 to SEL8 are commonly supplied to one input terminal. Similarly, the color code c0 _H -C3 _H held in the color code register CR1, the data selection circuit of the data amplifier DA1~DA8
The signals are commonly supplied to the other input terminals of SEL1 to SEL8.

Data selection circuits SEL1 to SEL8 for data amplifiers DA1 to DA8
Is, according to the logic level of the corresponding image data d1 to d8,
The above color codes c0 _{L to} c3 _L or c0 _{H to} c3 _H are selected, and the corresponding write amplifiers WA1 to WA3 as write data wd0 to wd31.
Communicate to WA8. That is, bit map processor B
The 8-bit image data supplied from the MP is converted into 4-bit color codes by the data selection circuits SEL1 to SEL8, respectively, and the 32-bit write data wd0 to w
d31 is formed.

The output terminals of each bit of the data selection circuits SEL1 to SEL8 are
It is coupled to the input terminal of the corresponding bit of the corresponding write amplifier WA1 to WA8. Control terminals of these write amplifiers WA1 to WA8 are coupled to output terminals of corresponding AND gate circuits AG1 to AG8.

A timing signal φwr is commonly supplied from the timing control circuit TC to one of the input terminals of the AND gate circuits AG1 to AG8. The timing signal φwr is in accordance with the write enable signal ▲ ▼ when the dual port memory DPM1 is selected in the random write operation mode and the complementary data line selection operation by the random access port column address decode RCD is completed. High level temporarily. The other input terminals of the AND gate circuits AG1 to AG8 are supplied with inverted output signals of the corresponding bits of the mask register MR, respectively. Mask register MR
The mask data m1 to m8 held in are not particularly limited, but are selectively set to a high level when it is desired to mask the write operation in the corresponding write amplifiers WA1 to WA8.
The output signals of the AND gate circuits AG1 to AG8 are selectively output when the timing signal φwr is set to the high level and the inverted signals of the mask data m1 to m8 held in the corresponding bits of the mask register MR are set to the high level. To a high level. The output signals of the AND gate circuits AG1 to AG8 are supplied to the corresponding write amplifiers WA1 to WA8 as write pulses φw1 to φw8 for controlling the write operation, respectively. That is, the AND gate circuits AG1 to AG8 change the timing signal φwr supplied from the timing control circuit TC to the corresponding write amplifier WA1 only when the write operation is not masked by the corresponding mask data m1 to m8.
~ WA8 selectively.

The write amplifiers WA1 to WA8 output the corresponding write pulse φw1
When .about..phi.w8 is set to the high level, it is selectively activated. In this operation state, the write amplifiers WA1 to WA8
The write data wd0 to wd31 supplied from the corresponding data selection circuits SEL1 to SEL8 are used as complementary write signals, and the corresponding complementary common data lines CD0 ・ ▲ to CD3 ・ ▲
Supply to ▼ or CD28 ・ ▲ ▼ ~ CD31 ・ ▲ ▼. When the write pulses φw1 to φw8 are at a low level, the outputs of the write amplifiers WA1 to WA8 are in a high impedance state.

Complementary common data line CD0 ~ ▲ ▼ ~ CD3 ・ ▲ ▼
Or CD28 • ▲ to CD31 • ▲ ▼ are commonly coupled to the input terminals of the read amplifiers RA1 to RA8 of the corresponding data amplifiers DA1 to DA8, respectively. When the dual-port memory DPM1 is set to the random read operation mode, the read signals output from the selected memory cells via these complementary common data lines are amplified by the corresponding read amplifiers RA1 to RA8. These read signals are further sent to a data output buffer DOB (not shown).

Although not particularly limited, the data output buffer DOB is selectively activated in the random read operation mode of the dual port memory. At this time, the column switch CSW is repeatedly changed from the high level to the low level while the row address strobe signal ▼ is kept at the low level. Data output buffer DOB
Are complementary common data lines CD0 ・ ▲ ▼ ~ CD3 ・ ▲
The 32-bit read data output via ▼ or CD28 / ▲ ▼ to CD31 / ▲ ▼ is transferred from the data input / output terminals IO1 to IO8 to the column address strobe signal ▲.
According to ▼, time-division is transmitted four times.

FIG. 3 shows the dual port memory DPM1 of FIG.
3 is a timing chart of one embodiment of the color code register set mode.

In FIG. 3, the dual port memory is set to the selected state by changing the row address strobe signal ▼ from high level to low level.
At the falling edge of the row address strobe signal ▲ ▼, the color code register set signal ▲
When ▼ is at the low level, the dual port memory is set to the color code register set mode. At this time, a data transfer control signal (not shown)
▼ / ▲ ▼ and serial output control signal ▲ ▼
Both are set to high level. Data input / output terminals IO1 to IO4
The color code c0 _L -C3 _L corresponding to a logical "0" level of the image data is supplied. Similarly, data input / output terminals
The IO5～IO8, color code c0 _H -C3 _H corresponding to a logical "1" level of the image data is supplied.

With a slight delay from the row address strobe signal ロ ウ, the column address strobe signal ▼ changes from high level to low level. At approximately the time when the column address strobe signal ロ ー ブ is at the low level, the write enable signal ▼ is temporarily at the low level.

In the dual port memory DPM1, the timing signal φcs is temporarily set to the high level by setting the write enable signal ▼ to the low level. Thus, in the random input / output circuit RIO of the random access port, the color codes c0 _{L to} c3 _L supplied via the data input / output terminals IO1 to IO4 are stored in the color code register.
Captured and held in CR0. The color code c0 _H -C3 _H supplied through the data input-output terminal IO5~IO8 is taken into the color code register CR1, it is maintained.
These color codes are stored in the color code register CR until the next color code register set mode is executed.
It is held at 0 and CR1.

FIG. 4 shows the dual port memory DPM1 of FIG.
The timing chart of one embodiment of the random write operation mode is shown.

In FIG. 4, the dual port memory DPM1 is
At the falling edge of the row address strobe signal ▲ ▼, the color code register set signal ▲
When ▼, the data transfer control signal ▲ / ▲ ▼, and the serial output control signal ▲ ▼ are set to the high level, the random operation mode is set. At this time, as shown by the dotted line in FIG. 4, when the write enable signal ▼ is temporarily set to the low level prior to the falling change of the row address strobe signal ▼, the dual port memory operates in the mask mode. The write operation is selectively executed according to the mask data m1 to m8.

Prior to the falling transition of the row address strobe signal で, the X address signals AX0 to AXi are supplied to the address input terminals A0 to Ai in a combination designating the row address ra. When the dual-port memory is set to the mask mode, mask data m1 to m8 are supplied to the data input / output terminals IO1 to IO8.

In the dual port memory DPM1, the timing signal φar (not shown) is temporarily set to the high level by setting the row address strobe signal ▲ to the low level, and the X address signals AX0 to AXi are set to the row address buffer.
Imported into RADB. Further, the timing signal φx is set to the high level, and the operation of selecting a word line by the row address decoder RDCR is started. Further, when the dual-port memory DPM1 is set to the mask mode, the timing signal φms is temporarily set to the high level, and the mask data m1 to m8 supplied via the data input / output terminals IO1 to IO8 are stored in the mask register MR. It is taken in. These mask data
m1 to m8 are held in the mask register MR only while the dual port memory is in the selected state.

Next, at a predetermined time after the fall of the row address strobe signal 所 定, the column address strobe signal ▼ changes from high level to low level. Prior to the falling of the column address strobe signal ▲ ▼, the Y address signals AY0 to AYi are applied to the address input terminals A0 to Ai.
Are supplied in a combination that specifies The image data d1 to d8 are supplied to the data input / output terminals IO1 to IO8.

In the dual port memory DPM1, the timing signal φyr is set to the high level by setting the column address strobe signal ▲ to the low level, and the selection operation of the complementary data line by the column address decoder RCD for the random access port is started. You. Thus, each 4-bit memory cell from the memory array M-ARY1~M-ARY8 is selected, the corresponding complementary common data line C D0-
It C D3 without being connected to the C D28~ C D31. Image data d1 to d1 supplied through data input / output terminals IO1 to IO8
d8 is transmitted to the corresponding data selection circuits SEL1 to SEL8 as a selection control signal. Thereby, the color code c0 _{L to} c3 _L or c0 _L held in the color code register CR0 or CR1
_H -C3 _H is selected in accordance with the image data d1~d8 corresponding,
Write amplifier W corresponding to write data wd0 to wd31
A1 to WA8 are supplied respectively.

At the timing when the selection operation of the complementary data line by the random access port column address decoder RCD is completed, the write enable signal ▼ is temporarily set to the low level.

In the dual port memory DPM1, the write enable signal ▲ ▼ is temporarily set to low level,
The timing signal φwr is temporarily set to the high level. As a result, the write pulses φw1 to φw8 are temporarily set to the high level. When the dual port memory is set to the mask mode, these write pulses φw1 to φw8 are selectively formed according to mask data m1 to m8 held in corresponding bits of the mask register MR. Write pulse φ
w1~φw8 By is temporarily high, the corresponding write amplifier WA1~WA8 is an operating state, the complementary write signals in accordance with the write data wd0~wd31 is corresponding complementary common data line C D0- C D3 not supplied all at once to the C D28~ C D31. Thus, a write operation is performed on the selected 32-bit memory cell.

As described above, the random access port of the dual port memory according to the present embodiment has a function of performing a coloring process on image data. For this reason, random
The random input / output circuit RIO of the access port is provided with color code registers CR0 and CR1 corresponding to the logical “0” level and the logical “1” level of the image data. Also,
The color code c0 held in the color code register CR0 or CR1 according to the logical level of the input image data.
Data selection circuit SEL1~SEL8 selectively write amplifier transmit _L -C3 _L or c0 _H -C3 _H is provided. The serial access port of the dual port memory DPM1 has four data input / output terminals SIO1 to SIO4,
The access port is provided with twice, that is, eight data input / output terminals IO1 to IO8. Serial access
The port serial input / output circuit SIO is provided with an 8-bit shift register corresponding to the data input / output terminals SIO1 to SIO4. Stored data read serially from the memory array in 32-bit units is further serial-parallel converted by these shift registers, and sequentially transmitted from the data input / output terminals SIO1 to SIO4 in units of 4 bits corresponding to color codes.

Based on these facts, the dual-port
When a memory is used, an image memory VRAM suitable for an image processing system having a 32-bit data bus can be constituted by four dual-port memories.
Therefore, the data bus provided between the pixel data controller PDC and the image memory VRAM only needs to be 32 bits, and the number of bits of the shift register SR provided outside the image memory VRAM may be 16 bits. As a result, the configuration of the image processing system is significantly simplified and its mounting efficiency is improved, so that the cost of the system can be reduced. Further, the coloring process for the image data can be executed at high speed without passing through the pixel data controller PDC.

As shown in the above-described embodiment, the present invention relates to a dual-port memory constituting an image memory of an image processing system.
When applied to a semiconductor storage device such as a memory, the following effects can be obtained. That is, (1) the logic “0” level and the logic “1” of the input data are applied to the random access port of the dual port memory.
There are provided first and second code registers respectively corresponding to levels, and a data selection circuit for selectively transmitting a color code held in the first or second code register to a writing circuit according to a logic level of input data. As a result, an effect is obtained that the coloring process for the image data required in the image processing system can be executed in the dual port memory.

(2) According to the above item (1), the effect is obtained that the bit width of the data bus provided between the pixel data controller of the image processing system and the image memory VRAM can be reduced.

(3) According to the above item (1), an effect is obtained that the coloring processing in the image processing system can be executed at high speed without the intervention of the pixel data controller PDC.

(4) In the dual port memory of the above item (1), a color register is changed by, for example, providing a multi-bit mask register corresponding to image data and selectively executing a write operation for each bit. The effect is that the background color can be changed without any change.

(5) The number of data input / output terminals provided in the random access port is set to a power of 2 times the number of data input / output terminals provided in the serial access port, and read data is directly input to the serial access port. By providing a shift register for parallel conversion,
The effect is obtained that the data input width of the access port can be expanded and the adaptability to a data bus having a large number of bits can be improved.

(6) According to the above item (5), since the use efficiency of the memory area of the image memory is improved and the timing condition at the time of data transfer is relaxed, the frequency of the serial clock signal is increased to increase the system data rate. The effect that it can be obtained is obtained.

(7) According to the above items (1) to (6), an effect is obtained that the image memory of the image processing system can be constituted by a small number of dual port memories.

(8) The effect of item (7) is that the number of bits of the serial-parallel conversion shift register provided outside the image memory can be reduced.

(9) According to the above items (1) to (8), the configuration of the image processing system can be simplified, its mounting efficiency can be increased, and the cost of the system can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in this embodiment, 16 colors are specified by setting the color code registers CR0 and CR1 to 4 bits. However, as shown by a dotted line in FIG. By allowing arbitrary changes via the pixel data controller PDC, more color designations can also be implemented. It is also possible to provide a plurality of sets of color code registers and switch between them so as to make the color specification more efficient. The memory array can have any configuration by appropriately selecting the number of complementary data lines to be selected at the same time as the number of complementary common data lines. The number of data input / output terminals provided in the random access port and the serial access port can be set arbitrarily. Also, the color code register set signal ▲ ▼ should not be a separate external terminal,
Other external terminals may be shared by a high voltage or a function code. Further, the specific circuit configuration of the random input / output circuit RIO shown in FIG. 1, the block configuration of the dual port memory shown in FIG. 2, and the block configuration of the image processing system shown in FIG. The combination of control signals, address signals, data, and the like shown in FIGS. 3 and 4 can take various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to a dual-port memory used as an image memory, which is an application field serving as a background, has been described. , Dual port used for various other applications
It is applicable to memories and similar multiport memories. The present invention can be widely applied to a semiconductor memory device having at least a random access port and a serial access port, or a digital device incorporating such a semiconductor memory device.

〔The invention's effect〕

The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows. That is, the random port of the dual port memory
The first and second code registers corresponding to the logic “0” level and the logic “1” level of the input data, respectively, and the color code held in the first and second code registers are input to the access port. By providing a data selection circuit that selectively transmits to the write circuit according to the logic level of the data, the coloring process for the image data can be executed at the random access port of the dual port memory. It is possible to simplify and reduce the cost of an image processing system or the like including an image memory.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of a random input / output circuit of a dual port memory to which the present invention is applied. FIG. 2 is a dual port memory including the random input / output circuit of FIG. FIG. 3 is a timing chart showing one embodiment of a color code register set mode of the dual port memory of FIG. 2, and FIG. 4 is a dual port memory of FIG. FIG. 5 is a timing chart showing an embodiment of a random write operation mode of the memory; FIG. 5 is a block diagram showing an embodiment of an image processing system including an image memory constituted by the dual port memory of FIG. FIG. 6 is a block diagram showing an example of an image processing system developed by the present inventors prior to the present invention. RIO: Random input / output circuit, CR0, CR1: Color code register, MR: Mask register, SEL1 to SEL8: Data selection circuit, WA1 to WA8: Write amplifier, RA1 to RA8 ...
Read amplifier, DIB ... Data input buffer, AG1 to AG8
... And gate circuit. DPM1 to DPM8: Dual port memory, M-ARY1 to
M-ARY8 memory array, SA1 to SA8 sense amplifier, CSW1 to CSW8 column switch, RCD column address decoder for random access port, RD
Row address decoders, DR1 to DR8 ... data registers,
DSL1 to DSL8: Data selector, PNT: Pointer, SCD
…… Column address decoder for serial access port, SIO …… Serial I / O circuit, CADB …… Column address buffer, RADB …… Row address buffer, AMX
… Address multiplexer, REFC… Refresh address counter, TC… Timing control circuit. BMP: Bit map processor, PDC: Pixel data controller, VRAM: Image memory, SR:
Shift register, CP ... Color palette, CRT ... CRT display.

Claims (2)

(57) [Claims] In a color code capturing operation, first and second color codes for capturing, as color codes, upper half bits and lower half bits of input data supplied from a plurality of first external terminals, respectively. In the random access operation, the selection signal of the first or second color code register is determined by the logic “0” and the logic “1” of each bit of the input data supplied from the first external terminal. A random access port for forming and storing the color code stored in the color code register specified by the selection signal at a specified address of the memory array; and storing the color code in the memory array in a serial access operation. The read color code is read in parallel to the data register in word line units, and the data A serial access port for serially outputting data held in a register in a bit unit corresponding to the color code via a second external terminal, and a color access port in accordance with a control signal from a plurality of control signal terminals; A semiconductor memory device comprising: a timing control circuit that forms a timing signal for performing a code fetch operation, the random access operation, and the serial access operation. 2. The random access port according to claim 1, further comprising a mask register for taking in, as mask data, input data supplied from said first external terminal in a mask data taking operation, said random access port being stored in said mask register. The write operation of the color code stored in the color register selected by the individual bits of the input data supplied from the first external terminal in the random access operation by each bit of the mask data. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is characterized in that: