JPS6353793A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten time necessary for clearing a memory and to decrease the influence on a display image by simultaneously operating MOSFETs provided between the I/O nodes of flip-flops for data-latching data registers and the power supply and grounding voltages of a circuit. CONSTITUTION:The switch MOSFETs Q13, Q14, Q15, and Q16 to receive a timing signal phic1 for clearing a memory, are provided between the I/O nodes of the flip-flops for data-latching data registers DR1-DR4. These switch MOSFETs are turned ON simultaneously in the memory clearing action mode to set a clearing data in the flip-flops of all bits of the data register DR1-DR4. In such a way, a time necessary for clearing the memory can be shortened, and the time in which a serial output for displaying an image is prohibited is shortened. As a result, a stable image can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective when used in dual port memory for image processing, which has both random input and output functions and serial input and output functions.

[Conventional technology]

For example, as an image frame buffer memory for displaying characters or figures on the screen of a CRT (cathode ray tube),
4th edition “Nikkei Electronics” pages 243-264
A dual port memory described on page 1 is known.

The dual port memory described above has a random access port for inputting/outputting stored data in units of one bit or several bits, and a random access port for serially inputting/outputting stored data in units of word lines of the memory array. A serial access port is provided for the Further, the serial access port of the dual port memory is provided with a data register that holds stored data, and is used for timing adjustment necessary for serial-to-parallel conversion of stored data.

[Problem that the invention seeks to solve]

In such a dual port memory, the serial write operation of stored data is performed by inputting the stored data serially through the external terminal for serial input/output, sequentially holding it in the data register according to the selection signal, and then transferring the write data. A method is adopted in which a signal is formed and the data held in the data register is written all at once to all memory cells coupled to the selected word line. Therefore, when performing a so-called memory clear in which data of logic 11" or logic "0" is written to all memory cells, clear data of logic "0" or logic "1" is held in all bits of the data register by the above method. After clearing the memory, the word lines must be specified sequentially, which takes a relatively long time.Especially when clearing the memory while displaying an image, serial output cannot be performed during the clearing period. , the image becomes distorted.

An object of the present invention is to provide a semiconductor memory device that achieves faster memory clearing.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical embodiments disclosed in this application is as follows. That is,
A switch MO5FET is provided between the input/output node of the data launch flipflop included in each unit circuit of the data register of the dual port memory and the circuit power supply voltage and ground potential, and these MOSFETs are set to the memory clear operation mode. The devices are turned on all at once.

[For production]

According to the above means, clear data of logic "1" or logic "0" can be sent to all bits of the data register in the time equivalent to one memory cycle of the dual port memory, and clear data of logic "1" or logic "0" can be written to all bits of the data register. By repeating the write data transfer mode, clear data can be transferred word line by word line to a memory array such as a dual port memory, reducing the time required to clear the memory such as a dual port memory. This can reduce the influence on the displayed image.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of a dual port memory to which this invention is applied. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The dual port memory of this embodiment includes a random access port that is accessed in 4-bit units and has a basic configuration of dynamic RAM, and a serial access port that serially inputs and outputs stored data in word line units.
A port is provided.

This allows the dual port memory to perform a series of serial input/output operations while simultaneously accessing the random access port. Further, although not particularly limited, the random turnout six circuit RIO included in the random access port is provided with a logic operation circuit for performing raster operations, etc., and a function control circuit FC for controlling this logic operation circuit. is provided. The logic operation circuit is equipped with various operation methods such as AND and OR, and which operation to perform depends on the operation code input via the address signal external terminals AO to A3 for a specific combination of control signals. It is specified.

A serial access boat is equipped with a serial input/output circuit S0, which normally has four serial input/output terminals 5I.
Storage data corresponding to the four memory arrays is simultaneously serially input/output via OI-5IO3. Also,
In a specific combination of operation codes, it can also be used as a memory with a so-called x1 bit configuration in which read data output from four memory arrays is alternately output via the serial input/output terminal 5101.

The dual port memory receives the row address strobe signal RAS and column address strobe signal στ used in normal dynamic RAM from an external device.
In addition to control signals such as 1 and write enable signal Wπ, data transfer control signal DT10E used for output control and data transfer control between the random access boat and the serial access boat, and the serial access
A serial output control signal SOE used for port input/output switching control and a serial clock signal SC used as a synchronization signal during serial input/output are input. Furthermore, during the serial input operation of the serial access port, a memory clear signal MC is provided for bringing all data registers into the recent state of logic "1" in - memory access cycles.

Although not particularly limited, the random access boat of the dual port memory of this embodiment is provided with four memory arrays M-ARY 1 to M-ARY 4, and a sense amplifier SAI is provided corresponding to each memory array. ~
SA4. Column switchers C3WI to C3W4 are provided. Furthermore, a random access boat column address decoder RCD and a row address decoder RD are provided in common to memory arrays M-ARY1 to M-ARY4. A plurality of these address decoders may be provided depending on the arrangement of the memory array on the semiconductor substrate. FIG. 2 exemplarily shows the memory array M-ARYI and its peripheral circuits.

In FIG. 2, the memory array M-ARYI includes m+1 word lines arranged in the vertical direction of the figure and n+1 sets of complementary data lines DO and DO arranged in the horizontal direction of the figure.
~Dn-Dn and (m+1) x (n+1) memory cells arranged at the intersections of these word lines and complementary data lines.

The dynamic memory cells constituting the memory array M-ARYI include an information storage capacitor and an address selection M
It is composed of OSFET. n placed in the same row
The gates of the address selection MOSFETs of +1 memory cells are coupled to the corresponding word lines. Each word line is further coupled to a row address decoder RD, and one word line designated by X address signals AXO to AXi is selected and designated.

Row address decoder RD is row address buffer R.
Complementary internal address signal axQ~a supplied from ADB
xi (Here, for example, an internal address signal axQ having the same phase as the X address signal AXO supplied from the outside and an internal address signal axQ having the opposite phase are collectively expressed as a complementary internal address signal axQ. The same applies hereinafter). One word line specified by the X address signals AXO- to AXi is selected and set to a high level selected state. The word line selection operation by row address decoder RD is performed according to word line selection timing signal φX supplied from timing control circuit TC.

Row address buffer RADB receives a row address signal supplied from address multiplexer AMX, forms complementary internal address signal axQxaxi, and supplies it to row address decoder RD. In the dynamic RAM of this embodiment, X is used to specify the row address.
The address signal AXO=AXi and the Y address signals AYO to AYi for specifying a column address adopt a so-called address multiplexer type in which they are supplied in a time-division manner via the same external terminals AO to At.

Therefore, X
Address signals AXO-AXI and Y address signals AYO-AYi are respectively supplied to external terminals AO-Ai in synchronization with the fall of column address strobe signal CAS. Furthermore, the dynamic RAM of this embodiment
is provided with an automatic refresh mode for reading and rewriting data stored in memory cells within a predetermined cycle, and is provided with a refresh address counter REFC for specifying a word line to be refreshed in this automatic refresh mode. .

Address multiplexer AMX outputs X address signals AXO-AXI supplied via external terminals AO-Ai and refresh address counter RE according to timing signal φref supplied from timing control circuit TC.
Refresh address signal cxQ~ supplied from FC
cxi is selected and transmitted to the row address buffer RADB as a row address signal. That is, in a normal memory access mode in which the timing signal φref is set to a low level, X address signals AXO to AXi supplied from an external device via the external terminals AO-At are selected, and the timing signal φref is set to a high level. In the automatic refresh mode, the refresh address signals cxQ to cxi output from the refresh address counter REFC are selected.

As mentioned above, since the X address signals AXO to AXt are supplied to the external terminals AO to At in synchronization with the falling edge of the row address strobe signal RAS, the acquisition of the row address signal by the row address buffer RADB is controlled by the timing control circuit. This is performed in accordance with a timing signal φar generated by detecting the fall of row address strobe signal RAS at TC.

On the other hand, the drains of the address selection MOSFETs of memory cells arranged in the same column of memory array M-ARYI are coupled to corresponding complementary data lines. Complementary data lines DO・■1 to Dn -Dn of memory array M-ARY1
is coupled to the corresponding switch MOSFET of the column switch C3WI, and selectively connects the complementary common data line DDI (here, the non-inverted signal line CDI and the inverted signal line CDI constituting the complementary common data line). They are also expressed as a complementary common data line CDO.

The same applies hereafter).

Column switch C5WI is composed of n+1 pairs of switch MOSFETs each coupled to a corresponding complementary data line. The other terminals of these switch MOS FETs are commonly coupled to a non-inverted signal line CDI or an inverted signal line CDI that constitutes a complementary common data line. This causes the column switch C3WI to connect to the complementary data line DO
-Do-Dn-Dn and common complementary data lines CDI/CDI
to be selectively connected. The gates of each pair of two switch MOSFETs constituting the column switch C3WI are connected in common, and each is supplied with a data line selection signal formed by a random access boat column address decoder RCD.

The random access boat column address decoder RCD decodes the complementary internal address signals ayQ to ayi supplied from the column address buffer CADB, and selects the data line according to the data line selection timing signal φyr supplied from the timing control circuit TC. A selection signal is formed and supplied to column switches C5WI to C3W4.

The column address buffer CADB receives a timing signal φac generated by detecting the fall of the column address strobe signal CAS in the timing control circuit TC.
Accordingly, the Y address signal AYO-AYl supplied via the external terminals AO to Ai is input and held, and an internal address signal ayQ-ayi is formed to output the column address decoder RC for the random access port.
Supply to D.

Complementary data line DO/D1 of memory array M-ARYI
On the other hand, Dn −Dn is the sense amplifier SA
I is coupled to a corresponding unit circuit of data register DRI of the serial access port, and further coupled to a corresponding unit circuit of data register DRI of the serial access port.

Each unit circuit of the sense amplifier SAO has a launch consisting of two cross-connected CMOS inverter circuits as its basic configuration. These sense amplifier unit circuits receive a timing signal φpa supplied from a timing control circuit TC.
The small read signal of the memory cell that is put into the operating state and output to the corresponding complementary data line is amplified and converted into a high level/low level binary signal.

A complementary common data line CDI to which a complementary data line designated by Y address signal AYO=AYi is selectively connected is coupled to a random access port input/output circuit RIO. This random access port user output circuit R
IO includes complementary common data lines CD2 to -CD4 provided corresponding to memory arrays M-ARY2 to M-ARY4.
are similarly combined.

The random input/output circuit RIO is put into an operating state by the timing signal φr- supplied from the timing control circuit TO in the random access port write operation mode of the dual port memory, and the input/output terminal I
The write data supplied from an external device via O1 to 104 is used as a complementary write signal, and the complementary common data line -
It is transmitted to Ω-D1 to ball D4. In addition, in the random access port read operation mode of the dual port memory, the memory cells are brought into an operating state by the timing signal φrr supplied from the timing control circuit TC and transmitted via the complementary common data lines CDI to CD4. Further amplify the read binary signal of the input/output terminal IO
1 to 104.

Furthermore, this random input/output circuit RIO includes, but is not particularly limited to, logical operations for performing various operations between data read from memory cells and input data and writing them again using a read/modify/write function. A circuit is provided. This logic operation circuit is provided with various operation modes for performing processing such as rask operation.

The operation mode of the logical operation circuit is specified by the function control circuit FC.The function control circuit FC is specified by the external terminals AO to A.
3, and a decoder for decoding the operation code and selecting and specifying the operation mode of the logical operation circuit. The operation code is supplied to the dual port memory via external terminals AO to A3 in a combination in which column address strobe signal CAS is set to low level prior to row address strobe signal RAS, and write enable signal WE is set to low level at the same time. be done. Further, a specific combination of operational codes is used as an internal control signal sp for configuring the output of the serial input/output circuit SIO, which will be described later, into a ×1 bit configuration.

On the other hand, the serial access port of the dual port memory of this embodiment includes n+1 bit data registers DRI to DR4 provided corresponding to complementary data lines of each memory array, and data selectors DSLI to DSL4.
and a pointer PNT provided in common to these four data registers and data selectors, a serial access boat column address decoder SCD, and a serial input/output circuit SIO. Note that a plurality of pointers PNT and serial access boat column address decoders SCD may be provided depending on the arrangement of the memory array on the semiconductor substrate.

Data register DRI includes a flip-flop consisting of two cross-connected CMOS inverter circuits provided corresponding to each complementary data line of memory array M-ARYI, as will be described later. A switch MOS for data transfer is connected between the input/output nodes of these flip-flops and the non-inverted signal line and inverted signal line of the corresponding complementary data line.
FETs are provided, and a timing signal φdt for data transfer is supplied to their gates from a timing control circuit TC.

Each bit of data register DRI is further coupled to a corresponding switch MOSFET of data selector DSLI. The data selector DSLI has the same configuration as the above-mentioned column switch C5WI, and the data register DRI
each bit and complementary common data line CD5 for serial input/output
Selectively connect L/CDS 1. Data selector D
The gates of the switch MOS FETs of each pair of SLI are connected in common, and a data register selection signal is supplied from the pointer PNT.

The pointer PNT is constituted by an n+1 bit shift register, and the output terminal ps of the last bit is coupled to the input terminal of the first bit.

In the serial input/output mode of the dual port memory, the pointer PNT performs a loop-shaped shift operation in accordance with the shift clock timing signal φS supplied from the timing control circuit TC. Each bit of pointer PNT is further coupled to a corresponding output terminal of a serial access boat column address decoder SCD.

The serial access port column address decoder SCD receives a complementary internal address signal ay supplied from the column address buffer CADH.

~ayi is decoded and Y address signal AYO~AYi
Only the bits of the pointer PNT corresponding to the beginning of the serial input/output specified by and to are set to logic "1". That is, in the serial input/output mode, a word line is selected by the X address signal AXO=AXt, and the first column address for serial input/output is specified by the Y address signals AYO to AYi. Logic written to the specified bit of pointer PNT by column address decoder SCD for serial access port
1'' signal is sent to the pointer P according to the timing signal φS.
It is shifted in a loop within the NT. By shifting this logic "1" signal, the data selector DSL
1 is sequentially supplied with a high-level data register selection signal, and each bit of the data register DRI is successively connected to complementary common data lines CD5I and CD5L for serial input/output. As a result, the dual port memory of this embodiment can start serial input/output of stored data from any column address, and can speed up scroll processing in the image memory, for example.

From the above, in the dual boat memory serial read operation mode, the memory array M-ARY
The read data of n+l bits output from the n+1 sets of complementary data lines of I is taken into the data register DR1 by the high level of the timing signal φdt supplied from the timing control circuit TC. These read data are sent to the serial input/output circuit SIO via the serial input/output complementary common data lines CDS1 and CD5l in accordance with data register selection signals sent one after another from the pointer PNT. In addition, in the serial write operation mode of the dual boat memory, the write data serially input from the serial input/output terminal 5IOI via the serial input/output circuit SIO is transferred to the pointer PN.
According to the data register selection signal sent one after another from T, the corresponding switch MO5F of the data selector DSLI
The signals are sequentially input to corresponding bits of the data register DRI via ET. The write data held in the data register DPI is coupled to the selected word line of the memory array M-ARYI by the high level of the timing signal φdt supplied from the timing control circuit.
l (Written to the memory cells of fJ all at once.

By the way, the dual boat memory of this embodiment has a data register D according to a timing signal φc1 supplied from a timing control circuit TC, as described later.
A method has been adopted to speed up memory clearing by setting all bits of RI to DR4 to logic 'l' all at once. Therefore, a switch MOSFET whose gate receives the timing signal φcl is provided between the input/output node of the flip-flop of each bit of the data registers DRI to DR4 and the power supply voltage and ground potential of the circuit. These switch MOS FETs are turned on all at once by the high level of the timing signal φc1,
Logic "1" data is sent to the flip-flop of the corresponding bit of data registers DRI-DR4. Logic “1” in all bits of data registers DRI to DR4
After setting the data, the X address signal AXO=AX
Memory clearing can be performed at high speed simply by changing i and sequentially specifying word lines.

The serial input/output circuit SIO includes four main amplifiers, a data cover sofa, and a data output buffer provided corresponding to each serial input/output complementary common data line DSI to CD 3.4 and serial input/output terminals 5IOI to 5104. include. The data output buffer of the serial input/output circuit SIO is activated by the high level of the timing signal φsr supplied from the timing control circuit TC in the serial read operation mode of the dual port memory, and the data output buffer of the serial input/output circuit SIO is activated by the high level of the timing signal φsr supplied from the timing control circuit TC. Read data outputted via the common data lines CDS1 to CD54 and amplified by the corresponding main amplifiers is outputted to external devices from the serial input/output terminals 5101 to 5IO4. Furthermore, in the serial write operation mode of the dual port memory, the data cover sofa of the serial input/output circuit SIO is put into an operating state by the high level of the timing signal φS- supplied from the timing control circuit TC, and the corresponding serial input Output terminal 5101~
Write data supplied from an external device via 5IO4 is made into a complementary write signal and transmitted to the corresponding serial input/output complementary common data lines CD5I to CD54. Serial input/output operations on data stored in the serial input/output circuit srO are performed in the timing control circuit TC according to a timing signal φC formed based on a serial clock signal SC supplied from the outside.

In the dual port memory of this embodiment, the serial output signal of the normal serial input/output circuit 510 is output simultaneously in 4 bits via the four serial input/output terminals 5101 to 5104 as described above. However, if you want to realize a serial memory with even larger storage capacity, you can combine this dual port memory with four memory arrays M-AR.
It can be used as a memory having a so-called x1 bit configuration in which read data outputted from Y1 to M-ARY4 is serially outputted via one serial input/output terminal. In this case, as mentioned above, the random input/output circuit R1
One of the combinations of operation codes for controlling the operation mode of the logical operation circuit of ◯ is an internal control signal sp for making the serial output have a ×1 bit configuration. When the internal control signal sp supplied from the function control circuit FC becomes high level, the serial input/output circuit SIO serially outputs the read data serially through the complementary common data lines CD5I to DS4 for serial input/output. They are sequentially selected by a multiplexer provided in the input/output circuit SIO and output to an external device via one serial input/output terminal 5IOI.

Since this serial output is performed according to the timing signal φC supplied from the timing control circuit TC, the data rate of each input/output terminal is Same data rate.

The timing control circuit TC receives a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, a data transfer control signal RISO/δ1-, a serial output control signal "5 lower and memory" which are supplied as control signals from the outside. The various timing signals mentioned above are formed using the clear control signal MC and supplied to each circuit. Also, the timing signal φC for synchronizing the serial input/output operation is formed using the serial clock signal SC supplied from the outside. , serial input/output circuit SIO
supply to.

The operation mode of the dual port memory is specified by appropriate combinations of control signals. For example, first the row address strobe signal RAS becomes low level, and then the column address strobe signal CAS becomes low level. If the write enable signal WE is at a high level at this point, the normal random access port read operation mode is set. Row address strobe signal RAS and column address strobe signal CA
Write enable signal WE at both falling edges of S
is low level, normal random access
The port is set to write operation mode. Furthermore, if the write enable signal WE is at a high level when the row address strobe signal RA1 falls and is at a low level when the column address strobe signal O3 falls, it is determined that this is an arithmetic write cycle using a logical operation circuit. Furthermore, if the write enable signal WE is at high level and the data transfer control signal DT10E is at low level at the falling edge of the row address strobe signal RAS, the read data of the memory array is transferred to the data registers DRI to DR4 to perform so-called serial read. A read data transfer mode is set for this purpose, and a timing signal φdt is generated. In this read data transfer mode, after the read data transfer to the data registers DRI to DR4 is completed and the data transfer control signal ■/σ is returned from low level to high level, serial output operation is performed in synchronization with the serial clock signal SC. is started. Next, when the data transfer control signal DT10E and the write enable signal WE are at a low level and the serial input/output control signal SOE is at a high level at the falling edge of the row address strobe signal RAS, the serial write operation mode is set, and the serial Input/output terminal 5I
Serial write data supplied via OI-5IO4 is input to data registers DRI-DR4. At this time, if the memory clear control signal MC is at a low level, the memory clear operation mode is entered, and the data register D
A predetermined write data pattern, that is, write data in which all bits are logic "1" is set in RI to DR4. Further, when the data transfer control signal "/σE" and the write enable signal WE are at a low level and the serial input/output control signal SOE is at a low level at the falling edge of the row address strobe signal RAS, the write data transfer mode is set. Transfer timing signal φdt
is formed.

As a result, the transfer switch MO5FET of the data registers DRI-DR4 is turned on, and the data register DRI-D is turned on in the serial write operation mode.
The write data sent to R4 is input all at once to n+1 bit memory cells coupled to the selected word line of the memory array. A serial write operation using a serial access port is realized by executing the above-described serial write operation mode and then executing the write data transfer mode in combination.

On the other hand, prior to the fall of the row address strobe signal RAS, the column address strobe signal cAs changes from high level to low level to enter the sash mode. At this time, if the write enable signal WE is at a low level at the falling edge of the row address strobe signal RAS, it is considered an operation mode setting cycle, and the operation code supplied via the external terminals AO to A3 is stored in the function control circuit FC. is loaded into the register.

In each operation mode except for the arithmetic mode setting cycle described above, X address signals AXO to AXi for specifying a word line are supplied to external terminals AOxAi in synchronization with the fall of the row address strobe signal RAS, and the column address In the operation mode that requires
~AYi is supplied to the external terminal AO-At.

FIG. 1 shows a circuit diagram of one embodiment of a data register DRI in the dual port memory of FIG. Since the data registers DR2 to DR4 also have the same circuit configuration as in FIG. 1, an outline of the memory clear operation of the dual port memory will be explained using the data register DRI as an example. In addition, in the same figure, the channel (
MOSFETs with an arrow added to the back gate) are P
It is a channel type MOSFET, and is distinguished from an N-channel MOSFET without an arrow.

In FIG. 1, fi+1 sets of complementary data lines DO-DO to Dn-Dn forming memory array M-ARYI are as follows:
Corresponding unit circuit of sense amplifier SAI
= U S A n, and further a switch MO5FETQ13 for data transfer of data register DRI.
Data register DRI via Q14-Q15-Q16
are coupled to corresponding unit circuits UDRO to UDRn.

n+1 unit circuits UDRO of data register DR1~
UDRn is the switch MO of data selector DSL 1
It is selectively coupled to the serial input/output complementary common data line -CDSL via SFETs Q17, Q18 to Q19, and Q20. Switch MOSF of data register DRI
The gates of ETQ13, Q14 to Q15, and Q16 are all connected in common, and a timing signal φdt for data transfer is supplied from the timing control circuit TC. In addition, the switch MOSFET TQ of each pair of data selector DSL 1
I? - The gates of Q18 to Q19 and Q20 are connected in common, and the corresponding data register selection signal S Ow S n is supplied from the pointer PNT.

Each unit circuit of data register DPI is a unit circuit UDR.
As represented by I (and UDRn), a C
OS inverter circuit and P-channel MOSFETQ2
(Q4) and N-channel MOSFETQ6 (QI
It includes another CMOS inverter circuit consisting of O). The input terminals and output terminals of these CMOS inverter circuits are each cross-connected to form a data launch flip-flop. In addition, the input/output node of this flip-flop is the switch MOSFETQI3/Q
14 (Q15/Q16) to the memory array M-AR
It is coupled to complementary data lines DO and DO (Dn-Dn) of Y1.

Furthermore, in the dual port memory of this embodiment,
To speed up memory clear operation, data register D
A switch MOS FET is provided for supplying the circuit's power supply voltage Vcc or ground potential to the input/output node of the flip-flop of each unit circuit of the PI. As a result, the data register DPI is brought into a clear state in which all bits hold logic "1" data. In other words, the MO used as the non-inverting output node of the unit circuit UDRO (UDRn) in FIG.
Between the commonly connected drains of SFETQI (Q3) and Q5 (Q9) and the circuit power supply voltage Vcc, there is an N
Channel type switch MOSFETQ? (Qll
) is provided and is used as an inverting output node.
An N-channel switch MOSFET Q8 (Q12) is provided between the commonly connected drains of 2 (Q4) and Q6 (QIO) and the ground potential of the circuit. These MOSFETs Q7 (Qll) and Q8 (Q12)
A timing signal φc1, which is set at high level in the memory clear operation mode, is supplied from the timing control circuit TC to the gate of.

In the case of the dual port memory read data transfer mode, when a word line is selected, a minute read signal from the n+1 bit memory cell coupled to the word line is sent to the corresponding unit circuit USAO of the sense amplifier SAI.
~Input into USAn. Each unit circuit of the sense amplifier SAI is put into an operating state by a timing signal φpa supplied from the timing control circuit TC, amplifies the minute read signal sent from the memory cell, and outputs the complementary data line D.
Set O-DO to Dn-Dn to high level or low level. These complementary data lines DO-DO to Dn-D
The level of n is determined by the high level of the timing signal φdt supplied from the timing control circuit TC.
When the 5FETQI3.Q14 to Q15.Q16 are turned on, the data is taken into the unit circuits UDRI to UDRn of the data register DRI and held. The read data held in the data register DRI is sent to the data selector DSL1 in accordance with the data register selection signal S Ow S n sent one after another from the pointer PNT when the serial input/output control signal D T10 E is returned from low level to high level. switch MOSFETQ
17.Q18 to Q19.Q20 are turned on one after another, so that the complementary common data line for serial input/output CD5
Sequentially transmitted to I/CD5L, serial input/output circuit S■
0 and is sent out from the serial input/output terminal 5IOI.

On the other hand, in the serial write operation mode of the dual boat memory, the write data serially input from the serial input/output circuit SIO via the complementary common data lines CD5L/CDS1 for serial input/output is the data sent from the pointer PNT. Register selection signal 5O-3
Switch MO5F of data selector DSLI according to n
When ETQI7.Q18 to Q19.Q20 are turned on one after another, the data is sequentially taken into the unit circuits UD RO to UD Rn of the data register DRI and held. The write data held in the data register DPI is transferred to the switch MO5FE by the timing signal φdt supplied from the timing control circuit TC in the write data transfer mode newly established immediately thereafter.
By turning on TQ13, Q14 to Q15, and Q16 all at once, fi+ of memory array M-ARYI
It is input to fi+1 memory cells coupled to the selected word line via a set of complementary data lines.

In the memory clear operation mode of the dual boat memory, the high level of the timing signal φcl supplied from the timing control circuit TC causes MOSFETQ7 to
- Q8 (Qll and Q12) are simultaneously turned on. As a result, the power supply voltage Vcc and the ground potential of the circuit are supplied to the non-inverting output node and the inverting output node of the flip-flops constituting each unit circuit of the data register DRI, respectively. Therefore, data registers DRI~DR
Each of the unit circuits No. 4 is in a state in which so-called logic "1" write data is set, with its non-inverted output node being at a high level and its inverted output node being at a low level. These write data of logic "1" are transferred to the switch MOSFETQ by the high level of the timing signal φdt supplied from the timing control circuit TC in the write data transfer mode newly established immediately after that.
When I3.Q14 to Q15.Q16 are turned on all at once, the signal is input to the (n+1) memory cells coupled to the selected word line. By executing such a write data transfer mode while sequentially switching the Y address signals AYO to AYi, all memory cells of the dual boat memory can be brought to a clear state of logic "1". Further, in this memory clear operation mode, the time required to write write data of logic "1" to all bits of data registers DRI to DR4 is only one memory cycle of the dual port memory.

As described above, in the dual boat memory of this embodiment, there is a connection between the input/output nodes of the data launch flip-flops constituting each unit circuit of data registers DRI to DR4 and the circuit power supply voltage and ground potential. , a switch MO5FET whose gate receives a timing signal φcl for memory clearing supplied from the timing control circuit TC.
is provided. These switch MOS FETs are
In the memory clear operation mode newly provided in the dual boat memory, - they are simultaneously turned on and write data of logic "1", that is, clear data, is set in the flip-flops of all bits of data registers DRI to DR4. . The clear data held in the data registers DRI to DR4 is transferred to the memory array M-AR in the write data transfer mode that is repeatedly performed immediately thereafter.
It is input to all memory cells YI to M-ARY4. Therefore, when clearing the memory of the dual boat memory, it only takes one memory cycle to set the clear data in the data registers DRI to DR4, greatly reducing the time required to clear the memory. It is something. In addition, these word line unit memory clear operations can be used to partially clear the displayed image, reducing the time during which serial output for image display is prohibited during these clear operations. , stable images can be obtained.

As shown in the above embodiment, when the present invention is applied to a semiconductor storage device such as a dual port memory used as an image processing memory, the following effects can be obtained. That is, between the input/output node of a data launch flip-flop of a data register such as +ll dual port memory and the power supply voltage and ground potential of the circuit,
A switch MOSFET is provided and these M O
By activating S FET all at once, clear data of logic "1" or logic "O" can be set to all bits of the data register in the time equivalent to one memory cycle of the dual port memory. You can get the effect that you can.

(2) The clear data sent to the data register in accordance with item (1) above is transferred to the memory array in word line units by repeating the write data transfer mode, which is required to clear memory such as dual boat memory. This has the effect of shortening the time.

(3) Items (1) and (2) above shorten the time during which serial output operation is inhibited by memory clearing of dual port memory, thereby reducing the impact on the display image during clearing. The effect is that the number of images can be reduced and a stable image can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment shown in FIG. 1, write data of logic "1" is sent to data registers DRL to DR4 as clear data.
The write data of logic "0" may be used as clear data. In addition, the non-inverting output node of the flip-flop of the data register in FIG. 1 and the power supply voltage Vc of the circuit
MOSFETQ7 and Qll provided between
A P-channel MO5FET may also be used. In this case, an inverted signal of the timing signal φcl is supplied to the gates of these MOSFETs. Furthermore, the dual boat memory shown in FIG.
It is possible to adopt various embodiments such as not providing a logic operation circuit in the input/output circuit RIO of the access boat, and combinations of block configurations and control signals.

The above explanation mainly describes the invention made by the present inventor in the field of application, which is the dual boat
Although the case where the present invention is applicable to memory clearing of the memory has been described, the present invention is not limited thereto, and can also be applied to various semiconductor storage devices having a serial input/output function, for example.

The present invention is applicable to semiconductor memory devices having at least a data register for serial/parallel conversion and a serial input/output function.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a switch MO is connected between the input/output node of a data launch flip-flop of a data register such as a dual boat memory and the power supply voltage and ground potential of the circuit.
By providing SFETs and activating these MOSFETs all at once using a timing signal supplied in the memory clear mode, all bits of the data register can be set to logic "1" in the time equivalent to one memory cycle of the dual port memory. Alternatively, clear data of logic "0" can be set, and the clear data sent to this data register is transferred to the memory array in units of word lines by repeating the write data transfer mode, thereby achieving dual port transfer. The time required to clear the memory or the like can be shortened, and the influence on the displayed image during the clearing operation can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of a data register of a dual port memory to which the present invention is applied, and Fig. 2 is an embodiment of a dual port memory including the data register of Fig. 1. FIG. DRI...Data register, DSLl...Data selector, SAI...Sense amplifier, M-ARYl-.
・Memory array, PNT...pointer, SiC...
Serial input/output circuit, TC...timing control circuit,
UDRI~UDRn...Data register unit circuit, U
SAO~USAn...Sense amplifier unit circuit, Q1~
Q4--Pf Ya7 channel MO5FET, Q5~Q20-
...N-channel MOSFET. C3WI...Column switch, RCD...Column address decoder for random access port, SCD
...Column address decoder for serial access boat, RD...Row address decoder, RIO...
・Random input/output circuit, FC...Function control circuit, CA
DB: Column address buffer, RADB: Row address buffer, AMX: Address multiplexer, REFC: Refresh address counter. Figure 1 Figure 2

Claims (1)

[Claims] 1. A memory array consisting of a plurality of data lines, a plurality of word lines, and a plurality of memory cells arranged at the intersections of the data lines and the word lines, and each bit is connected to the plurality of data lines. a data register that inputs and outputs data in parallel with a plurality of memory cells that are provided correspondingly and are selectively coupled to the plurality of data lines by a selection operation of the word line; The serial/parallel conversion circuit outputs read data serially to an external terminal according to a selection signal, and sequentially holds write data input serially through an external terminal in the data register according to a selection signal. 1. A semiconductor memory device, wherein predetermined write data can be collectively held in the data register under a specific combination of control signals. 2. Each bit of the data register has a first P-channel MOSFET and a second N-channel MOSFET connected in series between the power supply voltage of the circuit and the ground potential.
Two sets of CMOS inverter circuits consisting of OSFETs are cross-connected, and their input/output nodes are coupled to the non-inverting signal line and the inverting signal line of the corresponding complementary data line of the memory array through a pair of data transfer switch MOSFETs. a flip-flop, and two switch MOSFETs that are provided between each of the input/output nodes of the flip-flop and the power supply voltage and ground potential of the circuit, and receive timing signals for batch writing to the gates of the flip-flops.
A semiconductor memory device according to claim 1, characterized in that the semiconductor memory device includes: