JP2575090B2 - Semiconductor storage device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a RAM (random access memory) for image processing.
It relates to technology that is effective to use.

(Background technology)

As image processing RAM for displaying characters and graphics on the screen of a CRT (cathode ray tube), for example, Nikkei McGraw-Hill, February 11, 1985, Nikkei Electronics, pages 219-
The serial access memory described on page 229 is known. In this RAM, a counter circuit for forming an address signal is operated by a control signal and a timing signal supplied from external terminals, thereby forming a word line selection signal of a memory array. Further, the data lines of the memory array are connected in parallel to a data register via a switch circuit, and data is serially transmitted and received between the data register and an external terminal. As a result, data transmission / reception with the external terminal is performed serially, so that pixel data can be easily taken out in synchronization with the raster scan timing of the CRT. The shift register has a multi-bit output configuration in order to increase the bit rate. However, in the case of a CRT having a small display screen, a 1-bit output configuration is more preferable than a configuration in which a very high bit rate is not required.

[Object of the invention]

An object of the present invention is to provide a semiconductor memory device in which a multi-bit output function and a 1-bit output function are selectively switched by a predetermined operation mode signal.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention]

The outline of a representative embodiment among the embodiments disclosed in the present application will be briefly described as follows. That is, an amplifier circuit for transmitting output signals of a plurality of shift registers, in which signals of data lines in a plurality of memory arrays are transferred in parallel, to an external terminal, respectively, and transmitting the signals serially to a specific amplifier circuit for external transmission. And a shift register for serially transmitting to a terminal, and selectively operating them by a predetermined operation mode signal.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. Each circuit block in the figure is formed on a single semiconductor substrate such as single crystal silicon, although not particularly limited by a known semiconductor integrated circuit manufacturing technique.

The semiconductor memory device of this embodiment is based on a dynamic RAM having a × 4 bit configuration, and has an internal circuit for performing an image processing operation at high speed, as described below. Although not particularly limited, the memory RAM shown in FIG.
Is composed of four sets of memory arrays, sense amplifiers and address decoder circuits. The memory array unit RAM includes dynamic memory cells each including an address selection MOSFET (insulated gate field effect transistor) and a capacitor for storing information arranged in a matrix. The gate of the memory cell address selection MOSFET is coupled to the corresponding word line, and the drain is coupled to the corresponding one of the data lines. The configuration of such a memory RAM is the same as that of a conventional × 4 bit dynamic RAM, and a description thereof will be omitted.

Signals of complementary data lines in the memory array are transferred in parallel to respective bits of a total of four sets of shift registers SR via switch MOSFETs Q1, Q2, etc. shown as examples. These MOSFETs Q1 and Q2 are controlled by a timing signal φs commonly supplied to their gates, and the transfer timing of the signals is controlled. The output signal of this shift register SR is output via an output circuit P / S.
The 4-bit signal transmitted from the shift register SR is transmitted to the external terminal Ds in parallel or serial. The configuration and operation of such shift register SR and output circuit P / S will be described later in detail. The function of reading out stored information for one word line in such a memory array in parallel and transmitting a 4-bit signal from a total of four sets of shift registers SR to the external terminal Ds is synchronized with the raster scan timing of the CRT. This is convenient for generating graphic data of red, blue, green, and luminance constituting a color pixel to be displayed.

The row address buffer R-ADB takes in the external address signals AX0 to AXi in synchronization with the timing signal φr formed by the row address strobe signal ▼, and forms an internal complementary address signal to be transmitted to the row address decoder. A row address decoder included in the memory unit RAM decodes the address signal and performs a predetermined word line and dummy word line selection operation in synchronization with a word line selection timing signal.

The column address buffer C-ADB takes in the external address signals AY0 to AYi in synchronization with the timing signal φc formed by the column address strobe signal ▲ ▼ which is supplied with a delay in normal memory access, and takes in the column address decoder. Tell A column address decoder included in the memory unit RAM decodes the address signal and performs a data line selection operation in synchronization with a data line selection timing signal. In this embodiment, the column address buffer C-ADB receives the address signals AY0 to AYi as described above, and also uses the signal fetched from the address terminal under certain operating conditions as a function signal as a function setting circuit FN. Tell

The function setting circuit FN decodes a signal fetched through the column address buffer C-ADB when the function setting circuit FN is activated by a timing signal φfn formed by a timing control circuit TC, which will be described later. An operation mode signal of the circuit P / S and a shift clock signal corresponding to the operation mode signal are generated. Further, the function setting circuit FN can switch the output operation,
Although not particularly limited, the operation mode signal fn for setting the operation mode of the logical operation circuit LU, the mask signal msk for selectively disabling the operation of the data input circuit IB, and the output signal of the data input circuit IB are used for the logical operation circuit LU. A pass signal for controlling the gate circuit G to be transmitted to the input / output node I / O of the memory unit RAM without being passed through is generated.

The logical operation circuit LU includes four sets of circuits corresponding to the four sets of memory units RAM, and a signal held in a latch circuit F provided at one input thereof and a data input circuit IB
And a write signal supplied from the external terminal Di through the AND circuit, and performs various logical operation operations such as AND (AND), NAND (NAND), OR (OR), NOR (NOR), inversion and exclusive OR operation. This is performed according to the operation mode signal fn. The latch circuit F has its input terminal coupled to the input / output node I / O of the corresponding memory unit RAM, and holds the storage information of the selected memory cell. Logical operation circuit
The LU is composed of a combination of a plurality of logic gate circuits and a multiplexer circuit for switching the signal transmission path. For this reason, when writing the write signal supplied from the external terminal Di as it is, if the write signal is passed through the logical operation circuit LU including the above-described logic gate circuit and multiplexer circuit, the signal transmission time is correspondingly reduced. Would. The gate circuit G outputs the output signal of the data input circuit IB directly to the memory RAM
To the input / output node I / O. With such an operation, a writing operation can be performed at high speed.

The data input circuit IB is composed of a total of four sets of circuits. When the data input circuit IB is activated by the operation timing signal φin,
The 4-bit write signal supplied from the external terminal Di is amplified to form an internal write signal. The data input circuit IB receives the timing signal φi in accordance with the mask signal msk formed by the function setting circuit FN.
The operation state by n is selectively disabled. In other words, the operation of any circuit of the above four sets of circuits is invalidated. Such a masking operation for an external write signal is a convenient function when any one to three signals of one pixel data including red, blue, green, and luminance signals are selectively input.

The data output circuit OB is composed of a total of four circuits. When the data output circuit OB is activated by the operation timing signal φop,
The signal of a total of 4 bits of the corresponding input / output node of the memory unit RAM is amplified and transmitted to the external terminal Do.

The timing control circuit TC receives externally supplied address strobe signals ▲ ▼, ▲ ▼, a write enable signal ▲ ▼, and a clock signal CLK for operating the shift register SR, identifies the operation mode, and performs various operations in accordance with the operation mode. The timing signal φfn and the like are formed.

Although the refresh control circuit REFC is not particularly limited,
A refresh address counter circuit for generating a refresh address signal is included. The refresh address counter circuit receives the refresh signal φrf formed by detecting that the column address strobe signal ▼ is set to the low level prior to the row address strobe signal ▼ by the timing control circuit TC. The above-described step (counting operation) is performed for each low level of the signal ▼. In the refresh operation mode, the refresh address signal generated by the refresh control circuit REFC is transmitted to the input of the row address buffer R-ADB in the refresh mode, and the memory section RAM is passed through the row address buffer R-ADB. Are supplied to the row decoder.

FIG. 2 is a block diagram showing an embodiment of the shift register SR and the output circuit P / S.

The shift register SR has a total of four shift registers SR0
~ SR3. These shift registers SR0 to SR
3 is the data line of the memory array to which each bit corresponds, and the switch MOSFETs Q1 and Q1 as shown in FIG.
Combined via 2 etc. This allows the MOSFETs Q1, Q2
Are turned on, the storage information of the memory cells coupled to the selected word line of the memory array is transferred in parallel. These shift registers SR0 to SR3 perform their shift operations in accordance with a clock signal φsc formed by function setting circuit FN.

The output circuit P / S includes main amplifiers MA0 to MA3 that receive output signals of the shift registers SR0 to SR3, and a data output buffer DO0 that amplifies the output signals and sends output signals to external terminals Ds0 to Ds3. ~ DO3.
The operation of the data output buffers DO0 to DO3 is controlled by a control signal PS.

Further, in order to provide a function of serially transmitting signals output in parallel from the four shift registers SR0 to SR3 to external terminals, the main amplifiers MA0 to MA3 are
A shift register is formed by cascade connection via a transmission gate MOSFET (not shown) and a latch circuit. This enables the main amplifier and shift register MA / SR
Is configured. These main amplifiers and shift registers
The operation of MA · SR is controlled by its clock signal φsc ′.

The operation of the output circuit of this embodiment will be described with reference to the timing chart shown in FIG.

The parallel output operation of the output circuit P / S is as follows.

Prior to the fall of the row address strobe signal ▼, for example, when the clock signal CLK is set to the low level, the mode is set to the signal transfer mode to the shift register SR.
That is, the row address strobe signal ▲ ▼
The row address signals AX0 to AXi are fetched in synchronization with the falling edge of, and one word line is selected. After this word line selection operation, the sense amplifier and active restore circuit of the memory array are operated. As a result, the signal of the data line (bit line or digit line) is used as storage information of the selected memory cell. Thereafter, a timing signal φs is generated, and the signal of the data line is transferred to the shift register SR in parallel. Such a parallel read operation of the memory array ends when the row address strobe signal ▼ rises to a high level. Thereafter, in parallel with the operation for outputting all the signals transferred to the shift register SR to the external terminal Ds, a function setting operation and a write / read operation to / from the memory RAM as described later are arbitrarily performed.

When the clock signal CLK is changed after the transfer operation, the function setting circuit FN causes the clock signal CL to change.
A clock signal φsc synchronized with K is generated, and the clock signal φsc ′ is maintained at a low level. Due to the low level of the clock signal φsc ′, the transmission gate MOSFET forming the main amplifier / shift register MA / SR is maintained in the off state, and the main amplifiers MA0 to MA3 are turned off.
Amplifies the output signals shifted from the shift registers SR0 to SR3 and transmits them to the data output buffers DO0 to DO3, respectively. At this time, the data output buffers DO0 to DO3 are all activated by the control signal PS, and the main amplifier
The output signals of MA0 to MA3 are amplified and sent to external terminals Ds0 to Ds3.

The serial output operation of the output circuit P / S is as follows.

As described above, prior to the falling of the row address strobe signal ▲ ▼, the clock signal CLK is set to the low level to perform a parallel read operation to the shift register SR of the memory array, and then the clock signal CLK is changed. FN is the clock signal CL
A clock signal φsc ′ synchronized with K and a clock signal φsc frequency-divided by / 4 are generated. In addition, the control signal PS (not shown) is changed to make the data output buffer DO0 operational, and the remaining data output buffers DO1 to DO3
Is made inoperative. In other words, the output of the output data output buffers DO1 to DO3 is set to a high impedance state.

As a result, the 4-bit signal output to the main amplifiers MA0 to MA3 by the clock signal φsc is serially shifted by the transmission gate MOSFET operating according to the clock signal φsc '. That is, the output (SR0) of the main amplifier MA0 is transmitted from the data output buffer DO0 by the first clock signal φsc ′, and the signals of the main amplifiers MA1 to MA3 are transmitted to the data output buffer DO0 by the clock signal φsc ′ that successively arrives. Thus, the signals corresponding to the shift registers SR1 to SR3 are transmitted serially.

Next, an example of the function setting operation and the write operation will be described with reference to the timing chart shown in FIG.

Before the row address strobe signal ▼ changes from the high level to the low level, the column address strobe signal ▼ and the write enable signal ▼ are set to the low level. Then, the internal circuit is activated at the timing when the row address strobe signal ▲ ▼ which is a substantial chip selection signal is changed from high level to low level, and the timing control circuit TC sets the column address strobe signal ▲ ▼ to low level at the above timing. Then, the refresh control signal φrf is generated to generate various timing signals for the refresh cycle. (▲ ▼ Before ▲
▼ Refresh). Thereby, the refresh control circuit
The refresh address signal formed by REFC is transmitted to a row address decoder of the memory unit RAM via a row address buffer R-ADB, and thereafter, according to a time-series timing signal generated by a timing control circuit TC (not shown). A refresh operation is performed by a word line selection operation and a series of operations of a sense amplifier and an active restore circuit. At this time, the row address buffer R-AD
The input terminal of B is coupled to the refresh-controlled REFC, and is separated from the external address terminal.

The timing control circuit TC outputs the column address strobe signal ▲ ▼ and the write enable signal ▲
When it is detected that both ▼ are at the low level, the timing of the change of the row address strobe signal ▲ to the low level causes the column address buffer C-ADB
And a timing signal φfn for activating the function setting circuit FN. In the above refresh operation, since no data line selection timing signal is generated, the column address decoder C-DCR is substantially put into a non-operating state. Therefore, the function signal F (fn, ml) passed through the column address buffer C-ADB is taken into the function setting circuit FN which is activated at this time. The function setting circuit FN holds the acquired function signal F, decodes it, and forms various operation mode signals for the next operation. In this way, the refresh operation and the operation of taking in the function signal F are performed in parallel in the same memory cycle (refresh cycle).

Next, when the row address strobe signal ▼ changes from the high level to the low level, the timing control TC generates the timing signal φr to put the row address buffer R-ADB into the operating state, and is supplied from the external address terminal. The address signal is converted to the row address signal AX (AX0
~ AXi). Thereafter, although not shown, the timing control circuit TC generates the word line selection timing signal, the sense amplifier operation timing signal, and the active restore operation timing signal in time series, and performs the row-related selection operation.

Next, when the column address strobe signal ▼ changes from the high level to the low level, the timing control TC generates a timing signal φc to activate the column address buffer C-ADB, and the address supplied from the external address terminal. Signal to column address signal
Import as AY (AY0 to AYi). Thereafter, although not shown, the timing control circuit TC generates the data line selection timing signal to perform a data line selection operation. As a result, the signal of the common complementary data line CDL of the memory array in the memory part RAM, ▼ (input / output node I / O), in other words, the storage information DA of the memory cell specified by the address signals AX and AY is The data is taken into the latch circuit F.

In the write operation mode in which the write enable signal ▼ is set to low level, the write signal DB supplied from the external terminal Di is taken in via the data input circuit IB. If the operation mode signal fn indicates the AND operation mode, the logical operation circuit LU forms the signal DA of the latch circuit F and the AND signals DA and DB of the write signal DB to form the input / output node I / O. Tell Thus, the signals DA and DB are written to the selected memory cells. Thus, by one cycle of the write operation, the storage information of the memory cell can be replaced with pixel data according to the logical operation of the write information and the write signal supplied from the external terminal.

Another mode of operation based on the function setting is to replace information stored in a memory cell with a write signal supplied from an external terminal. In this case, a pass signal ps is formed in the same function setting operation as described above. As a result, the write signal passing through the data input circuit IB is directly transmitted to the input / output node of the memory section RAM (the common complementary data line of the memory array MARY) through the gate circuit (tristate buffer) G instead of the logical operation circuit LU. ). With this, conventional dynamic RAM
The writing operation can be performed at high speed in the same manner as in the first embodiment.

Note that the read operation is the same as that of a conventional × 4 bit dynamic type RAM, and a description thereof will be omitted. In this case, a function of masking a specific bit in the 4-bit pixel signal may be provided, but such an operation is performed by not processing the bit on the microprocessor side. realizable.

〔effect〕

(1) As an output circuit for receiving output signals from shift registers corresponding to a plurality of memory arrays, a shift register (also serving as a main amplifier) selectively activated by a function setting is provided, so that a parallel output of a plurality of bits is provided. The function and the serial output function can be realized.

(2) According to the above (1), an image corresponding to a high-resolution CRT by increasing the number of pixel dots and an image corresponding to a CRT reduced in size by relatively reducing the number of pixel dots. The effect that a semiconductor memory device for processing can be obtained is obtained.

(3) By configuring a shift register for realizing serial output using the main amplifier, an effect is obtained that the circuit can be simplified.

(4) Prior to the fall timing of the row address strobe signal ▲ ▼, identify that the column address strobe signal ▲ ▼ and the write enable signal ▲ ▼ are at the low level, and take in the signal supplied from the address terminal to capture the function signal. ▲ ▼ Before ▲
The effect that the refresh operation can be performed simultaneously and in parallel is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, parallel /
The circuit for realizing the serial output function can adopt various embodiments such as providing a shift register on the input side of the main amplifier or using a multiplexer for transmitting each bit output to a specific output circuit. The word line selection operation of the memory array for parallel reading to the shift register may be performed by an address signal generated by a built-in address counter circuit. The arithmetic circuit may have an arithmetic operation function, or may omit the arithmetic circuit itself. The function signal for switching between the parallel output and the serial output is formed by the level of a signal supplied from an external terminal. It may also be supplied as such.
The input terminal of the data input circuit and the output terminal of the data output circuit may be connected to a common external terminal to reduce the number of external terminals.

[Applications]

The present invention can be widely used as a semiconductor storage device for image processing or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the output circuit, and FIG. 3 is an example of a parallel output operation and a serial output operation. FIG. 4 is a timing chart showing an example of a function setting operation and a write operation. RAM: memory unit, R-ADB: row address buffer,
C-ADB: column address buffer, OB: data output circuit, IB: data input circuit, TC: timing control circuit, REFC: refresh control circuit, FN: function setting circuit, LU: arithmetic circuit, G ... gate circuit,
F: Latch circuit, SR (SR0 to SR3): Shift register, P / S: Output circuit, MA / SR: Main amplifier and shift register, DO0 to DO3: Data output buffer, MA0 to M
A3 …… Main amplifier

Claims (1)

(57) [Claims] A plurality of memory arrays in which dynamic memory cells are arranged in a matrix at intersections of data lines and word lines; a plurality of shift registers provided corresponding to the plurality of memory arrays; A transfer gate provided between the memory array and the corresponding shift register to transfer signals in parallel, a plurality of main amplifiers receiving signals output from the plurality of shift registers, and a plurality of main amplifiers. A data output circuit provided correspondingly; a function setting circuit for forming a predetermined operation mode signal; and a timing control circuit, wherein the output signal of the main amplifier is passed through each data output circuit by the predetermined operation mode signal. First operation to output, and output of each main amplifier from one data output circuit A second operation for serially outputting a signal, wherein the timing control circuit changes the column address strobe signal to a low level when the row address strobe signal changes from a high level to a low level. And is configured to supply a timing signal to the function setting circuit by identifying that the write enable signal is at a low level, and the function setting circuit responds to the timing signal from the timing control circuit, A semiconductor memory device wherein a signal supplied from a terminal is taken in as the operation mode signal.