JP2527257B2 - Image signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in the reading of facsimiles and digital copiers, image scanners, etc., and amplifies an output image signal of an image sensor having a black dummy bit, and outputs the black dummy bibit. The present invention relates to an image signal processing device that clamps a predetermined potential with a section as a reference.

2. Description of the Related Art Conventionally, an image sensor 1 has been used as an image signal processing device.
There is generally known a device in which a drive pulse having a constant frequency is applied to the image sensor, the image signal read from the image sensor is guided to the clamp circuit, and the image signal is clamped with the signal level of the black dummy bit as a reference.

However, in the configuration of the image signal processing device, when the image sensor of the two-phase drive system in which black dummy bits are 64 pixels and the number of effective pixels is 4096 pixels is used, Since the frequency is constant, the time ratio between the black dummy bit section and the other sections is about 1:64. Due to such a large time ratio, the following problems occur.

As a clamp circuit for using the output of the black dummy bit as a reference of the image signal level, for example, a clamp circuit using AC coupling is used.However, in the clamp circuit using AC coupling, when the clamp switch is ON, It is desirable that the capacity of the capacitor used for the clamp is small in order to improve the followability by speeding up the charge and discharge with respect to the change in the amplitude of the image signal, but on the other hand, in order to improve the hold characteristic when the clamp switch is OFF, The larger the capacitance of the capacitor used for the clamp, the more desirable. In this case, the time ratio between the black dummy bit section and the other sections is the same as in the prior art.
If it is as large as 1:64, the ratio between the charge / discharge time of the capacitor of the clamp circuit and the hold time becomes large accordingly, and there is a problem that it is difficult to easily determine the capacitance of the capacitor.

In addition, a plurality of sensor chips provided with black dummy bits are provided on the substrate, image signals are taken out from each sensor chip independently, and the image signals output from these sensor chips are sequentially switched to obtain the image signal for one line. When used in combination with each other, since the DC potential of the black dummy bit is different for each sensor, the image signal of each sensor chip is fed back within the interval of each black dummy bit and is in a stable state. However, in the conventional device, the black dummy bit section of the image sensor is much shorter than the other sections as described above, and it becomes extremely short when driven at high speed. There was a problem that it was difficult to give feedback within the section to make it stable.

In view of such a point, the present invention has an object to provide an image signal processing device that can easily process an image signal output from an image sensor with a black dummy bit as a reference. Even when high-speed driving is performed and the image signals are sequentially switched and combined into an image signal for one line, the output of each black dummy bit of the image sensor is set to a predetermined DC potential, and a black dummy for each sensor chip is used. It is an object of the present invention to provide an image signal processing device that can stably clamp even when the DC potential of a bit is different.

Means for Solving the Problems In order to achieve the above object, an image signal processing apparatus according to the present invention provides an image sensor having a black dummy bit and a drive pulse having a first frequency for driving the image sensor. A first driving pulse generating circuit, a second driving pulse generating circuit that generates a driving pulse having a second frequency lower than the first frequency, an output of the first driving pulse generating circuit, and the And a switching means for switching the output to and from the second drive pulse generating circuit.

Further, the image signal processing device according to the present invention provides an image sensor which is provided with a plurality of sensor chips each having a black dummy bit and can independently output a signal from each sensor chip, and an image signal output from each of these sensor chips. Image signal synthesizing means for sequentially switching to obtain an image signal of one line, a first drive pulse generating circuit for generating a first drive pulse having a first frequency for driving an image sensor, and a first frequency A second drive pulse generating circuit for generating a drive pulse having a low second frequency; switching means for switching the output of the first drive pulse generating circuit and the output of the second drive pulse generating circuit; A differential amplifier that receives the image signal from the image signal synthesizing unit as one input, sample holding unit that samples and holds the output signal of the differential amplifier for each pixel, and Hold means for holding the potential of the black dummy bit portion of the output signal of the sample hold means, an error amplifier for amplifying the error between the potential held by the hold means and a predetermined reference voltage, and the output of this error amplifier And a low-pass filter whose output is used as the other input of the differential amplifier.

Operation According to the first aspect of the present invention, the drive pulse for driving the black dummy bit section is given to the image sensor as a frequency lower than the drive pulse for driving the other section, so that the black dummy bit section and the section other than the black dummy bit section are provided. And the time ratio becomes smaller.

According to the second aspect of the invention, the image signal from the image signal synthesizing unit is driven at a low frequency only in the black dummy bit section to extend the image signal in the black dummy bit section in time and sample-hold for each pixel. In the stretched black dummy bit section, the output obtained by amplifying the error between the DC voltage of the black dummy bit and the predetermined reference voltage is input to the differential amplifier with a predetermined time constant, and this input and the image from the image signal combining means are input. The signal is differentially amplified with a predetermined gain of the signal, sampled and held again for each pixel, and input to the holding means to output the black dummy bit.
Feedback is applied to eliminate the error between the DC voltage and the specified reference voltage. That is, when the DC voltage of the black dummy bit is lower than the predetermined reference voltage, that is, the clamp voltage,
Feedback is applied to increase the DC voltage of the black dummy bit. If the DC output voltage of the black dummy bit is higher than a predetermined reference voltage, that is, the clamp voltage, feedback is applied to decrease the DC voltage of the black dummy bit.

When the black dummy bit section of the image signal ends,
The output of the sample and hold means, that is, the DC voltage of the black dummy bit fed back so as to eliminate the error from the predetermined reference voltage as described above, is held by the hold means, and the section other than the black dummy bit is held. An output obtained by amplifying an error between the voltage and a predetermined reference voltage is input to a differential amplifier with a predetermined time constant, the input and the image signal from the image signal combining means are differentially amplified with a predetermined gain, and each pixel is again amplified. It samples and holds each time and outputs it to the circuit in the subsequent stage.

Then, by only adjusting the frequency of the second drive pulse generating circuit and setting the time of the black dummy bit so that the feedback can be stably applied, the plurality of image sensors are driven at high speed and the image signals are sequentially switched to 1 Even when the image signal combined with the line image signal is handled, the output of each black dummy bit of each image sensor can be stabilized at a predetermined DC voltage without slowing the transfer rate other than the black dummy bit section of the image sensor. It can then be clamped.

Embodiment FIG. 1 is a block diagram showing an embodiment of an image signal processing device according to the first invention, and FIG. 2 is a waveform diagram of each part of this embodiment.

In FIG. 1, 1 is an image sensor having a black dummy bit, and 2 and 3 are frequencies f1 and f2 (where f1>
At f2), first and second drive pulse generation circuits 4 for generating drive pulses for the image sensor select drive pulses to be given to the image sensor from the outputs of the first and second drive pulse generation circuits 2, 3. Switching control means 5 for outputting a switching signal for switching the switching outputs of the first and second drive pulse generation circuits 2 and 3 according to the output of the switching control means 4, and 6 is a driver for driving the image sensor. , 7 is a sample and hold circuit that samples and holds the output of the image sensor 1 at a proper time, 8 is a clamp circuit that clamps the output of the sample and hold circuit 7 to a reference voltage by AC coupling, and includes a capacitor 8a, an analog switch 8b,
It is composed of a reference voltage source 8c. Reference numeral 9 is a pulse generating means for supplying necessary pulses to the sample and hold circuit 7 and the clamp circuit 8, 10 is a buffer for buffering the output of the clamp circuit 8, and 11 is an A / D converter for A / D converting the output of the buffer 10.
It is a converter.

FIG. 2 shows a detailed configuration example of the switching control means 4. The switching control means 4 includes a counter 12 and an RS flip-flop 13
It consists of and. The counter 12 is reset by a start pulse given to the image sensor every time one line is scanned, and counts the first drive pulse. The value K to be counted up by the counter 12 is set to the number of the first drive pulses corresponding to the period in which the second drive pulse is applied to the black dummy bit of the image sensor. The RS flip-flop 13 is set by the start pulse, holds the Q output at the H level, is reset by the count-up signal of the counter 12, and sets the Q output at the L level.
Turn to a level. Therefore, the Q output is at the H level while the black dummy bit of the image sensor is driven by the second drive pulse, and the L output is L while the bits other than the black dummy bit are driven by the first drive pulse.
To be kept at a level. In the waveform of FIG. 4, (c) shows this Q output. This Q output is the switching means 5 shown in FIG.
Given to. The switching means 5 is composed of two AND circuits 15 and 16 and an OR circuit 17 in this example. AND circuit 1
5 opens the gate when the Q output becomes H level,
Drive pulse of. On the other hand, the AND circuit 16 opens the gate when the Q output becomes L level, and passes the first drive pulse. The drive pulse output from the two AND circuits 15 and 16 is given to the driver 6 through the OR circuit 17.

The operation of the image signal processing apparatus of this embodiment constructed as above will be described below.

First, the first drive pulse generation circuit 2 produces a pulse of frequency f1 as shown in FIG. 4 (a), and the second drive pulse generation circuit 3 produces a pulse of frequency f2 as shown in FIG. 4 (b). A pulse (however, f1> f2) is generated and input to the switching means 5.

The switching control means 4 generates a control signal shown in FIG. 4 (c) by the start pulse and the drive pulse from the first pulse generating circuit 2 and gives it to the switching means 5. This signal (c)
As a result, the switching means 5 supplies the driver 6 with a pulse having a low frequency only during the black dummy bit section as shown in FIG. 4 (d). The driver 6 adjusts the pulse supplied from the switching means 5 to the pulse input level of the image sensor 1 and supplies the drive pulse having the timing shown in FIG. 4 (d) to the image sensor 1. Then, the image sensor 1 outputs an image signal which is temporally stretched by the black dummy bit section as shown in FIG. 4 (e). The sample hold circuit 7 is a pulse generating means 9 shown in FIG.
The image signal from the image sensor 1 is sampled and held for each pixel in accordance with the control signal input from the image sensor 1 and the image signal as shown in FIG. The clamp circuit 8 turns on the analog switch 8b while the control signal input from the pulse generating means shown in FIG. 4 (h) is "1" to turn on the black dummy bit section of the image signal from the sample hold circuit 7. The capacitor 8a is charged and discharged so that the signal level becomes the reference voltage of the reference voltage source 8c (for example, the reference voltage of the A / D converter 11). Further, while the control signal input from the pulse generating means 9 shown in FIG. 4 (h) is "0", the analog switch 8b is turned off and the capacitor is turned on.
The voltage level of 8a is held in the above state, that is, the signal level of the black dummy bit section of the image signal becomes the reference voltage of the reference voltage source 8c, and the image signal is input to the buffer 10. The buffer 10 A / Ds the image signal from the clamp circuit 8.
Input to the converter 11. The signal generated by the switching control means 4 (FIG. 4 (c)) can be used as it is as the control signal of the pulse generation means 9.

As described above, in this embodiment, it is possible to prolong only the black dummy bit section of the image sensor 1, that is, only the charging / discharging time of the capacitor 8a of the clamp circuit 8, so that the black dummy bit section and other sections. It is possible to reduce the time ratio with. Therefore, it is possible to configure the image signal processing device that can easily determine the capacitance of the capacitor used for the clamp and can easily process the image signal of the image sensor with the black dummy bit as a reference.

FIG. 5 is a block diagram showing an embodiment of the image signal processing apparatus in the second invention, and FIG. 6 is a waveform diagram of each part of this embodiment.

In FIG. 5, 21 is a first image sensor having a black dummy bit, 22 is a first image sensor having a black dummy bit, and 23 and 24 are frequencies f1 and f2 (however,
The first to generate the drive pulse of the image sensor when f1> f2)
And a second pulse generating circuit, 25 is a switching control means for outputting a switching signal for selecting a drive pulse to be applied to the image sensor from the outputs of the first and second pulse generating circuits 23 and 24, and 26 is a switching control. Switching means for switching the outputs of the first and second drive pulse generation circuits 23, 24 by the output of the means 25, and 27 for the first and second image sensors 21, 22 using the pulse from the switching means 26 as a reference pulse. Drive pulse generating means for generating a pulse for driving the image sensor, 28 a driver for driving the image sensor, and 29 an image signal for one line by sequentially switching the output image signals of the first image sensor 21 and the second image sensor 22. An image signal synthesizing means for outputting a signal, and 30 is a difference for differentially amplifying with a gain A using an image signal from the image signal synthesizing means 29 as a non-inverting input and an output of a second low-pass filter described later as an inverting input A dynamic amplifier 31 is a sample and hold means for sampling and holding an image signal containing a black dummy bit amplified by the differential amplifier 30 for each pixel, and is composed of an analog switch 31a and a capacitor 31b. 32 is a first buffer amplifier, 33 is a first low-pass filter, and 34 is a second buffer amplifier. 35 is the second
Is a holding means for detecting and holding the DC potential of the black dummy bit part of the output of the buffer amplifier 34, and is composed of an analog switch 35a and a capacitor 35b. 36 is a third buffer amplifier, 37 is an error amplifier that subtracts a predetermined reference voltage from the output of the third buffer amplifier 36, and amplifies with a gain B, and 38 is a DC power supply that supplies this predetermined reference voltage.
39 excludes unnecessary high frequency components of the output of the error amplifier 37,
This is a second low-pass filter for maintaining the stability of the circuit, and is composed of a resistor 39a and a capacitor 39b. Reference numeral 40 is an A / D converter for analog / digital converting the output of the second buffer amplifier 34, and reference numeral 41 is a pulse generating means for supplying necessary pulses to the sample and hold means 31 and the hold means 35. Since the switching control means 25 and the switching means 26 can be constructed with the configuration described in the first embodiment as a main part, the description thereof will be omitted.

The operation of the image signal processing apparatus of this embodiment will be described next.

First, the first pulse generation circuit 23 generates a pulse of frequency f1 as shown in FIG. 6 (a), and the second pulse generation circuit 23
24 generates a pulse of frequency f2 (however, f1> f2) as shown in FIG. 6 (b) and inputs it to the switching means 26. The switching control means 25 uses the information (start pulse and drive pulse) from the first pulse generation circuit 23 to supply the pulse supplied by the switching means 26 to the drive pulse generation means 27 at the head of the black dummy bit. 23 to the second pulse generation circuit
The control signal shown in FIG. 6 (c) is applied to the switching means 26 so as to switch to 24 and switch from the second pulse generating circuit 24 to the first pulse generating circuit 23 at the end of the black dummy bit. By this operation, the switching means 26 becomes the drive pulse generating means.
A pulse having a low frequency is supplied to 27 as shown in FIG. 6 (d) only during the black dummy bit section. The drive pulse generating means 27 supplies a pulse for driving the first and second image sensors 21 and 22 (not shown) to the driver 28 using the input pulse as a reference pulse. The driver 28 adjusts the pulse supplied from the drive pulse generating means 27 to the pulse input levels of the first and second image sensors 21 and 22 and outputs the drive pulse in accordance with the timing shown in FIG. 6 (d). The image is supplied to the first and second image sensors 21 and 22. Then, the first and second image sensors 21 and 22 output the image signals extended by the black dummy bit intervals as shown in FIGS. 6 (e) and 6 (f), respectively. At this time, the read image signals are alternated to the first and second image sensors 21 and 22 so that no inconvenience occurs when they are combined by the image signal combining means 29 and combined into the image signal of one line. The drive pulse that is read out is generated by the drive pulse generating means 27. The image signal synthesizing means 29 is supplied with a control signal for switching the image signal of each image sensor from the switching control means 25 at the beginning of the black dummy bit of each image sensor as shown in FIG. The signals of the second image sensors 21 and 22 are switched, and when the control signal is "1", the image signal of the first image sensor 21 is changed to "0".
At the time of, the image signal of the second image sensor 22 is selected and the image signal combined into one line as shown in FIG. 6 (h) is output. At this time, the frequency of the second pulse generating circuit 24 can be arbitrarily changed.

The differential amplifier 30 amplifies the image signal combined into one line from the image signal combining means 29 with a gain A and inputs it to the sample hold means 31. The sample and hold means 31 samples and holds the image signal containing the black dummy bits amplified by the pulse supplied from the pulse generation means 41 for each pixel and outputs the image signal as shown in FIG. 6 (i) to the first buffer. It is input to the first low-pass filter 33 via the amplifier 32. Then, the first low-pass filter 33 removes the switching noise generated at the time of sample hold, and FIG. 6 (j)
The image signal as shown in (1) is input to the holding means 35 via the second buffer amplifier 34. The holding means 35 is supplied with a signal "1" (FIG. 6 (k)) from the pulse generating means 41 at the head of the black dummy bit of the image signal, and turns on the analog switch 35a to turn on the second buffer amplifier 34. And the third buffer amplifier 36 are connected. Then, the third buffer amplifier 36 inputs the output voltage of the black dummy bit to the non-inverting input terminal of the error amplifier 37. In the error amplifier 37, the voltage of the DC power source 38 is subtracted from the output voltage of the black dummy bit input from the third buffer amplifier 36, and the voltage multiplied by B is input to the differential amplifier 30 via the second low-pass filter 39. Input to the terminal. At this time, the voltage of the DC power supply 38 is set to the reference voltage of the A / D converter 40. The second low pass filter 39 keeps the stability of the circuit except the unnecessary high frequency component of the output of the error amplifier 37.

Then, in the differential amplifier 30, the input voltage of the image signal from the image signal synthesizing means 29 and the input voltage from the second low pass filter 39 are differentially amplified by the gain A, and the sample and hold means is provided.
The image signal input from the differential amplifier 30 is sampled and held by the sample-hold means 31 as described above, and the image signal is input to the first buffer amplifier 32, the first low-pass filter 33, and the second buffer. It is input again to the holding means 35 via the amplifier 34 and the above-mentioned operation is repeated to perform feedback so that the error between the output voltage of the black dummy bit and the voltage of the DC power supply 38 is minimized.

The hold means 35 has a second buffer amplifier 34.
At the end of the black dummy bit section of the image signal inputted from the pulse generator 41, the signal "0" (FIG. 6 (k)) is supplied, the analog switch 35a is turned off and the second signal at that time is output. The output of the buffer amplifier 34, that is, the DC voltage of the black dummy bit fed back so as to eliminate the error from the voltage of the DC power source 38 as described above is held in the capacitor 35b. The third buffer amplifier 36 is this capacitor 35b
The voltage held at is input to the non-inverting input terminal of the error amplifier 37. In the error amplifier 37, a voltage obtained by subtracting the voltage of the DC power source 38 from the voltage held by the capacitor 35b input from the third buffer amplifier 36 and multiplying it by B is applied to the differential amplifier 30 via the second low pass filter 39. Input to the inverting input terminal of. At this time, the voltage held in the capacitor 35b is a voltage that minimizes the error between the output voltage of the black dummy bit and the voltage of the DC power supply 38.

Then, in the differential amplifier 30, the input voltage of the image signal from the image signal synthesizing means 29 and the input voltage from the second low pass filter 39 are differentially amplified by the gain A, and the sample and hold means is provided.
The image signal input from the differential amplifier 30 is sampled and held by the sample-hold means 31 as described above, and the image signal is input to the first buffer amplifier 32, the first low-pass filter 33, and the second buffer. A / D via amplifier 34
Input to the converter 40.

As described above, in this embodiment, in the black dummy bit section, the output voltage of the black dummy bit of the second buffer amplifier 34 is the DC reference voltage of the A / D converter 40.
When the voltage is higher than the voltage of the power supply 38, the output voltage of the error amplifier 37 is increased and the output voltage of the differential amplifier 30 is decreased to change the output voltage of the black dummy bit of the second buffer amplifier 34 to the A / D converter 40. When the feedback is applied so as to clamp the reference voltage and the output voltage of the black dummy bit of the second buffer amplifier 34 is smaller than the voltage of the DC power supply 38 which is the reference voltage of the A / D converter 40, the error amplifier 37
Output voltage of the differential amplifier 30 is increased to increase the output voltage of the black dummy bit of the second buffer amplifier 34.
Feedback is applied to clamp to the A / D converter reference voltage. And the second pulse generation circuit
By adjusting the frequency of the pulse generated by 24 and setting the time of the black dummy bit so that stable feedback can be applied, multiple image sensors are driven at high speed,
Even when the image signals are sequentially switched and the image signal combined into the image signal of one line is handled, the transfer speed other than the black dummy bit section of the image sensor is not slowed down and the black dummy bit of each image sensor is not changed. Predetermined output
The DC voltage can be easily and stably clamped to the difference in the DC voltage of the black dummy bid of each image sensor.

As described above, according to the first invention, only the black dummy bit section of the image signal output from the image sensor,
Only the charging / discharging time of the capacitor used in the clamp circuit can be extended, so the time ratio between the black dummy bit section and other sections can be reduced, and the capacity of the capacitor used for clamping can be easily determined. The image signal of the image sensor can be easily processed with the black dummy bit as a reference.

Further, according to the second aspect of the present invention, by adjusting the frequency of the pulse generated by the second drive pulse generating circuit and setting the time of the black dummy bit such that stable feedback can be applied, a plurality of image sensors can be obtained. Even when the image signals combined with the one-line image signals by sequentially driving the image signals by sequentially switching the image signals are handled without slowing down the transfer speed other than the black dummy bit of the image sensor, It is possible to easily and stably clamp the output of the black dummy bit to a predetermined DC voltage even with respect to the difference in the DC voltage of the black dummy bit for each image sensor. Therefore, its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image signal processing device in the first invention, and FIG. 2 is a structural example of a switching control means,
FIG. 3 is a diagram showing an example of the configuration of the switching means, FIG. 4 is a waveform diagram of each part of the device, FIG. 5 is a block diagram showing an embodiment of the image signal processing device in the second invention, and FIG. The figure is a waveform diagram of each part of the apparatus. 1 ... Image sensor, 2 ... First drive pulse generation circuit, 3 ... Second drive pulse generation circuit, 4 ... Switching control means, 5 ... Switching means, 8 ... Clamp circuit, 21 ... First image sensor, 22 ... Second image sensor, 23
...... First pulse generating circuit, 24 ...... Second pulse generating circuit, 25 ...... Switching control means, 26 ...... Switching means, 27 ...... Drive pulse generating means, 29 ...... Image signal synthesizing means, 30 ... … Differential amplifier, 31 …… Sample hold means, 35 …… Hold means, 37 …… Error amplifier, 39 …… Second low-pass filter.

Claims (2)

(57) [Claims] 1. An image sensor having a black dummy bit, and a first drive pulse generation circuit for generating a drive pulse having a first frequency for driving the image sensor,
A second drive pulse generation circuit that generates a drive pulse having a second frequency lower than the first frequency, an output of the first drive pulse generation circuit, and an output of the second drive pulse generation circuit Switching means for switching the black dummy bit section with the drive pulse generated by the second drive pulse generation circuit, and the section other than the black dummy bit section with the drive pulse generated by the first drive pulse generation circuit. An image signal processing device driving the image sensor. 2. An image sensor in which a plurality of sensor chips each having a black dummy bit are provided and a signal can be independently output from each sensor chip, and an output image signal from each of these sensor chips is sequentially switched to display one line image. An image signal synthesizing unit for obtaining a signal, a first drive pulse generating circuit for generating a first drive pulse having a first frequency for driving the image sensor, and a second frequency lower than the first frequency are provided. A second drive pulse generating circuit for generating a drive pulse having the same; an output of the first drive pulse generating circuit;
Switching means for switching the output to and from the drive pulse generating circuit, a differential amplifier that receives the image signal from the image signal combining means as one input, and a sample hold that samples and holds the output signal of the differential amplifier for each pixel. Means, a holding means for holding the potential of the black dummy bit portion of the output signal of the sample and hold means, an error amplifier for amplifying an error between the potential held by the holding means and a predetermined reference voltage, and this error amplifier. And a low-pass filter that receives the output of the low-pass filter as the other input of the differential amplifier.