JP2927837B2 - Photoelectric conversion device output signal detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photoelectric conversion device having a plurality of photoelectric conversion elements whose charge amount is an output signal and a driving circuit for driving these photoelectric conversion elements. The present invention relates to a photoelectric conversion device output signal detection device for detecting an amount of charge output in time series from a photoelectric conversion element.

[Conventional technology]

2. Description of the Related Art Conventionally, there is a line sensor or the like as a photoelectric conversion device having a plurality of photoelectric conversion elements that output a charge amount as an output signal and a driving circuit for driving the photoelectric conversion elements.

Also, the photoelectric conversion device output signal detection device divides the path of the output current signal of the photoelectric conversion device so that noise is evenly included, and converts the current signal of each path into a voltage by a resistor,
Performing these differential amplifications reduces noise,
The polarity of the signal is made uniform by polarity switching, and the signal is output as a relatively stable signal for a certain period of time by integration or peak hold. Noise that could not be removed due to DC offset and noise imbalance was removed by manual adjustment.

In another photoelectric conversion device output signal detection device, the output current signal of the photoelectric conversion device is converted into a voltage by a low input impedance amplifier including a grounded base circuit of a bipolar transistor, and an external noise reduction signal is added thereto. After the noise is reduced, the signal is output as a relatively stable signal for a certain period of time by integration or peak hold. The setting of the DC offset and the noise reduction signal is performed by manual adjustment.

[Problems to be solved by the invention]

In the above-described photoelectric conversion device output signal detection device, the signal is relatively stabilized for a certain period of time by integration or peak hold. However, this cannot be said to be sufficient to stabilize the signal, and furthermore, there is no reduction in DC offset or noise. The adjustment could not be done.

The present invention improves the above disadvantages, reduces the influence of external noise, and can sufficiently stabilize the signal.
It is another object of the present invention to provide a photoelectric conversion device output signal detection device capable of reducing a DC offset and a clock noise without adjustment.

[Means for solving the problem]

In order to achieve the above object, the present invention is directed to a photoelectric conversion device including a plurality of photoelectric conversion elements each having a charge amount as an output signal and a driving circuit for driving these photoelectric conversion elements. A low input impedance differential current-to-voltage conversion circuit for converting a current of a difference between a signal input through a signal line in a series and a dummy signal input from a dummy line into a voltage, and the differential current-to-voltage conversion circuit An integration circuit that integrates the output signal of each bit for each bit, a sample and hold circuit that samples and holds the output signal of this integration circuit for each bit, and automatically reduces the DC offset of the output signal of this sample and hold circuit DC offset reducing circuit, and clock noise reduction for automatically reducing clock noise of the output signal of the sample and hold circuit A negative feedback of a DC offset reduction signal from the DC offset reduction circuit to an input side of the differential current / voltage conversion circuit, and a clock noise reduction signal from the clock noise reduction circuit to the differential current / voltage conversion circuit. The negative feedback is applied to the input side of.

[Operation] A difference between a signal input from a plurality of photoelectric conversion elements in a photoelectric conversion device through a signal line in time series and a dummy signal input from a dummy line by a differential current / voltage conversion circuit having an input impedance. Is converted to a voltage, the integration circuit integrates the output signal of the differential current-voltage conversion circuit for each bit, and the sample and hold circuit samples and holds the output signal of the integration circuit for each bit. The DC offset reduction circuit negatively feeds back the DC offset reduction signal to the input side of the differential current-to-voltage conversion circuit to automatically reduce the DC offset of the output signal of the sample and hold circuit, and the clock noise reduction circuit reduces the clock noise reduction signal. Negative feedback is provided to the input side of the differential current / voltage conversion circuit to automatically reduce the clock noise of the output signal of the sample and hold circuit.

〔Example〕

 FIG. 1 shows an embodiment of the present invention.

In the figure, 11 is a low input impedance differential current-to-voltage conversion circuit, 12 is an integration circuit that resets and integrates each bit, 13 is a sample and hold circuit, 14 is a DC offset reduction circuit, and 15 is a clock noise reduction circuit. , IN- is a photoelectric conversion device having a plurality of photoelectric conversion elements and the drive circuit for driving these photoelectric conversion elements and the amount of charge as an output signal,
For example, an input terminal connected to the a-Si line sensor via a signal line, IN + is an input terminal connected to a dummy line arranged close to the signal line, and OUT is an output terminal.

A differential current-to-voltage conversion circuit 11 converts a difference current between a signal input from a plurality of photoelectric conversion elements in the photoelectric conversion device through a signal line in time series and a dummy signal input from a dummy line to a voltage. External noise such as hum and stepping motor driving noise that are evenly mixed into the signal line and the dummy line is reduced in the output signal of the differential current / voltage conversion circuit 11 by the common mode rejection ratio of the differential current / voltage conversion circuit 11. ing. The output signal of the differential current / voltage conversion circuit 11 is integrated for each bit by the integration circuit 12, but does not settle to a constant value due to a DC offset, noise, or the like. The output signal of the integrating circuit 12 is sampled and held for each bit by the sample and hold circuit 13, and each bit section becomes a constant voltage. The output signal of the sample-and-hold circuit 13 is output from an output terminal OUT. The DC offset reduction circuit 14 detects the DC offset of the output signal of the sample-and-hold circuit 13 and outputs a DC offset reduction signal corresponding to the DC offset to the differential current. Negative feedback is performed on the input side of the voltage conversion circuit 11 so that the DC offset is reduced. Further, the clock noise reduction circuit 15 detects the clock noise of the output signal of the sample and hold circuit 13 and outputs a clock noise reduction signal corresponding to the clock noise to the input side of the differential current / voltage conversion circuit 11 so that the clock noise is reduced. Negative feedback.

 FIG. 2 shows a specific configuration of this embodiment.

In the figure, 16 is a feedback amplifier, 17 is a sample and hold circuit for detecting a DC offset, 18 is a voltage-current conversion circuit, 19 is a sample and hold circuit for detecting clock noise, and 20 is a circuit for generating a noise reduction signal. Is a voltage-to-charge conversion circuit.

A differential current-voltage conversion circuit 11, an integration circuit 12, and a sample hold circuit 13 are a charge detection circuit for outputting a voltage that is proportional to a current (charge amount) as an output signal of the a-Si line sensor and that is stable for a certain period of time. Is composed. The differential current / voltage conversion circuit 11 removes external noise input to the input terminals IN− and IN + in the same phase, converts the output signal of the a-Si line sensor into a voltage, and outputs the voltage. The integration circuit 12 is reset for each bit, integrates the output signal of the differential current / voltage conversion circuit 11, and outputs a voltage signal proportional to the input charge amount for each bit. However, it is difficult to make the output signal of the integrating circuit 12 a stable voltage signal for a certain time due to DC offset, noise, and the like. The sample and hold circuit 13 is an integration circuit 12
The output signal is sampled and held for each bit, so that the hold section becomes a stable voltage signal. However, the output signals of the charge detection circuits 11 to 13 are DC offset due to DC offset of each block of the charge detection circuits 11 to 13, noise at the time of reset at the integration circuit 12, noise generated at the time of holding at the sample and hold circuit 13, and the like. Occurs. Also, clock noise is mixed in the signal from the a-Si line sensor.

The DC offset is reduced in the output signals of the charge detection circuits 11 to 13 by a DC offset reduction circuit 14 composed of a feedback amplifier 16, a sample hold circuit 17, and a voltage-current converter 18. In the DC offset reduction circuits 16 to 18, a
In a no-signal section in which the output signal of the Si line sensor is a no-signal, the output signals of the charge detection circuits 11 to 13 are amplified by the feedback amplifier 16 and the average value (DC offset) is sampled by the sample-and-hold circuit 17 . The output signal of this sample-and-hold circuit 17 is a voltage-current converter
The signal is converted into a current signal suitable for the input of the differential current / voltage conversion circuit 11 by the signal 18, and is negatively fed back to the input side of the differential current / voltage conversion circuit 11. This negative feedback reduces the DC offset of the output signals of the charge detection circuits 11 to 13. In the signal output section where the output signal of the a-Si line sensor is output, the feedback amplifier 16 disconnects the input side and outputs 0 V, the sample hold circuit 17 enters the hold mode, and the DC offset in the non-signal section is reduced. The reduced state is maintained, and the DC offset of the output signals of the charge detection circuits 11 to 13 is reduced.
Here, the feedback amplifier 16 is a low-offset, high-gain amplifier in the non-signal section, and 0 V in the signal output section.
Is output.

The clock noise is reduced by the feedback amplifier 16, the sample and hold circuit 17, the sample and hold circuit 19, and the multiplier 20.
And a clock noise reduction circuit 15 composed of a voltage-to-charge conversion circuit 21. Sample hold circuit 19
Samples the output signal of the amplifier 16 every other bit in the non-signal section and holds it in the signal section. The multiplier 20 is a sample and hold circuit 17
Is multiplied by the difference between the output signal of the sampler and the output signal of the sampler hold circuit 19 and the clock CK, which is the source of clock noise mixed into the output signal of the a-Si line sensor, and
A clock synchronization signal having an amplitude proportional to the clock noise at OUT is generated. This clock synchronization signal is converted into a charge amount by the voltage-to-charge conversion circuit 21 and is negatively fed back to the input side of the differential current-to-voltage conversion circuit 11. Due to this negative feedback, the clock noise at the output terminal OUT is reduced. In the signal section, the reduced state of the clock noise in the non-signal section is maintained, and the clock noise is reduced over the entire time.

According to this embodiment, a difference current between a signal input from a plurality of photoelectric conversion elements in an a-Si line sensor via a signal line in time series and a dummy signal input from a dummy line is a differential current. A hum, which is converted into a voltage by the voltage conversion circuit 11 and is equally mixed into the signal line and the dummy line,
External noise such as stepping motor driving noise is reduced in the output signal of the differential current-to-voltage conversion circuit 11 by the common mode rejection ratio of the differential current-to-voltage conversion circuit 11, so that the effect of the external noise on the output signal is reduced. Can be. Also,
Since the output signal of the differential current / voltage conversion circuit 11 is integrated for each bit by the integration circuit 12 and sampled and held for each bit by the sample and hold circuit 13, a-Si
As compared with the output charge amount of the line sensor, it is possible to output a stable signal with less fluctuation for a certain period of time. Also,
Since the DC offset reduction circuit 14 is used, a detection signal with a small DC offset can be obtained without adjustment. further,
Since the clock noise reduction circuit 15 is used, a detection signal with little clock noise can be obtained without adjustment.

 FIG. 3 shows another embodiment of the present invention.

In this embodiment, a waveform shaping circuit 22 including an active filter and a variable gain amplifying circuit 23 are added to the above embodiment, and the same parts as those in the above embodiment are denoted by the same reference numerals.

The active filter 22 shapes the output signal of the differential current-to-voltage conversion circuit 11 to suppress sharp changes in the waveform, and suppresses the peak value.
In addition, the frequency band and the slew rate required for the above are reduced, and the limitation of the dynamic range due to the power supply voltage is reduced. The output signal of the active filter 22 is amplified by the variable gain amplifier 23 and output to the integration circuit 12.

〔The invention's effect〕

As described above, according to the present invention, in a time series from the plurality of photoelectric conversion elements in a photoelectric conversion device having a plurality of photoelectric conversion elements having a charge amount as an output signal and a drive circuit for driving these photoelectric conversion elements. A low input impedance differential current / voltage conversion circuit for converting a difference current between a signal input through a signal line and a dummy signal input from a dummy line into a voltage, and an output of the differential current / voltage conversion circuit An integrating circuit for integrating a signal for each bit, a sample and hold circuit for sampling and holding an output signal of the integrating circuit for each bit, and a DC for automatically reducing a DC offset of an output signal of the sample and hold circuit An offset reduction circuit; and a clock noise reduction circuit that automatically reduces clock noise of an output signal of the sample and hold circuit. For example, the DC from the offset reduction circuit the DC offset reduction signal the differential current at a voltage of is negatively fed back to the input side of the converter, the DC offset of the output signal is automatically reduced.

Further, since the clock noise reduction signal is negatively fed back from the clock noise reduction circuit to the input side of the differential current / voltage conversion circuit, the clock noise of the output signal is automatically reduced.

As described above, the influence of external noise can be reduced, and the DC offset and the clock noise can be reduced without adjustment. Furthermore, since the signal is sampled and held for each bit by the sample and hold circuit after the integration circuit, the signal level in one pixel can be sufficiently stabilized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram specifically showing the embodiment, and FIG. 3 is a block diagram showing another embodiment of the present invention. 11 …… Differential current-voltage conversion circuit, 12 …… Integration circuit, 13 ……
Sample hold circuit, 14 DC offset reduction circuit, 15 Clock noise reduction circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01J 1/44 G01R 19/00

Claims (1)

(57) [Claims] 1. A photoelectric conversion device comprising: a plurality of photoelectric conversion elements each having a charge amount as an output signal; and a drive circuit for driving these photoelectric conversion elements. A low-input impedance differential current-to-voltage conversion circuit that converts the current of the difference between the signal input to the dummy line and the dummy signal input from the dummy line to a voltage, and outputs the output signal of the differential current-to-voltage conversion circuit to each bit An integration circuit that integrates each time, a sample and hold circuit that samples and holds the output signal of the integration circuit for each bit, and a DC offset reduction circuit that automatically reduces the DC offset of the output signal of the sample and hold circuit. A clock noise reduction circuit that automatically reduces clock noise of an output signal of the sample-and-hold circuit, The DC offset reduction signal is negatively fed back to the input side of the differential current / voltage conversion circuit from the offset reduction circuit, and the clock noise reduction signal is negatively fed back to the input side of the differential current / voltage conversion circuit from the clock noise reduction circuit. A photoelectric conversion device output signal detection device, characterized in that: