JP2009182204A - Substrate fitting structure - Google Patents
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- JP2009182204A JP2009182204A JP2008020732A JP2008020732A JP2009182204A JP 2009182204 A JP2009182204 A JP 2009182204A JP 2008020732 A JP2008020732 A JP 2008020732A JP 2008020732 A JP2008020732 A JP 2008020732A JP 2009182204 A JP2009182204 A JP 2009182204A
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Abstract
Description
本発明は、各種電子機器においてシャーシ上に多層基板を取り付ける基板取り付け構造に関するものである。 The present invention relates to a board mounting structure for mounting a multilayer board on a chassis in various electronic devices.
従来、携帯端末機等の各種電子機器において、金属製のシャーシ上に多層基板を設置して、多層基板から発生する電磁波ノイズをシャーシによって遮断する基板取り付け構造が提案されている(例えば特許文献1参照)。 Conventionally, in various electronic devices such as portable terminals, a board mounting structure has been proposed in which a multilayer board is installed on a metal chassis and electromagnetic noise generated from the multilayer board is blocked by the chassis (for example, Patent Document 1). reference).
例えば、図3に示す基板取り付け構造においては、図示の如く、シャーシ(4)に突設したボス部(41)上に多層基板(10)が設置され、該多層基板(10)はビス(5)によってシャーシ(4)のボス部(41)にねじ止め固定されている。 For example, in the board mounting structure shown in FIG. 3, a multilayer board (10) is installed on a boss portion (41) projecting from the chassis (4), and the multilayer board (10) is screwed (5). ) To the boss portion (41) of the chassis (4).
多層基板(10)は、互いに積層された複数の絶縁層(11)〜(15)を具え、各絶縁層の表面や背面には、グランド層や回路パターンとなる複数の導体パターン(20)〜(25)が形成されている。又、複数の絶縁層(11)〜(15)には、ビア(31)〜(35)が形成されて、複数の導体パターン(20)〜(25)を互いに接続している。 The multilayer substrate (10) includes a plurality of insulating layers (11) to (15) stacked on each other, and a plurality of conductor patterns (20) to (20) to be ground layers and circuit patterns on the front and back surfaces of each insulating layer. (25) is formed. Further, vias (31) to (35) are formed in the plurality of insulating layers (11) to (15), and the plurality of conductor patterns (20) to (25) are connected to each other.
図3に示す基板取り付け構造においては、表面の導体パターン(25)と内層の導体パターン(21)〜(24)とがビア(31)〜(35)を介して背面の導体パターン(20)と接続され、該背面導体パターン(20)がシャーシ(4)のボス部(41)と接触することによって、複数の導体パターン(20)〜(25)がシャーシ(4)に接続されている。
該基板取り付け構造によれば、シャーシ(4)のシールド効果によって多層基板(10)から発生する電磁波ノイズがシールドされることになる。
According to the board mounting structure, electromagnetic noise generated from the multilayer board (10) is shielded by the shielding effect of the chassis (4).
図4は、上記多層基板(10)の複数の導体パターン(21)〜(25)に関する等価回路図を表わしている。複数の導体パターン(21)〜(25)には電源(7)が接続され、各絶縁層に形成されているビア(31)〜(35)が、電源(7)のアース側に介在する抵抗R1〜R5となっている。
ところが、1つのビアは例えば80mΩ程度の抵抗値を有するため、各抵抗R1〜R5に電位差が生じ、この結果、各導体パターン(21)〜(25)のインピーダンスが充分に下がらない問題があった。
FIG. 4 shows an equivalent circuit diagram relating to the plurality of conductor patterns (21) to (25) of the multilayer substrate (10). A power source (7) is connected to the plurality of conductor patterns (21) to (25), and vias (31) to (35) formed in the respective insulating layers are resistors interposed on the ground side of the power source (7). R1 to R5.
However, since one via has a resistance value of about 80 mΩ, for example, there is a potential difference between the resistors R1 to R5. As a result, there is a problem that the impedance of each of the conductor patterns (21) to (25) is not sufficiently lowered. .
尚、図3に示す多層基板(10)の表面の導体パターン(25)は、ビス(5)を介してシャーシ(4)に接続されるため、該導体パターン(25)のインピーダンスはある程度まで下げることが可能であるが、例えば内層の1つの導体パターン(23)が特にインピーダンスを下げる必要のあるものであったとしても、ビス(5)は該導体パターン(23)のインピーダンスを下げる役割を充分に果たすものではない。
従来は、インピーダンスを下げる必要性の高い内層の導体パターン(23)については、該導体パターン(23)をシャーシ(4)と接続するためのビアを増設することが行なわれているが、ビアの増設によって製造コストが増大する問題があった。
Since the conductor pattern (25) on the surface of the multilayer substrate (10) shown in FIG. 3 is connected to the chassis (4) via the screw (5), the impedance of the conductor pattern (25) is lowered to some extent. Although it is possible, for example, even if one conductor pattern (23) in the inner layer needs to lower the impedance in particular, the screw (5) is sufficient to lower the impedance of the conductor pattern (23). It is not what you do.
Conventionally, with respect to the inner layer conductor pattern (23) which is highly required to lower the impedance, vias for connecting the conductor pattern (23) to the chassis (4) have been added. There is a problem that the manufacturing cost increases due to the expansion.
又、図3に示す基板取り付け構造においては、多層基板(10)の表面に沿って電池パック(6)等の部品を設置する場合、多層基板(10)の表面からビス(5)の頭部(51)が突出しているため、多層基板(10)と電池パック(6)との間には隙間が生じざるを得ず、この結果、電子機器の薄型化に支障が生じる問題があった。 In addition, in the board mounting structure shown in FIG. 3, when a component such as a battery pack (6) is installed along the surface of the multilayer board (10), the head of the screw (5) from the surface of the multilayer board (10). Since (51) protrudes, there must be a gap between the multilayer substrate (10) and the battery pack (6), and as a result, there is a problem in that the electronic device can be made thin.
そこで本発明の目的は、ビアを増設することなく特定の内層導体パターンのインピーダンスを下げることが出来、然も機器の薄型化を図ることが出来る基板取り付け構造を提供することである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a board mounting structure that can reduce the impedance of a specific inner layer conductor pattern without adding vias and can reduce the thickness of the device.
本発明に係る基板取り付け構造は、少なくとも表層部が導電性を有するシャーシ(4)と、該シャーシ(4)上にビス(5)によって固定された多層基板(1)とから構成され、該多層基板(1)は、積層された複数の絶縁層を具え、該複数の絶縁層の内、内層に位置する少なくとも1つの絶縁層を含む複数の絶縁層の表面又は背面若しくは両面に、グランド層若しくは電気回路となる複数の導体パターンが形成されている。 A substrate mounting structure according to the present invention includes a chassis (4) having at least a surface layer portion having conductivity, and a multilayer substrate (1) fixed on the chassis (4) by screws (5). The substrate (1) includes a plurality of laminated insulating layers, and a ground layer or a back surface or both surfaces of the plurality of insulating layers including at least one insulating layer located in the inner layer among the plurality of insulating layers. A plurality of conductor patterns serving as an electric circuit are formed.
ここで、多層基板(1)の表面若しくは背面には、1或いは複数の絶縁層を貫通させて座ぐり部(16)が凹設され、該座ぐり部(16)に前記ビス(5)の頭部(51)が設置されると共に、前記ビス(5)のねじ部(52)が前記シャーシ(4)にねじ込まれ、該ビス(5)の頭部(51)が座ぐり部(16)の底面に露出する導体パターンと接触して、該導体パターンがビス(5)を介してシャーシ(4)と電気的に導通している。 Here, a counterbore part (16) is recessed in the front or back surface of the multilayer substrate (1) through one or a plurality of insulating layers, and the screw (5) is formed in the counterbore part (16). The head (51) is installed, and the screw portion (52) of the screw (5) is screwed into the chassis (4), and the head (51) of the screw (5) is turned into the counterbore portion (16). The conductor pattern is in electrical communication with the chassis (4) through screws (5) in contact with the conductor pattern exposed on the bottom surface of the chassis.
具体的には、前記ビス(5)のねじ部(52)が接触する導体パターンはグランド層を構成すると共に、前記シャーシ(4)がグランド電位部を構成し、該導体パターンがシャーシ(4)に導通することによって、該導体パターンがグランド電位に保たれている。 Specifically, the conductor pattern in contact with the screw portion (52) of the screw (5) constitutes a ground layer, the chassis (4) constitutes a ground potential portion, and the conductor pattern becomes the chassis (4). The conductive pattern is kept at the ground potential by conducting to the ground.
上記本発明の基板取り付け構造によれば、多層基板(1)の座ぐり部(16)の底面に露出する導体パターンが、ビス(5)を介してシャーシ(4)に接続されることなる。ここで、ビス(5)はビアよりも抵抗値が遙かに小さいため、該導体パターンとシャーシ(4)の間には僅かな電圧降下が生じるに過ぎず、この結果、該導体パターンのインピーダンスは充分に下がることなる。
そこで、座ぐり部(16)から露出することとなる絶縁層の露出面に、特にインピーダンスを下げる必要のある導体パターンを形成することによって、特定の内層導体パターンのインピーダンスを下げることが出来る。
According to the substrate mounting structure of the present invention, the conductor pattern exposed on the bottom surface of the spot facing portion (16) of the multilayer substrate (1) is connected to the chassis (4) via the screw (5). Here, since the resistance value of the screw (5) is much smaller than that of the via, there is only a slight voltage drop between the conductor pattern and the chassis (4). As a result, the impedance of the conductor pattern Will drop sufficiently.
Therefore, the impedance of a specific inner layer conductor pattern can be lowered by forming a conductor pattern that needs to lower the impedance particularly on the exposed surface of the insulating layer that is exposed from the spot facing portion (16).
又、多層基板(1)の座ぐり部(16)には、ビス(5)の頭部(51)の全体若しくは一部が収容されるので、該ビス(5)の頭部(51)に沿って部品を配置する場合、多層基板(1)と該部品との隙間を従来よりも小さくすることが出来る。 Further, the counterbore part (16) of the multi-layer substrate (1) accommodates all or part of the head (51) of the screw (5), so that the head (51) of the screw (5) is accommodated. When the components are arranged along the gap, the gap between the multilayer substrate (1) and the components can be made smaller than before.
本発明に係る基板取り付け構造によれば、ビアを増設することなく特定の内層導体パターンのインピーダンスを下げることが出来、然も機器の薄型化を図ることが出来る。 According to the substrate mounting structure of the present invention, the impedance of a specific inner layer conductor pattern can be lowered without adding vias, and the device can be made thinner.
以下、本発明の実施の形態につき、図面に沿って具体的に説明する。
本発明に係る基板取り付け構造においては、図1に示す如く、マグネシウム製のシャーシ(4)に突設したボス部(41)上に、多層基板(1)が設置され、該多層基板(1)は金属製のビス(5)によってシャーシ(4)のボス部(41)にねじ止め固定されている。
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
In the substrate mounting structure according to the present invention, as shown in FIG. 1, a multilayer substrate (1) is installed on a boss portion (41) projecting from a magnesium chassis (4), and the multilayer substrate (1). Is fixed to the boss portion (41) of the chassis (4) with a metal screw (5).
多層基板(1)は、第1絶縁層(11)、第2絶縁層(12)、第3絶縁層(13)、第4絶縁層(14)及び第5絶縁層(15)を積層して構成され、各絶縁層の表面や背面には、グランド層や回路パターンとなる背面導体パターン(20)、第1内層導体パターン(21)、第2内層導体パターン(22)、第3内層導体パターン(23)、第4内層導体パターン(24)及び表面導体パターン(25)が形成されている。又、第1乃至第5絶縁層(11)〜(15)には、ビア(31)〜(35)が形成されて、複数の導体パターン(20)〜(25)を互いに接続している。 The multilayer substrate (1) is formed by laminating a first insulating layer (11), a second insulating layer (12), a third insulating layer (13), a fourth insulating layer (14), and a fifth insulating layer (15). Constructed on the front and back of each insulating layer are a back conductor pattern (20), a first inner conductor pattern (21), a second inner conductor pattern (22), and a third inner conductor pattern, which are ground and circuit patterns. (23) A fourth inner layer conductor pattern (24) and a surface conductor pattern (25) are formed. Further, vias (31) to (35) are formed in the first to fifth insulating layers (11) to (15), and the plurality of conductor patterns (20) to (25) are connected to each other.
多層基板(1)の表面には、第5絶縁層(15)及び第4絶縁層(14)を貫通する座ぐり部(16)が凹設され、該座ぐり部(16)の底面に第3絶縁層(13)上の第3内層導体パターン(23)が露出している。
ビス(5)は、その頭部(51)が多層基板(1)の座ぐり部(16)内に収容されると共に、ねじ部(52)が第3絶縁層(13)、第2絶縁層(12)及び第1絶縁層(11)を貫通して、その先端部がシャーシ(4)のボス部(41)にねじ込まれている。
A counterbore part (16) penetrating the fifth insulating layer (15) and the fourth insulating layer (14) is recessed in the surface of the multilayer substrate (1). The third inner layer conductor pattern (23) on the third insulating layer (13) is exposed.
The screw (5) has a head portion (51) housed in a counterbore portion (16) of the multilayer substrate (1), a screw portion (52) having a third insulating layer (13), and a second insulating layer. (12) and the 1st insulating layer (11) are penetrated, The front-end | tip part is screwed in the boss | hub part (41) of a chassis (4).
これによって、ビス(5)の頭部(51)が第3内層導体パターン(23)と接触し、第3内層導体パターン(23)は、ビス(5)を介して、シャーシ(4)と電気的に導通している。
又、多層基板(1)の表面には、座ぐり部(16)を覆って電池パック(6)が設置されており、多層基板(1)と電池パック(6)との隙間は殆ど零となっている。
As a result, the head (51) of the screw (5) comes into contact with the third inner layer conductor pattern (23), and the third inner layer conductor pattern (23) is electrically connected to the chassis (4) via the screw (5). Is conductive.
Further, a battery pack (6) is installed on the surface of the multilayer substrate (1) so as to cover the spot facing (16), and the gap between the multilayer substrate (1) and the battery pack (6) is almost zero. It has become.
図2は、多層基板(1)の第1乃至第5導体パターン(21)〜(25)に関する等価回路図を表わしている。これらの導体パターン(21)〜(25)には電源(7)が接続され、各絶縁層に形成されているビア(31)〜(35)が、電源(7)のアース側に介在する抵抗R1〜R5となっている。 FIG. 2 is an equivalent circuit diagram relating to the first to fifth conductor patterns (21) to (25) of the multilayer substrate (1). A power source (7) is connected to these conductor patterns (21) to (25), and vias (31) to (35) formed in the respective insulating layers are resistors interposed on the ground side of the power source (7). R1 to R5.
又、図1に示す多層基板(1)の第3内層導体パターン(23)は、ビス(5)を介してシャーシ(4)に接続されており、該ビス(5)が図2に示す如く第3内層導体パターン(23)と電源(7)のアース側に介在する抵抗R1〜R3に対して並列となるバイパス線路の抵抗Rxを構成している。
ビス(5)はビアに比べて遙かに大きな直径を有して、その抵抗値はビアの抵抗値に比べて遙かに小さいので、前記抵抗Rxに生じる電位差は極めて小さく、この結果、第3内層導体パターン(23)のインピーダンスは充分に下がることになる。
Further, the third inner layer conductor pattern (23) of the multilayer substrate (1) shown in FIG. 1 is connected to the chassis (4) through the screws (5), and the screws (5) are connected as shown in FIG. A bypass line resistor Rx is formed in parallel with the resistors R1 to R3 interposed on the ground side of the third inner layer conductor pattern (23) and the power source (7).
The screw (5) has a much larger diameter than the via, and its resistance value is much smaller than the resistance value of the via. Therefore, the potential difference generated in the resistor Rx is extremely small. The impedance of the three inner layer conductor pattern (23) is sufficiently lowered.
そこで、第3内層導体パターン(23)としては、他の導体パターン(21)(22)(24)(25)よりもインピーダンスを下げる必要性の高いものが設定されている。
これによって、例えば第3内層導体パターン(23)がグランド層の場合、多層基板(1)から発生する電磁波に対して高いシールド効果が得られる。又、第3内層導体パターン(23)が回路パターンの場合は、インピーダンスの低下によって回路動作の安定化や電圧降下の減少等の効果が得られる。
Therefore, the third inner layer conductor pattern (23) is set to have a higher necessity of lowering the impedance than the other conductor patterns (21), (22), (24), and (25).
Thus, for example, when the third inner layer conductor pattern (23) is a ground layer, a high shielding effect is obtained against electromagnetic waves generated from the multilayer substrate (1). Further, when the third inner layer conductor pattern (23) is a circuit pattern, effects such as stabilization of circuit operation and reduction of voltage drop can be obtained due to a decrease in impedance.
又、多層基板(1)の座ぐり部(16)にビス(5)の頭部(51)が完全に収容されているため、多層基板(1)と電池パック(6)との隙間は殆ど零となって、電子機器の薄型化を図ることが出来る。 Further, since the head (51) of the screw (5) is completely accommodated in the counterbore (16) of the multilayer substrate (1), there is almost no gap between the multilayer substrate (1) and the battery pack (6). As a result, the thickness of the electronic device can be reduced.
尚、本発明の各部構成は上記実施の形態に限らず、特許請求の範囲に記載の技術的範囲内で種々の変形が可能である。例えばシャーシ(4)としては、全体が金属から形成されているものに限らず、表層部のみが金属製であるものを採用することが可能である。
又、多層基板(1)は、図1に示す如く5層の積層構造を有するものに限らず、2層以上の積層構造を有するものであっても、本発明の効果が得られる。
In addition, each part structure of this invention is not restricted to the said embodiment, A various deformation | transformation is possible within the technical scope as described in a claim. For example, the chassis (4) is not limited to one that is entirely formed of metal, and it is possible to adopt one in which only the surface layer portion is made of metal.
In addition, the multilayer substrate (1) is not limited to the one having a five-layer laminated structure as shown in FIG.
又、多層基板(1)の表面導体パターン(25)や背面導体パターン(20)は省略することが可能であり、複数の内層導体パターン(21)〜(24)についても、少なくとも単一の内層導体パターンが形成されている構成において本発明を実施することが可能である。
更に又、ビア(31)〜(35)は全ての絶縁層に形成する必要はなく、必要最小限の絶縁層に形成すればよい。
Further, the surface conductor pattern (25) and the back conductor pattern (20) of the multilayer substrate (1) can be omitted, and the plurality of inner layer conductor patterns (21) to (24) are at least a single inner layer. The present invention can be implemented in a configuration in which a conductor pattern is formed.
Furthermore, the vias (31) to (35) need not be formed in all the insulating layers, but may be formed in the minimum necessary insulating layer.
(1) 多層基板
(11) 第1絶縁層
(12) 第2絶縁層
(13) 第3絶縁層
(14) 第4絶縁層
(15) 第5絶縁層
(16) 座ぐり部
(21) 第1内層導体パターン
(22) 第2内層導体パターン
(23) 第3内層導体パターン
(24) 第4内層導体パターン
(25) 表面導体パターン
(4) シャーシ
(41) ボス部
(5) ビス
(51) 頭部
(52) ねじ部
(6) 電池パック
(1) Multilayer substrate
(11) First insulation layer
(12) Second insulation layer
(13) Third insulation layer
(14) Fourth insulation layer
(15) Fifth insulating layer
(16) Counterbore
(21) First inner layer conductor pattern
(22) Second inner layer conductor pattern
(23) Third inner layer conductor pattern
(24) 4th inner layer conductor pattern
(25) Surface conductor pattern
(4) Chassis
(41) Boss
(5) Screw
(51) Head
(52) Screw
(6) Battery pack
Claims (3)
多層基板(1)の表面若しくは背面には、1或いは複数の絶縁層を貫通させて座ぐり部(16)が凹設され、該座ぐり部(16)に前記ビス(5)の頭部(51)が設置されると共に、前記ビス(5)のねじ部(52)が前記シャーシ(4)にねじ込まれ、該ビス(5)の頭部(51)が座ぐり部(16)の底面に露出する導体パターンと接触して、該導体パターンがビス(5)を介してシャーシ(4)と電気的に導通していることを特徴とする基板取り付け構造。 A chassis (4) having at least a surface layer portion having conductivity and a multilayer substrate (1) fixed on the chassis (4) by screws (5) are formed. The multilayer substrate (1) is laminated. A plurality of conductor patterns that comprise a plurality of insulating layers and that are ground layers or electrical circuits are provided on the front surface, back surface, or both surfaces of the plurality of insulating layers including at least one insulating layer located in the inner layer among the plurality of insulating layers. In the board mounting structure being formed,
A counterbore part (16) is recessed in the front surface or the back surface of the multilayer substrate (1) through one or a plurality of insulating layers, and the head part (16) of the screw (5) is formed in the counterbore part (16). 51) is installed, the screw portion (52) of the screw (5) is screwed into the chassis (4), and the head portion (51) of the screw (5) is placed on the bottom surface of the counterbore portion (16). A board mounting structure, wherein the conductive pattern comes into contact with an exposed conductive pattern and is electrically connected to the chassis (4) through a screw (5).
Priority Applications (1)
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JP2008020732A JP2009182204A (en) | 2008-01-31 | 2008-01-31 | Substrate fitting structure |
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JP2008020732A JP2009182204A (en) | 2008-01-31 | 2008-01-31 | Substrate fitting structure |
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JP2009182204A true JP2009182204A (en) | 2009-08-13 |
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JP2008020732A Pending JP2009182204A (en) | 2008-01-31 | 2008-01-31 | Substrate fitting structure |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20220042712A (en) * | 2020-09-28 | 2022-04-05 | 주식회사 디아이티 | Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000299577A (en) * | 1999-04-14 | 2000-10-24 | Nec Corp | Structure and method for mounting printed wiring board |
-
2008
- 2008-01-31 JP JP2008020732A patent/JP2009182204A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000299577A (en) * | 1999-04-14 | 2000-10-24 | Nec Corp | Structure and method for mounting printed wiring board |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20220042712A (en) * | 2020-09-28 | 2022-04-05 | 주식회사 디아이티 | Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same |
KR102466911B1 (en) * | 2020-09-28 | 2022-11-14 | 주식회사 디아이티 | Multilayer ceramic substrate having connecting means with frame and method of manufacturing the same |
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