JP2009158912A - パッケージ用基板及びその製造方法 - Google Patents
パッケージ用基板及びその製造方法 Download PDFInfo
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- JP2009158912A JP2009158912A JP2008178311A JP2008178311A JP2009158912A JP 2009158912 A JP2009158912 A JP 2009158912A JP 2008178311 A JP2008178311 A JP 2008178311A JP 2008178311 A JP2008178311 A JP 2008178311A JP 2009158912 A JP2009158912 A JP 2009158912A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09481—Via in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49204—Contact or terminal manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24851—Intermediate layer is discontinuous or differential
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】 本発明に係るパッケージ用基板及びその製造方法は、(a)第1金属層に、ホールが形成されている第2金属層を積層する段階と、(b)前記ホールかた露出した前記第1金属層と前記第2金属層とにベリア層を積層する段階と、(c)前記ホールの内部を導電性金属を充填してバンプを形成する段階と、(d)前記バンプの上面に絶縁層を積層し、前記絶縁層に回路パターンを形成する段階と、(e)前記第1金属層、前記第2金属層及び前記ベリア層を除去する段階と、を含むことを特徴とする。
【選択図】図1
Description
212 キャリア板
22 第2金属層
23 ベリア層
24 バンプ
25 バット
26 絶縁層
27 オープン部
28 表面処理層
Claims (7)
- (a)第1金属層に、ホールが形成されている第2金属層を積層する段階と、
(b)前記ホールから露出した前記第1金属層と、前記第2金属層とにベリア層(barrier layer)を積層する段階と、
(c)前記ホールの内部に導電性金属を充填してバンプを形成する段階と、
(d)前記バンプの上面に絶縁層を積層し、 前記絶縁層に回路パターンを形成する段階と、
(e)前記第1金属層、 前記第2金属層、及び前記ベリア層を除去する段階と、
を含むパッケージ用基板の製造方法。 - (f)キャリア板の両面に、縁が接着されるようにして第1金属層を積層する段階と、
(g)前記第1金属層に、ホールが形成されている第2金属層を積層する段階と、
(h)前記ホールから露出した前記第1金属層と、 前記第2金属層とにベリア層を積層する段階と、
(i)前記ホールの内部に導電性金属を充填してバンプを形成する段階と、
(j)前記バンプの上面に絶縁層を積層し、 前記絶縁層に回路パターンを形成する段階と、
(k)前記キャリア板と前記第1金属層を分離する段階と、
(l)前記第1金属層、 前記第2金属層及び前記ベリア層を除去する段階と、
を含むパッケージ用基板の製造方法。 - 前記第2金属層はNiからなることを特徴とする請求項1または2に記載のパッケージ用基板の製造方法。
- 前記ベリア層は、TiまたはCrの何れか一つであることを特徴とするパッケージ用基板の請求項1または2に記載のパッケージ用基板の製造方法 。
- 前記絶縁層はソルダーレジストであることを特徴とする 請求項1または2に記載のパッケージ用基板の製造方法。
- 平坦な表面のソルダーレジスト層と、
前記ソルダーレジスト層に含浸された回路パターンと、
前記ソルダーレジスト層から突出されたバンプと、
を含むパッケージ用基板。 - 前記バンプには表面処理層が積層されたことを特徴とする請求項6に記載のパッケージ用基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2007-0137663 | 2007-12-26 | ||
KR1020070137663A KR100992181B1 (ko) | 2007-12-26 | 2007-12-26 | 패키지용 기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009158912A true JP2009158912A (ja) | 2009-07-16 |
JP4982779B2 JP4982779B2 (ja) | 2012-07-25 |
Family
ID=40798815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008178311A Expired - Fee Related JP4982779B2 (ja) | 2007-12-26 | 2008-07-08 | パッケージ用基板の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US8499444B2 (ja) |
JP (1) | JP4982779B2 (ja) |
KR (1) | KR100992181B1 (ja) |
TW (1) | TWI484605B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103906341A (zh) * | 2012-12-24 | 2014-07-02 | 深圳市共进电子股份有限公司 | 防止包装印刷电路板的密封袋破损的方法及印刷电路板 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5147779B2 (ja) * | 2009-04-16 | 2013-02-20 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体パッケージの製造方法 |
US20110048786A1 (en) * | 2009-08-31 | 2011-03-03 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board having a bump and a method of manufacturing the same |
CN103474401B (zh) * | 2012-06-06 | 2016-12-14 | 欣兴电子股份有限公司 | 载板结构与芯片封装结构及其制作方法 |
US9171739B1 (en) | 2014-06-24 | 2015-10-27 | Stats Chippac Ltd. | Integrated circuit packaging system with coreless substrate and method of manufacture thereof |
JP2016134409A (ja) * | 2015-01-16 | 2016-07-25 | イビデン株式会社 | プリント配線板 |
US10566103B2 (en) * | 2016-01-08 | 2020-02-18 | Lilotree, L.L.C. | Printed circuit surface finish, method of use, and assemblies made therefrom |
CN109337418A (zh) * | 2018-11-09 | 2019-02-15 | 北京航星机器制造有限公司 | 用于超塑成形/扩散连接的阻焊剂、配制方法及使用方法 |
CN114073171B (zh) * | 2019-08-20 | 2024-08-20 | 华为技术有限公司 | 线路嵌入式基板、芯片封装结构及基板制备方法 |
Citations (8)
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JPH06216195A (ja) * | 1992-10-09 | 1994-08-05 | Sumitomo Kinzoku Ceramics:Kk | バンプ付セラミックス基板 |
JPH11162601A (ja) * | 1997-11-27 | 1999-06-18 | Texas Instr Japan Ltd | ソケット |
JP2000294675A (ja) * | 1999-04-02 | 2000-10-20 | Toppan Printing Co Ltd | チップキャリア及び半導体装置並びにチップキャリアの製造方法 |
JP2003309215A (ja) * | 2002-02-15 | 2003-10-31 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005079493A (ja) * | 2003-09-03 | 2005-03-24 | Fujitsu Ltd | 薄膜多層基板及びその製造方法 |
JP2006148031A (ja) * | 2004-11-25 | 2006-06-08 | Sumitomo Metal Electronics Devices Inc | 高周波用プラスチックパッケージとその製造方法 |
JP2006196860A (ja) * | 2004-12-16 | 2006-07-27 | Shinko Electric Ind Co Ltd | 半導体パッケージ及びその製造方法 |
JP2007311713A (ja) * | 2006-05-22 | 2007-11-29 | Hitachi Cable Ltd | 電子装置用基板およびその製造方法、ならびに電子装置およびその製造方法 |
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US5072520A (en) * | 1990-10-23 | 1991-12-17 | Rogers Corporation | Method of manufacturing an interconnect device having coplanar contact bumps |
KR100244580B1 (ko) * | 1997-06-24 | 2000-02-15 | 윤종용 | 금속 범프를 갖는 회로 기판의 제조 방법 및 그를 이용한 반도체 칩 패키지의 제조 방법 |
JP3949849B2 (ja) * | 1999-07-19 | 2007-07-25 | 日東電工株式会社 | チップサイズパッケージ用インターポーザーの製造方法およびチップサイズパッケージ用インターポーザー |
TWI247369B (en) | 2000-08-11 | 2006-01-11 | Taiwan Semiconductor Mfg | Forming method of conductive bump |
KR100674319B1 (ko) * | 2004-12-02 | 2007-01-24 | 삼성전기주식회사 | 얇은 코어층을 갖는 인쇄회로기판 제조방법 |
KR20100025597A (ko) * | 2005-05-23 | 2010-03-09 | 이비덴 가부시키가이샤 | 프린트 배선판 |
JP5021472B2 (ja) | 2005-06-30 | 2012-09-05 | イビデン株式会社 | プリント配線板の製造方法 |
-
2007
- 2007-12-26 KR KR1020070137663A patent/KR100992181B1/ko not_active IP Right Cessation
-
2008
- 2008-06-30 US US12/216,152 patent/US8499444B2/en not_active Expired - Fee Related
- 2008-07-07 TW TW097125616A patent/TWI484605B/zh not_active IP Right Cessation
- 2008-07-08 JP JP2008178311A patent/JP4982779B2/ja not_active Expired - Fee Related
-
2013
- 2013-07-30 US US13/954,442 patent/US20130313004A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06216195A (ja) * | 1992-10-09 | 1994-08-05 | Sumitomo Kinzoku Ceramics:Kk | バンプ付セラミックス基板 |
JPH11162601A (ja) * | 1997-11-27 | 1999-06-18 | Texas Instr Japan Ltd | ソケット |
JP2000294675A (ja) * | 1999-04-02 | 2000-10-20 | Toppan Printing Co Ltd | チップキャリア及び半導体装置並びにチップキャリアの製造方法 |
JP2003309215A (ja) * | 2002-02-15 | 2003-10-31 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP2005079493A (ja) * | 2003-09-03 | 2005-03-24 | Fujitsu Ltd | 薄膜多層基板及びその製造方法 |
JP2006148031A (ja) * | 2004-11-25 | 2006-06-08 | Sumitomo Metal Electronics Devices Inc | 高周波用プラスチックパッケージとその製造方法 |
JP2006196860A (ja) * | 2004-12-16 | 2006-07-27 | Shinko Electric Ind Co Ltd | 半導体パッケージ及びその製造方法 |
JP2007311713A (ja) * | 2006-05-22 | 2007-11-29 | Hitachi Cable Ltd | 電子装置用基板およびその製造方法、ならびに電子装置およびその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103906341A (zh) * | 2012-12-24 | 2014-07-02 | 深圳市共进电子股份有限公司 | 防止包装印刷电路板的密封袋破损的方法及印刷电路板 |
Also Published As
Publication number | Publication date |
---|---|
US8499444B2 (en) | 2013-08-06 |
KR100992181B1 (ko) | 2010-11-04 |
TWI484605B (zh) | 2015-05-11 |
JP4982779B2 (ja) | 2012-07-25 |
KR20090069852A (ko) | 2009-07-01 |
US20090169837A1 (en) | 2009-07-02 |
TW200929474A (en) | 2009-07-01 |
US20130313004A1 (en) | 2013-11-28 |
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