JP2008532271A - 原子層堆積のための表面のプラズマ前処理 - Google Patents
原子層堆積のための表面のプラズマ前処理 Download PDFInfo
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- JP2008532271A JP2008532271A JP2007556376A JP2007556376A JP2008532271A JP 2008532271 A JP2008532271 A JP 2008532271A JP 2007556376 A JP2007556376 A JP 2007556376A JP 2007556376 A JP2007556376 A JP 2007556376A JP 2008532271 A JP2008532271 A JP 2008532271A
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- Prior art keywords
- plasma
- layer
- trench
- barrier
- barrier layer
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- 239000010949 copper Substances 0.000 claims description 41
- 238000009832 plasma treatment Methods 0.000 claims description 41
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- 229910052802 copper Inorganic materials 0.000 claims description 38
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 5
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- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/02—Pretreatment of the material to be coated
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/36—Carbonitrides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45531—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making ternary or higher compositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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Abstract
【選択図】図3
Description
本明細書において特定される所望の利益のうちの何れかを達成するのに十分な条件の下で、層のプラズマプロセスが遂行される。いくつかの実施形態では、kの低い絶縁体の表面でプラズマプロセスが実行され、絶縁物質の表面からプラズマ処理された表面を作成する。しかしながら、物質は絶縁物質に制限される必要はない。好ましい実施形態では、プラズマプロセスが、そのような物質に対する追加の利点を有すると信じられているので、物質は多孔性物質である。しかしながら、表面(例えば、High−又はLow−k、ウルトラLow−k(ULK)、エクストリームLow−k(ELK)、多孔性か否か、絶縁体か否か)のプラズマ処理は、最適化された条件の下で、本明細書に記述された優れた側面のうちの少なくともいくつかに帰着し得ると信じられている。本明細書において特定される改善された特性を実証するように、「プラズマ処理された層」は、絶縁物質の表面から作成されるが、未処理の絶縁物質の残りとは異なる。このプラズマ処理された層は、その後、原子層堆積(ALD)プロセスによって堆積され得るバリア層によってカバーされ得る。
絶縁層
図5〜8を参照すると、半導体基板を覆って絶縁層が形成される。当該技術における熟練者によって認識されるであろうが、そのような絶縁層を形成および処理することが可能な様々な方法がある。他に指摘されなければ、これは発明の範囲を制限することなく、絶縁体の形成及び処理の任意の方法又は技術が使用され得る。
図3に示されるように、形成100の後、kの低い物質(本実施形態ではビア及びトレンチの側壁を少なくとも含む)の表面が、kの低い絶縁層の表面を変更するプラズマ処理プロセス101にさらされる。好ましくは、プラズマ処理101はH2/Heプラズマ処理を含む。このステップの詳細な議論は以上に提供され、また、実施例はさらに以下に提供される。上記したように、いくつかの実施形態では、プラズマ処理は、改善された界面のために、後続のALDバリアを用いてトレンチの絶縁側面を処理するだけでなく、ビアの底の金属酸化膜を還元することもできる。好ましくは、その処理は等方性である。
プラズマプロセスに続いて、その後、ALDプロセスが、プラズマ処理された絶縁層の上面に直接実行される。好ましくは、各々のサイクルは、吸着によって、好ましくは化学吸着によって、ライニング物質のわずか1つの単分子層を形成する。基板温度は、化学吸着を促進する領域内に保持される。特に、基板温度は、吸着種と下層にある表面との間の完全な結合を維持し、反応性種の分解を防ぐのに十分に低い温度に維持される。他方では、基板温度は、反応物の凝縮を回避し、各段階での所望の表面反応に活性化エネルギーを供給するのに十分に高いレベルに維持される。もちろん、任意の与えられたALD反応に対する適切な温度領域は、表面の終端化及び関連する反応性種に依存するであろう。
プラズマ処理された絶縁表面上に形成されたWNxCyバリア層は、十分な、あるいは任意のプラズマプロセスが処理されなかった絶縁層上に配置された同様のバリア層と比較して、いくつかの改善されたバリア特性を実証した。次のセクションは、これら改善された特性、これら改善された特性を有する回路に帰着する方法、およびそのような方法を用いて形成された回路について議論する。一般に、回路の最適化は、様々なバリアを有する、プラズマ処理がされたあるいはされない、および異なるプラズマ処理がされた様々な回路の、直接の比較を通じて行われ得る。
トレンチ及びビアが、パターニング及びエッチングにより、シロキサン絶縁層内に形成された。真空の破壊に引き続き、トレンチ及びビアが形成された絶縁表面が、所望の特性(例えば、未処理の絶縁層上のバリアと比較して、改善されたバリア特性)に帰着するのに十分な期間、この実施例では約10秒間、H2およびHeプラズマ処理にさらされる。これに引き続き、ALDの60回のサイクルによって、約40オングストロームの厚さのWNxCyバリアが形成された。代替の実施形態では、バリア層は、例えば約30〜50オングストローム又は35〜45オングストロームの厚さに、より厚くもあるいはより薄くもなり得る。もう一回の真空の破壊に引き続き、約800オングストロームの厚さの銅のシード層が、PVDによりその層に追加された。これに引き続き、トレンチ及びビア内へ、銅層が電気めっきされた。このバリアは、以下でより詳細に議論される結果および比較において、「バリア1」あるいは「バリア1A」として識別される。代替の実施形態では、ステップ間に真空の破壊はない。これは、例えば、クラスターツール(例えば、オランダ国BilthovenのASMインターナショナルN.V.製のPOLYGON(登録商標))の使用を通じた様々な方法で達成され得る。代替の実施形態では、上記方法のために特別に設計された装置が使用される。例えば、その装置は、インシチュプラズマプロセス用のチャンバ、ALDプロセス用の別のチャンバ、および銅の蒸着ステップ用の第3のチャンバを持つことができる。その装置は、真空状態のチャンバ間の転送を可能にし、したがって、ステップ間の任意の表面の偶発的な酸化の危険性はない。これは、様々な方法、例えば、転送チャンバの形式でチャンバ間の空間を取り込み、シーケンシャルプロセス用の複数のチャンバ間を基板が移動する間、転送チャンバを真空状態に維持する方法で達成され得る。あるいは、ステップの各々が実行される前に、装置が減圧ステップを実行してもよい。
結果的に得られるプラズマ処理された絶縁層が、改善された特性を有するかどうかを調べるための比較は、さらに、He/H2プラズマ処理された回路と、代替の集積回路(例えば、異なるプラズマ、プラズマなし、異なるバリア層等で処理された回路)との比較を必要とした。以降の段落は、プラズマ処理された回路と比較される様々な回路のうちのいくつかを簡潔に説明する。
金属窒化物バリア層の形成の後、デュアルダマシン構造の埋め込みおよび堆積されたバリア層の導電率のために採用される方法に依存して、シード層が望まれてもよい。埋め込み銅は、望ましくは、図示する金属窒化物バリアを覆って電気めっきされる。従って、高導電性のシード層が、バリア層を覆って好ましくは最初に形成される。
図9aのデュアルダマシン構造は、典型的な回路の記述のための出発点として役立つことができる。表面は、最初にプラズマ(例えばH2/He、図17A)で十分に処理され、絶縁層56及び50の外部表面から形成されているプラズマ処理層148になる。プラズマ処理層148(プラズマによって変更された絶縁物質の層)は、絶縁層の上面上に堆積されたバリア層の不規則性を低減する。図17Aは埋め込みハードマスク/エッチング停止層54を図示せず、CMP停止層58もまた図9Aに示されていない。先に述べたように、いくつかの実施形態では、トレンチ及びビアは単一の絶縁層内に画定されることができる。例えば、トレンチ及びビアはVFTLアプローチにより形成され得る。
Claims (55)
- 半導体基板上のkの低い絶縁層内に、所望の相互接続パターンでトレンチを形成するステップと、
プラズマプロセスを実施されていないトレンチの表面に結合されるバリア層と比較して、バリア層のバリア特性を改善するのに十分な条件の下で、前記トレンチの露出する表面を前記プラズマプロセスで処理するステップと、
前記トレンチの露出する表面を前記プラズマプロセスで処理するステップの後に、原子層堆積(ALD)プロセスにより、前記トレンチの前記表面を前記バリア層でライニングするステップとを含むメタライゼーション・プロセス。 - 前記バリア層を覆う銅のシード層を堆積するステップをさらに含む請求項1のプロセス。
- 前記kの低い絶縁層内に、前記トレンチと通じるビアを形成するステップをさらに含む請求項1のプロセス。
- 前記プラズマプロセスが、He/H2プラズマプロセスである請求項1のプロセス。
- 前記トレンチを形成する前記ステップと前記プラズマプロセスとの間に、前記トレンチが酸化されない請求項4のプロセス。
- 前記He/H2プラズマプロセスの前に、酸化物除去プロセスで、下部導電素子の露出する部分をさらに処理し、金属酸化物を還元するステップをさらに含む請求項4のプロセス。
- 前記プラズマプロセスが、He/H2プラズマプロセスであり、該He/H2プラズマプロセスが、トレンチ側壁を処理する間に、下部導電素子から酸化物を還元し、前記バリア特性を改善する請求項1のプロセス。
- 前記改善されたバリア特性が、前記プロセスにより形成された回路について、0.1%未満の累積故障リスクでの使用の10年より長い延長された寿命である請求項1のプロセス。
- 前記延長された寿命が約17年である請求項8のプロセス。
- 前記プラズマプロセスが、250〜350℃でのHe/H2プラズマプロセスを含む請求項1のプロセス。
- 前記相互接続パターンが、それ自身の底で導体を露出させるビアを含み、前記改善されたバリア特性が、前記プラズマプロセスがなされていないビアよりも、低いビアチェーン抵抗である請求項1のプロセス。
- 前記低いビアチェーン抵抗が、前記He/H2プラズマプロセスの欠如を除いて同一のプロセスによるトレンチ内のビア内の抵抗よりも、約1%〜約20%低い請求項11のプロセス。
- 前記改善されたバリア特性が、前記バリア層のより一様な抵抗である請求項1のプロセス。
- 前記改善されたバリア特性が、エレクトロマイグレーションにおける改善された故障時間である請求項1のプロセス。
- 前記バリア特性を改善するのに十分な前記条件が、露出時間の総量を含み、前記露出する表面が5〜20秒の間処理される請求項1のプロセス。
- 前記バリア特性を改善するのに十分な前記条件が、13.5MHzで100〜200Wで生成されたプラズマを含む請求項1のプロセス。
- 前記バリア特性を改善するのに十分な前記条件が、10〜160部のH2に対して190〜40部のHeを含むプラズマを含む請求項1のプロセス。
- 前記バリア層が、タングステン、窒素、および炭素を含む請求項1のプロセス。
- 前記バリア層が、約35〜45オングストロームの厚さになるように堆積される請求項18のプロセス。
- 前記バリア層が、本質的にWNxCyから構成される請求項18のプロセス。
- 物理気相蒸着法(PVD)プロセスにより、前記バリア層上に銅のシード層を蒸着するステップをさらに含む請求項20のプロセス。
- 前記絶縁層が、Low−kのシロキサンポリマーを含む請求項1のプロセス。
- 前記プラズマプロセスが、前記トレンチの前記露出する表面へプラズマ生成物を供給するステップを含み、該プラズマ生成物がリモートに生成される請求項1のプロセス。
- 有効なバリア層を形成する際に、30〜60回のALDサイクルが実行される請求項1のプロセス。
- 前記トレンチの前記露出する表面が、エッチング停止層あるいはCMP停止層を含まない請求項1のプロセス。
- 絶縁層内にビアを形成するステップをさらに含み、前記トレンチ及びビアが、ビア−ファースト・トレンチ−ラスト(VFTL)プロセスにより形成される請求項1のプロセス。
- 前記kの低い絶縁層が、埋め込みエッチング停止層を含む請求項1のプロセス。
- 半導体基板上の絶縁層内に、所望の配線パターンに形成されたトレンチと、
前記トレンチの底から下方へ伸びて、下部導電素子の少なくとも一部を露出させるコンタクトビアと、
前記トレンチの表面上に直接形成された、タングステン、窒素、および炭素を含むバリア層と、
前記バリア層に付着する銅層とを備える集積回路。 - 前記回路が、110℃および5.5×105Å/cm2の電流密度の使用条件で、10年より長い期間0.1%の累積故障リスクを有する請求項28の回路。
- 前記絶縁層が、kの低い物質を含む請求項28の回路。
- 前記kの低い物質が、Low−k物質、ウルトラLow−k物質、エクストリームLow−k物質、およびシロキサンポリマー絶縁フィルムからなる群から選択される請求項30の回路。
- 前記kの低い物質が、多孔性かつ約3.3未満の誘電率を有する請求項31の回路。
- 前記kの低い物質が、−SiR2O−の繰り返し構造単位を有する請求項31の回路。
- 前記バリア層の厚さの標準偏差が、約1%である請求項28の回路。
- 前記バリア層が、約20〜60オングストロームの厚さである請求項34の回路。
- 前記バリア層が、約95%より高いステップカバレッジを有する請求項28の回路。
- 前記絶縁層が、一般式SiαOβCxHy(ここでa、β、xおよびyは整数である)のシリコン含有炭化水素化合物である請求項28の回路。
- 基板上の絶縁表面のインシチュプラズマプロセス用に設定された第1のチャンバと、
金属窒化物炭化物バリア物質の原子層堆積用に設定された第2のチャンバと、
前記金属窒化物炭化物物質にシード層を適用するために設定された第3のチャンバと、
前記第1、第2および第3のチャンバ間の空間であって、該空間が、該空間内において前記基板が前記第1、第2および第3のチャンバ間を移動することを可能にし、前記チャンバ間の転送の間、前記第1、第2および第3のチャンバ間の前記空間が真空を維持するように設定された空間とを備えるメタライゼーションのために設定されたクラスターツール。 - 前記第3のチャンバに操作可能に接続された銅のソースをさらに備える請求項38のクラスターツール。
- 前記第2のチャンバに操作可能に接続された、窒素のソースと炭素のソースとをさらに備える請求項38のクラスターツール。
- 前記第2のチャンバに操作可能に接続された金属のソースをさらに備える請求項40のクラスターツール。
- 前記金属のソースが、タングステンを含む請求項41のクラスターツール。
- 絶縁層の表面をプラズマ処理するステップであり、前記プラズマ処理が、前記表面を処理するための還元プラズマの使用を含むステップと、
前記絶縁層の前記表面をプラズマ処理するステップの後に、原子層堆積(ALD)により堆積された、金属、炭素、および窒素を含むバリア層で、前記表面をライニングするステップとを含み、前記バリア層の厚さの標準偏差が、前記バリアの前記厚さの平均の約5%未満である点で、前記表面と前記バリア層との間の界面が比較的一様である集積回路作製方法。 - 前記バリア層を覆う電気化学堆積シード層を形成するステップをさらに含む請求項43の方法。
- 前記金属がタングステンである請求項43の方法。
- 前記還元プラズマが、H2およびHeから形成されたプラズマを含む請求項43の方法。
- 前記プラズマが、10〜160部のH2に対して190〜40部のHeを含む請求項46の方法。
- 前記プラズマにより処理されることになっている前記表面を含む前記層が、kの低い絶縁物質を含む請求項43の方法。
- 前記絶縁物質が、フッ素化ケイ酸塩ガラス、テトラエチルオルソシリケート、および多孔性の絶縁物質からなる群から少なくとも1つ選択される請求項43の方法。
- 前記バリア層の厚さの前記標準偏差が、前記バリアの前記厚さの前記平均の約1%未満である請求項43の方法。
- プラズマ処理された前記表面が、ビアの表面およびトレンチの表面である請求項44の方法。
- プラズマ処理された前記表面が、ダマシントレンチの表面である請求項45の方法。
- 前記回路が、0.1%未満の累積故障リスクでの使用の10年より長い延長された寿命を有する請求項52の方法。
- 前記プラズマ処理で作製される回路が、前記プラズマ処理なしで作製される回路よりも優れたバリア特性を持つように、前記プラズマ処理が十分に実行され、他の点では同じプロセスによって、2つの前記回路が作製される請求項43の方法。
- 前記プラズマ処理で作製される回路が、前記プラズマ処理なしで作製される回路よりも低い抵抗性を持つように、前記プラズマ処理が十分に実行され、他の点では同じプロセスによって、2つの前記回路が作製される請求項43の方法。
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US7498242B2 (en) | 2009-03-03 |
EP1851794A1 (en) | 2007-11-07 |
US20060216932A1 (en) | 2006-09-28 |
TW200634982A (en) | 2006-10-01 |
KR20070108918A (ko) | 2007-11-13 |
WO2006091510A1 (en) | 2006-08-31 |
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